jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/tricore: Implement gdbstub
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20200529072148.284037-6-kbastian@mail.uni-paderborn.de>
+152
-1
+1
-1
target/tricore/Makefile.objs
+1
-1
target/tricore/Makefile.objs
+10
target/tricore/cpu.c
+10
target/tricore/cpu.c
···
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env->features |= 1ULL << feature;
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}
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static gchar *tricore_gdb_arch_name(CPUState *cs)
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{
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return g_strdup("tricore");
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}
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+
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static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
···
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device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset);
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cc->class_by_name = tricore_cpu_class_by_name;
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cc->has_work = tricore_cpu_has_work;
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cc->gdb_read_register = tricore_cpu_gdb_read_register;
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cc->gdb_write_register = tricore_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 44;
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cc->gdb_arch_name = tricore_gdb_arch_name;
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cc->dump_state = tricore_cpu_dump_state;
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cc->set_pc = tricore_cpu_set_pc;
+2
target/tricore/cpu.h
+2
target/tricore/cpu.h
···
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uint32_t psw_read(CPUTriCoreState *env);
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void psw_write(CPUTriCoreState *env, uint32_t val);
356
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int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
357
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int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
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void fpu_set_state(CPUTriCoreState *env);
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+139
target/tricore/gdbstub.c
+139
target/tricore/gdbstub.c
···
1
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/*
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* TriCore gdb server stub
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*
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* Copyright (c) 2019 Bastian Koppelmann, Paderborn University
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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+
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+
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#define LCX_REGNUM 32
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#define FCX_REGNUM 33
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#define PCXI_REGNUM 34
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#define TRICORE_PSW_REGNUM 35
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#define TRICORE_PC_REGNUM 36
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#define ICR_REGNUM 37
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#define ISP_REGNUM 38
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#define BTV_REGNUM 39
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#define BIV_REGNUM 40
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#define SYSCON_REGNUM 41
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#define PMUCON0_REGNUM 42
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#define DMUCON_REGNUM 43
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static uint32_t tricore_cpu_gdb_read_csfr(CPUTriCoreState *env, int n)
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{
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switch (n) {
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case LCX_REGNUM:
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return env->LCX;
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case FCX_REGNUM:
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return env->FCX;
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case PCXI_REGNUM:
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return env->PCXI;
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case TRICORE_PSW_REGNUM:
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return psw_read(env);
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case TRICORE_PC_REGNUM:
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return env->PC;
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case ICR_REGNUM:
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return env->ICR;
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case ISP_REGNUM:
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return env->ISP;
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case BTV_REGNUM:
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return env->BTV;
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case BIV_REGNUM:
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return env->BIV;
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case SYSCON_REGNUM:
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return env->SYSCON;
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case PMUCON0_REGNUM:
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return 0; /* PMUCON0 */
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case DMUCON_REGNUM:
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return 0; /* DMUCON0 */
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default:
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return 0;
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}
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}
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static void tricore_cpu_gdb_write_csfr(CPUTriCoreState *env, int n,
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uint32_t val)
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{
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switch (n) {
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case LCX_REGNUM:
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env->LCX = val;
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break;
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case FCX_REGNUM:
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env->FCX = val;
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break;
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case PCXI_REGNUM:
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env->PCXI = val;
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break;
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case TRICORE_PSW_REGNUM:
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psw_write(env, val);
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break;
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case TRICORE_PC_REGNUM:
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env->PC = val;
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break;
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case ICR_REGNUM:
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env->ICR = val;
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break;
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case ISP_REGNUM:
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env->ISP = val;
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break;
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case BTV_REGNUM:
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env->BTV = val;
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break;
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case BIV_REGNUM:
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env->BIV = val;
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break;
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case SYSCON_REGNUM:
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env->SYSCON = val;
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break;
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}
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}
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int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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if (n < 16) { /* data registers */
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return gdb_get_reg32(mem_buf, env->gpr_d[n]);
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} else if (n < 32) { /* address registers */
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return gdb_get_reg32(mem_buf, env->gpr_a[n - 16]);
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} else { /* csfr */
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return gdb_get_reg32(mem_buf, tricore_cpu_gdb_read_csfr(env, n));
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}
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return 0;
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}
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int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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TriCoreCPU *cpu = TRICORE_CPU(cs);
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CPUTriCoreState *env = &cpu->env;
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uint32_t tmp;
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+
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tmp = ldl_p(mem_buf);
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if (n < 16) { /* data registers */
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env->gpr_d[n] = tmp;
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} else if (n < 32) { /* address registers */
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env->gpr_d[n - 16] = tmp;
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} else {
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tricore_cpu_gdb_write_csfr(env, n, tmp);
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}
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return 4;
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}