qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

hw/arm/smmu-common: IOMMU memory region and address space setup

We set up the infrastructure to enumerate all the PCI devices
attached to the SMMU and create an associated IOMMU memory
region and address space.

Those info are stored in SMMUDevice objects. The devices are
grouped according to the PCIBus they belong to. A hash table
indexed by the PCIBus pointer is used. Also an array indexed by
the bus number allows to find the list of SMMUDevices.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1524665762-31355-3-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

authored by

Eric Auger and committed by
Peter Maydell
cac994ef 527773ee

+80
+69
hw/arm/smmu-common.c
··· 28 28 #include "qemu/error-report.h" 29 29 #include "hw/arm/smmu-common.h" 30 30 31 + /** 32 + * The bus number is used for lookup when SID based invalidation occurs. 33 + * In that case we lazily populate the SMMUPciBus array from the bus hash 34 + * table. At the time the SMMUPciBus is created (smmu_find_add_as), the bus 35 + * numbers may not be always initialized yet. 36 + */ 37 + SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num) 38 + { 39 + SMMUPciBus *smmu_pci_bus = s->smmu_pcibus_by_bus_num[bus_num]; 40 + 41 + if (!smmu_pci_bus) { 42 + GHashTableIter iter; 43 + 44 + g_hash_table_iter_init(&iter, s->smmu_pcibus_by_busptr); 45 + while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) { 46 + if (pci_bus_num(smmu_pci_bus->bus) == bus_num) { 47 + s->smmu_pcibus_by_bus_num[bus_num] = smmu_pci_bus; 48 + return smmu_pci_bus; 49 + } 50 + } 51 + } 52 + return smmu_pci_bus; 53 + } 54 + 55 + static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) 56 + { 57 + SMMUState *s = opaque; 58 + SMMUPciBus *sbus = g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus); 59 + SMMUDevice *sdev; 60 + 61 + if (!sbus) { 62 + sbus = g_malloc0(sizeof(SMMUPciBus) + 63 + sizeof(SMMUDevice *) * SMMU_PCI_DEVFN_MAX); 64 + sbus->bus = bus; 65 + g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus); 66 + } 67 + 68 + sdev = sbus->pbdev[devfn]; 69 + if (!sdev) { 70 + char *name = g_strdup_printf("%s-%d-%d", 71 + s->mrtypename, 72 + pci_bus_num(bus), devfn); 73 + sdev = sbus->pbdev[devfn] = g_new0(SMMUDevice, 1); 74 + 75 + sdev->smmu = s; 76 + sdev->bus = bus; 77 + sdev->devfn = devfn; 78 + 79 + memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), 80 + s->mrtypename, 81 + OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); 82 + address_space_init(&sdev->as, 83 + MEMORY_REGION(&sdev->iommu), name); 84 + trace_smmu_add_mr(name); 85 + g_free(name); 86 + } 87 + 88 + return &sdev->as; 89 + } 90 + 31 91 static void smmu_base_realize(DeviceState *dev, Error **errp) 32 92 { 93 + SMMUState *s = ARM_SMMU(dev); 33 94 SMMUBaseClass *sbc = ARM_SMMU_GET_CLASS(dev); 34 95 Error *local_err = NULL; 35 96 ··· 37 98 if (local_err) { 38 99 error_propagate(errp, local_err); 39 100 return; 101 + } 102 + 103 + s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL); 104 + 105 + if (s->primary_bus) { 106 + pci_setup_iommu(s->primary_bus, smmu_find_add_as, s); 107 + } else { 108 + error_setg(errp, "SMMU is not attached to any PCI bus!"); 40 109 } 41 110 } 42 111
+3
hw/arm/trace-events
··· 2 2 3 3 # hw/arm/virt-acpi-build.c 4 4 virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." 5 + 6 + # hw/arm/smmu-common.c 7 + smmu_add_mr(const char *name) "%s"
+8
include/hw/arm/smmu-common.h
··· 120 120 #define ARM_SMMU_GET_CLASS(obj) \ 121 121 OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_ARM_SMMU) 122 122 123 + /* Return the SMMUPciBus handle associated to a PCI bus number */ 124 + SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); 125 + 126 + /* Return the stream ID of an SMMU device */ 127 + static inline uint16_t smmu_get_sid(SMMUDevice *sdev) 128 + { 129 + return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); 130 + } 123 131 #endif /* HW_ARM_SMMU_COMMON */