jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
sm501: QOMify
Adding vmstate saving is not in this patch because the state structure
will be changed in further patches, then another patch will add
vmstate descriptor after those changes.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Message-id: a32b7fc981a20205f96d530d8e958f12ace1104c.1492787889.git.balaton@eik.bme.hu
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
BALATON Zoltan
and committed by
Peter Maydell
ca8a1104
70e46ca8
+132
-52
+123
-45
hw/display/sm501.c
+123
-45
hw/display/sm501.c
···
59
59
#define SM501_DPRINTF(fmt, ...) do {} while (0)
60
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#endif
61
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62
-
63
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#define MMIO_BASE_OFFSET 0x3e00000
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+
#define MMIO_SIZE 0x200000
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/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
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66
···
465
465
uint32_t local_mem_size_index;
466
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uint8_t *local_mem;
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MemoryRegion local_mem_region;
468
+
MemoryRegion mmio_region;
469
+
MemoryRegion system_config_region;
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+
MemoryRegion disp_ctrl_region;
471
+
MemoryRegion twoD_engine_region;
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472
uint32_t last_width;
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uint32_t last_height;
470
474
···
1404
1408
.gfx_update = sm501_update_display,
1405
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};
1406
1410
1407
-
void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
1408
-
uint32_t local_mem_bytes, qemu_irq irq, Chardev *chr)
1411
+
static void sm501_reset(SM501State *s)
1409
1412
{
1410
-
SM501State *s;
1411
-
DeviceState *dev;
1412
-
MemoryRegion *sm501_system_config = g_new(MemoryRegion, 1);
1413
-
MemoryRegion *sm501_disp_ctrl = g_new(MemoryRegion, 1);
1414
-
MemoryRegion *sm501_2d_engine = g_new(MemoryRegion, 1);
1415
-
1416
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/* allocate management data region */
1417
-
s = g_new0(SM501State, 1);
1418
-
s->base = base;
1419
-
s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
1420
-
SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
1421
-
s->local_mem_size_index);
1422
1413
s->system_control = 0x00100000; /* 2D engine FIFO empty */
1423
1414
/* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
1424
1415
* to be determined at reset by GPIO lines which set config bits.
···
1429
1420
* BUS = 0 : Hitachi SH3/SH4
1430
1421
*/
1431
1422
s->misc_control = SM501_MISC_DAC_POWER;
1423
+
s->gpio_31_0_control = 0;
1424
+
s->gpio_63_32_control = 0;
1425
+
s->dram_control = 0;
1432
1426
s->arbitration_control = 0x05146732;
1427
+
s->irq_mask = 0;
1428
+
s->misc_timing = 0;
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s->power_mode_control = 0;
1433
1430
s->dc_panel_control = 0x00010000; /* FIFO level 3 */
1434
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s->dc_crt_control = 0x00010000;
1432
+
s->twoD_control = 0;
1433
+
}
1435
1434
1436
-
/* allocate local memory */
1437
-
memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local",
1438
-
local_mem_bytes, &error_fatal);
1435
+
static void sm501_init(SM501State *s, DeviceState *dev, uint32_t base,
1436
+
uint32_t local_mem_bytes)
1437
+
{
1438
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s->base = base;
1439
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s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
1440
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SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s),
1441
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s->local_mem_size_index);
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+
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/* local memory */
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memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local",
1445
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get_local_mem_size(s), &error_fatal);
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vmstate_register_ram_global(&s->local_mem_region);
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memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA);
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s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
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memory_region_add_subregion(address_space_mem, base, &s->local_mem_region);
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/* map mmio */
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memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops,
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s, "sm501-system-config", 0x6c);
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memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET,
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sm501_system_config);
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memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s,
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+
/* mmio */
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memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE);
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memory_region_init_io(&s->system_config_region, OBJECT(dev),
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&sm501_system_config_ops, s,
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"sm501-system-config", 0x6c);
1455
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memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG,
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&s->system_config_region);
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memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev),
1458
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&sm501_disp_ctrl_ops, s,
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"sm501-disp-ctrl", 0x1000);
1451
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memory_region_add_subregion(address_space_mem,
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base + MMIO_BASE_OFFSET + SM501_DC,
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-
sm501_disp_ctrl);
1454
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memory_region_init_io(sm501_2d_engine, NULL, &sm501_2d_engine_ops, s,
1460
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memory_region_add_subregion(&s->mmio_region, SM501_DC,
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&s->disp_ctrl_region);
1462
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memory_region_init_io(&s->twoD_engine_region, OBJECT(dev),
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&sm501_2d_engine_ops, s,
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"sm501-2d-engine", 0x54);
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memory_region_add_subregion(address_space_mem,
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base + MMIO_BASE_OFFSET + SM501_2D_ENGINE,
1458
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sm501_2d_engine);
1465
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memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE,
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&s->twoD_engine_region);
1467
+
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/* create qemu graphic console */
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s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s);
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}
1471
+
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#define TYPE_SYSBUS_SM501 "sysbus-sm501"
1473
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#define SYSBUS_SM501(obj) \
1474
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OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501)
1475
+
1476
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typedef struct {
1477
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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SM501State state;
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uint32_t vram_size;
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uint32_t base;
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void *chr_state;
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} SM501SysBusState;
1485
+
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static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
1487
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{
1488
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SM501SysBusState *s = SYSBUS_SM501(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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DeviceState *usb_dev;
1491
+
1492
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sm501_init(&s->state, dev, s->base, s->vram_size);
1493
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if (get_local_mem_size(&s->state) != s->vram_size) {
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error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
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get_local_mem_size(&s->state));
1496
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return;
1497
+
}
1498
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sysbus_init_mmio(sbd, &s->state.local_mem_region);
1499
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sysbus_init_mmio(sbd, &s->state.mmio_region);
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/* bridge to usb host emulation module */
1461
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dev = qdev_create(NULL, "sysbus-ohci");
1462
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qdev_prop_set_uint32(dev, "num-ports", 2);
1463
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qdev_prop_set_uint64(dev, "dma-offset", base);
1464
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qdev_init_nofail(dev);
1465
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
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-
base + MMIO_BASE_OFFSET + SM501_USB_HOST);
1467
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
1502
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usb_dev = qdev_create(NULL, "sysbus-ohci");
1503
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qdev_prop_set_uint32(usb_dev, "num-ports", 2);
1504
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qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
1505
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qdev_init_nofail(usb_dev);
1506
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memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
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sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
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/* bridge to serial emulation module */
1470
-
if (chr) {
1471
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serial_mm_init(address_space_mem,
1472
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base + MMIO_BASE_OFFSET + SM501_UART0, 2,
1511
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if (s->chr_state) {
1512
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serial_mm_init(&s->state.mmio_region, SM501_UART0, 2,
1473
1513
NULL, /* TODO : chain irq to IRL */
1474
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115200, chr, DEVICE_NATIVE_ENDIAN);
1514
+
115200, s->chr_state, DEVICE_NATIVE_ENDIAN);
1475
1515
}
1516
+
}
1476
1517
1477
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/* create qemu graphic console */
1478
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s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s);
1518
+
static Property sm501_sysbus_properties[] = {
1519
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DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0),
1520
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DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0),
1521
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DEFINE_PROP_PTR("chr-state", SM501SysBusState, chr_state),
1522
+
DEFINE_PROP_END_OF_LIST(),
1523
+
};
1524
+
1525
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static void sm501_reset_sysbus(DeviceState *dev)
1526
+
{
1527
+
SM501SysBusState *s = SYSBUS_SM501(dev);
1528
+
sm501_reset(&s->state);
1479
1529
}
1530
+
1531
+
static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
1532
+
{
1533
+
DeviceClass *dc = DEVICE_CLASS(klass);
1534
+
1535
+
dc->realize = sm501_realize_sysbus;
1536
+
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
1537
+
dc->desc = "SM501 Multimedia Companion";
1538
+
dc->props = sm501_sysbus_properties;
1539
+
dc->reset = sm501_reset_sysbus;
1540
+
/* Note: pointer property "chr-state" may remain null, thus
1541
+
* no need for dc->cannot_instantiate_with_device_add_yet = true;
1542
+
*/
1543
+
}
1544
+
1545
+
static const TypeInfo sm501_sysbus_info = {
1546
+
.name = TYPE_SYSBUS_SM501,
1547
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.parent = TYPE_SYS_BUS_DEVICE,
1548
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.instance_size = sizeof(SM501SysBusState),
1549
+
.class_init = sm501_sysbus_class_init,
1550
+
};
1551
+
1552
+
static void sm501_register_types(void)
1553
+
{
1554
+
type_register_static(&sm501_sysbus_info);
1555
+
}
1556
+
1557
+
type_init(sm501_register_types)
+9
-2
hw/sh4/r2d.c
+9
-2
hw/sh4/r2d.c
···
277
277
sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
278
278
sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
279
279
280
-
sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE,
281
-
irq[SM501], serial_hds[2]);
280
+
dev = qdev_create(NULL, "sysbus-sm501");
281
+
busdev = SYS_BUS_DEVICE(dev);
282
+
qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
283
+
qdev_prop_set_uint32(dev, "base", 0x10000000);
284
+
qdev_prop_set_ptr(dev, "chr-state", serial_hds[2]);
285
+
qdev_init_nofail(dev);
286
+
sysbus_mmio_map(busdev, 0, 0x10000000);
287
+
sysbus_mmio_map(busdev, 1, 0x13e00000);
288
+
sysbus_connect_irq(busdev, 0, irq[SM501]);
282
289
283
290
/* onboard CF (True IDE mode, Master only). */
284
291
dinfo = drive_get(IF_IDE, 0, 0);
-5
include/hw/devices.h
-5
include/hw/devices.h