-8

backends/hostmem-file.c

··· 18 18 #include "sysemu/sysemu.h" 19 19 #include "qom/object_interfaces.h" 20 20 21 21 - /* hostmem-file.c */ 22 22 - /** 23 23 - * @TYPE_MEMORY_BACKEND_FILE: 24 24 - * name of backend that uses mmap on a file descriptor 25 25 - */ 26 26 - #define TYPE_MEMORY_BACKEND_FILE "memory-backend-file" 27 27 - 28 21 #define MEMORY_BACKEND_FILE(obj) \ 29 22 OBJECT_CHECK(HostMemoryBackendFile, (obj), TYPE_MEMORY_BACKEND_FILE) 30 23 ··· 58 51 return; 59 52 } 60 53 61 61 - backend->force_prealloc = mem_prealloc; 62 54 name = host_memory_backend_get_name(backend); 63 55 memory_region_init_ram_from_file(&backend->mr, OBJECT(backend), 64 56 name,

-1

backends/hostmem-memfd.c

··· 45 45 return; 46 46 } 47 47 48 48 - backend->force_prealloc = mem_prealloc; 49 48 fd = qemu_memfd_create(TYPE_MEMORY_BACKEND_MEMFD, backend->size, 50 49 m->hugetlb, m->hugetlbsize, m->seal ? 51 50 F_SEAL_GROW | F_SEAL_SHRINK | F_SEAL_SEAL : 0,

-2

backends/hostmem-ram.c

··· 16 16 #include "qemu/module.h" 17 17 #include "qom/object_interfaces.h" 18 18 19 19 - #define TYPE_MEMORY_BACKEND_RAM "memory-backend-ram" 20 20 - 21 19 static void 22 20 ram_backend_memory_alloc(HostMemoryBackend *backend, Error **errp) 23 21 {

+39 -14

backends/hostmem.c

··· 215 215 { 216 216 HostMemoryBackend *backend = MEMORY_BACKEND(obj); 217 217 218 218 - return backend->prealloc || backend->force_prealloc; 218 218 + return backend->prealloc; 219 219 } 220 220 221 221 static void host_memory_backend_set_prealloc(Object *obj, bool value, ··· 223 223 { 224 224 Error *local_err = NULL; 225 225 HostMemoryBackend *backend = MEMORY_BACKEND(obj); 226 226 - MachineState *ms = MACHINE(qdev_get_machine()); 227 227 - 228 228 - if (backend->force_prealloc) { 229 229 - if (value) { 230 230 - error_setg(errp, 231 231 - "remove -mem-prealloc to use the prealloc property"); 232 232 - return; 233 233 - } 234 234 - } 235 226 236 227 if (!host_memory_backend_mr_inited(backend)) { 237 228 backend->prealloc = value; ··· 243 234 void *ptr = memory_region_get_ram_ptr(&backend->mr); 244 235 uint64_t sz = memory_region_size(&backend->mr); 245 236 246 246 - os_mem_prealloc(fd, ptr, sz, ms->smp.cpus, &local_err); 237 237 + os_mem_prealloc(fd, ptr, sz, backend->prealloc_threads, &local_err); 247 238 if (local_err) { 248 239 error_propagate(errp, local_err); 249 240 return; ··· 252 243 } 253 244 } 254 245 246 246 + static void host_memory_backend_get_prealloc_threads(Object *obj, Visitor *v, 247 247 + const char *name, void *opaque, Error **errp) 248 248 + { 249 249 + HostMemoryBackend *backend = MEMORY_BACKEND(obj); 250 250 + visit_type_uint32(v, name, &backend->prealloc_threads, errp); 251 251 + } 252 252 + 253 253 + static void host_memory_backend_set_prealloc_threads(Object *obj, Visitor *v, 254 254 + const char *name, void *opaque, Error **errp) 255 255 + { 256 256 + HostMemoryBackend *backend = MEMORY_BACKEND(obj); 257 257 + Error *local_err = NULL; 258 258 + uint32_t value; 259 259 + 260 260 + visit_type_uint32(v, name, &value, &local_err); 261 261 + if (local_err) { 262 262 + goto out; 263 263 + } 264 264 + if (value <= 0) { 265 265 + error_setg(&local_err, 266 266 + "property '%s' of %s doesn't take value '%d'", 267 267 + name, object_get_typename(obj), value); 268 268 + goto out; 269 269 + } 270 270 + backend->prealloc_threads = value; 271 271 + out: 272 272 + error_propagate(errp, local_err); 273 273 + } 274 274 + 255 275 static void host_memory_backend_init(Object *obj) 256 276 { 257 277 HostMemoryBackend *backend = MEMORY_BACKEND(obj); 258 278 MachineState *machine = MACHINE(qdev_get_machine()); 259 279 280 280 + /* TODO: convert access to globals to compat properties */ 260 281 backend->merge = machine_mem_merge(machine); 261 282 backend->dump = machine_dump_guest_core(machine); 262 262 - backend->prealloc = mem_prealloc; 263 283 } 264 284 265 285 static void host_memory_backend_post_init(Object *obj) ··· 313 333 { 314 334 HostMemoryBackend *backend = MEMORY_BACKEND(uc); 315 335 HostMemoryBackendClass *bc = MEMORY_BACKEND_GET_CLASS(uc); 316 316 - MachineState *ms = MACHINE(qdev_get_machine()); 317 336 Error *local_err = NULL; 318 337 void *ptr; 319 338 uint64_t sz; ··· 378 397 */ 379 398 if (backend->prealloc) { 380 399 os_mem_prealloc(memory_region_get_fd(&backend->mr), ptr, sz, 381 381 - ms->smp.cpus, &local_err); 400 400 + backend->prealloc_threads, &local_err); 382 401 if (local_err) { 383 402 goto out; 384 403 } ··· 456 475 host_memory_backend_set_prealloc, &error_abort); 457 476 object_class_property_set_description(oc, "prealloc", 458 477 "Preallocate memory", &error_abort); 478 478 + object_class_property_add(oc, "prealloc-threads", "int", 479 479 + host_memory_backend_get_prealloc_threads, 480 480 + host_memory_backend_set_prealloc_threads, 481 481 + NULL, NULL, &error_abort); 482 482 + object_class_property_set_description(oc, "prealloc-threads", 483 483 + "Number of CPU threads to use for prealloc", &error_abort); 459 484 object_class_property_add(oc, "size", "int", 460 485 host_memory_backend_get_size, 461 486 host_memory_backend_set_size,

+6 -58

exec.c

··· 1668 1668 long qemu_minrampagesize(void) 1669 1669 { 1670 1670 long hpsize = LONG_MAX; 1671 1671 - long mainrampagesize; 1672 1672 - Object *memdev_root; 1673 1673 - MachineState *ms = MACHINE(qdev_get_machine()); 1671 1671 + Object *memdev_root = object_resolve_path("/objects", NULL); 1674 1672 1675 1675 - mainrampagesize = qemu_mempath_getpagesize(mem_path); 1676 1676 - 1677 1677 - /* it's possible we have memory-backend objects with 1678 1678 - * hugepage-backed RAM. these may get mapped into system 1679 1679 - * address space via -numa parameters or memory hotplug 1680 1680 - * hooks. we want to take these into account, but we 1681 1681 - * also want to make sure these supported hugepage 1682 1682 - * sizes are applicable across the entire range of memory 1683 1683 - * we may boot from, so we take the min across all 1684 1684 - * backends, and assume normal pages in cases where a 1685 1685 - * backend isn't backed by hugepages. 1686 1686 - */ 1687 1687 - memdev_root = object_resolve_path("/objects", NULL); 1688 1688 - if (memdev_root) { 1689 1689 - object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize); 1690 1690 - } 1691 1691 - if (hpsize == LONG_MAX) { 1692 1692 - /* No additional memory regions found ==> Report main RAM page size */ 1693 1693 - return mainrampagesize; 1694 1694 - } 1695 1695 - 1696 1696 - /* If NUMA is disabled or the NUMA nodes are not backed with a 1697 1697 - * memory-backend, then there is at least one node using "normal" RAM, 1698 1698 - * so if its page size is smaller we have got to report that size instead. 1699 1699 - */ 1700 1700 - if (hpsize > mainrampagesize && 1701 1701 - (ms->numa_state == NULL || 1702 1702 - ms->numa_state->num_nodes == 0 || 1703 1703 - ms->numa_state->nodes[0].node_memdev == NULL)) { 1704 1704 - static bool warned; 1705 1705 - if (!warned) { 1706 1706 - error_report("Huge page support disabled (n/a for main memory)."); 1707 1707 - warned = true; 1708 1708 - } 1709 1709 - return mainrampagesize; 1710 1710 - } 1711 1711 - 1673 1673 + object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize); 1712 1674 return hpsize; 1713 1675 } 1714 1676 1715 1677 long qemu_maxrampagesize(void) 1716 1678 { 1717 1717 - long pagesize = qemu_mempath_getpagesize(mem_path); 1679 1679 + long pagesize = 0; 1718 1680 Object *memdev_root = object_resolve_path("/objects", NULL); 1719 1681 1720 1720 - if (memdev_root) { 1721 1721 - object_child_foreach(memdev_root, find_max_backend_pagesize, 1722 1722 - &pagesize); 1723 1723 - } 1682 1682 + object_child_foreach(memdev_root, find_max_backend_pagesize, &pagesize); 1724 1683 return pagesize; 1725 1684 } 1726 1685 #else ··· 1843 1802 bool truncate, 1844 1803 Error **errp) 1845 1804 { 1846 1846 - Error *err = NULL; 1847 1847 - MachineState *ms = MACHINE(qdev_get_machine()); 1848 1805 void *area; 1849 1806 1850 1807 block->page_size = qemu_fd_getpagesize(fd); ··· 1898 1855 error_setg_errno(errp, errno, 1899 1856 "unable to map backing store for guest RAM"); 1900 1857 return NULL; 1901 1901 - } 1902 1902 - 1903 1903 - if (mem_prealloc) { 1904 1904 - os_mem_prealloc(fd, area, memory, ms->smp.cpus, &err); 1905 1905 - if (err) { 1906 1906 - error_propagate(errp, err); 1907 1907 - qemu_ram_munmap(fd, area, memory); 1908 1908 - return NULL; 1909 1909 - } 1910 1858 } 1911 1859 1912 1860 block->fd = fd; ··· 2356 2304 size = HOST_PAGE_ALIGN(size); 2357 2305 file_size = get_file_size(fd); 2358 2306 if (file_size > 0 && file_size < size) { 2359 2359 - error_setg(errp, "backing store %s size 0x%" PRIx64 2307 2307 + error_setg(errp, "backing store size 0x%" PRIx64 2360 2308 " does not match 'size' option 0x" RAM_ADDR_FMT, 2361 2361 - mem_path, file_size, size); 2309 2309 + file_size, size); 2362 2310 return NULL; 2363 2311 } 2364 2312

+1 -1

hw/alpha/alpha_sys.h

··· 11 11 #include "hw/intc/i8259.h" 12 12 13 13 14 14 - PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, AlphaCPU *[4], 14 14 + PCIBus *typhoon_init(MemoryRegion *, ISABus **, qemu_irq *, AlphaCPU *[4], 15 15 pci_map_irq_fn); 16 16 17 17 /* alpha_pci.c. */

+2 -1

hw/alpha/dp264.c

··· 75 75 cpus[0]->env.trap_arg2 = smp_cpus; 76 76 77 77 /* Init the chipset. */ 78 78 - pci_bus = typhoon_init(ram_size, &isa_bus, &rtc_irq, cpus, 78 78 + pci_bus = typhoon_init(machine->ram, &isa_bus, &rtc_irq, cpus, 79 79 clipper_pci_map_irq); 80 80 81 81 /* Since we have an SRM-compatible PALcode, use the SRM epoch. */ ··· 183 183 mc->max_cpus = 4; 184 184 mc->is_default = 1; 185 185 mc->default_cpu_type = ALPHA_CPU_TYPE_NAME("ev67"); 186 186 + mc->default_ram_id = "ram"; 186 187 } 187 188 188 189 DEFINE_MACHINE("clipper", clipper_machine_init)

+2 -6

hw/alpha/typhoon.c

··· 58 58 TyphoonCchip cchip; 59 59 TyphoonPchip pchip; 60 60 MemoryRegion dchip_region; 61 61 - MemoryRegion ram_region; 62 61 } TyphoonState; 63 62 64 63 /* Called when one of DRIR or DIM changes. */ ··· 817 816 cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER); 818 817 } 819 818 820 820 - PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, 821 821 - qemu_irq *p_rtc_irq, 819 819 + PCIBus *typhoon_init(MemoryRegion *ram, ISABus **isa_bus, qemu_irq *p_rtc_irq, 822 820 AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq) 823 821 { 824 822 MemoryRegion *addr_space = get_system_memory(); ··· 851 849 852 850 /* Main memory region, 0x00.0000.0000. Real hardware supports 32GB, 853 851 but the address space hole reserved at this point is 8TB. */ 854 854 - memory_region_allocate_system_memory(&s->ram_region, OBJECT(s), "ram", 855 855 - ram_size); 856 856 - memory_region_add_subregion(addr_space, 0, &s->ram_region); 852 852 + memory_region_add_subregion(addr_space, 0, ram); 857 853 858 854 /* TIGbus, 0x801.0000.0000, 1GB. */ 859 855 /* ??? The TIGbus is used for delivering interrupts, and access to

+7 -11

hw/arm/aspeed.c

··· 35 35 struct AspeedBoardState { 36 36 AspeedSoCState soc; 37 37 MemoryRegion ram_container; 38 38 - MemoryRegion ram; 39 38 MemoryRegion max_ram; 40 39 }; 41 40 ··· 197 196 198 197 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", 199 198 UINT32_MAX); 199 199 + memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); 200 200 201 201 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, 202 202 (sizeof(bmc->soc)), amc->soc_name, &error_abort, ··· 204 204 205 205 sc = ASPEED_SOC_GET_CLASS(&bmc->soc); 206 206 207 207 + /* 208 208 + * This will error out if isize is not supported by memory controller. 209 209 + */ 207 210 object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", 208 208 - &error_abort); 211 211 + &error_fatal); 212 212 + 209 213 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1", 210 214 &error_abort); 211 215 object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2", ··· 228 232 object_property_set_bool(OBJECT(&bmc->soc), true, "realized", 229 233 &error_abort); 230 234 231 231 - /* 232 232 - * Allocate RAM after the memory controller has checked the size 233 233 - * was valid. If not, a default value is used. 234 234 - */ 235 235 - ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size", 236 236 - &error_abort); 237 237 - 238 238 - memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); 239 239 - memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram); 240 235 memory_region_add_subregion(get_system_memory(), 241 236 sc->memmap[ASPEED_SDRAM], 242 237 &bmc->ram_container); ··· 439 434 mc->no_floppy = 1; 440 435 mc->no_cdrom = 1; 441 436 mc->no_parallel = 1; 437 437 + mc->default_ram_id = "ram"; 442 438 443 439 aspeed_machine_class_props_init(oc); 444 440 }

+12 -4

hw/arm/collie.c

··· 10 10 */ 11 11 #include "qemu/osdep.h" 12 12 #include "qemu/units.h" 13 13 + #include "qemu/cutils.h" 13 14 #include "hw/sysbus.h" 14 15 #include "hw/boards.h" 15 16 #include "strongarm.h" ··· 27 28 { 28 29 StrongARMState *s; 29 30 DriveInfo *dinfo; 30 30 - MemoryRegion *sdram = g_new(MemoryRegion, 1); 31 31 + MachineClass *mc = MACHINE_GET_CLASS(machine); 32 32 + 33 33 + if (machine->ram_size != mc->default_ram_size) { 34 34 + char *sz = size_to_str(mc->default_ram_size); 35 35 + error_report("Invalid RAM size, should be %s", sz); 36 36 + g_free(sz); 37 37 + exit(EXIT_FAILURE); 38 38 + } 31 39 32 40 s = sa1110_init(machine->cpu_type); 33 41 34 34 - memory_region_allocate_system_memory(sdram, NULL, "strongarm.sdram", 35 35 - collie_binfo.ram_size); 36 36 - memory_region_add_subregion(get_system_memory(), SA_SDCS0, sdram); 42 42 + memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram); 37 43 38 44 dinfo = drive_get(IF_PFLASH, 0, 0); 39 45 pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000, ··· 57 63 mc->init = collie_init; 58 64 mc->ignore_memory_transaction_failures = true; 59 65 mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110"); 66 66 + mc->default_ram_size = 0x20000000; 67 67 + mc->default_ram_id = "strongarm.sdram"; 60 68 } 61 69 62 70 DEFINE_MACHINE("collie", collie_machine_init)

+8 -17

hw/arm/cubieboard.c

··· 28 28 .board_id = 0x1008, 29 29 }; 30 30 31 31 - typedef struct CubieBoardState { 32 32 - AwA10State *a10; 33 33 - MemoryRegion sdram; 34 34 - } CubieBoardState; 35 35 - 36 31 static void cubieboard_init(MachineState *machine) 37 32 { 38 38 - CubieBoardState *s = g_new(CubieBoardState, 1); 33 33 + AwA10State *a10 = AW_A10(object_new(TYPE_AW_A10)); 39 34 Error *err = NULL; 40 35 41 41 - s->a10 = AW_A10(object_new(TYPE_AW_A10)); 42 42 - 43 43 - object_property_set_int(OBJECT(&s->a10->emac), 1, "phy-addr", &err); 36 36 + object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err); 44 37 if (err != NULL) { 45 38 error_reportf_err(err, "Couldn't set phy address: "); 46 39 exit(1); 47 40 } 48 41 49 49 - object_property_set_int(OBJECT(&s->a10->timer), 32768, "clk0-freq", &err); 42 42 + object_property_set_int(OBJECT(&a10->timer), 32768, "clk0-freq", &err); 50 43 if (err != NULL) { 51 44 error_reportf_err(err, "Couldn't set clk0 frequency: "); 52 45 exit(1); 53 46 } 54 47 55 55 - object_property_set_int(OBJECT(&s->a10->timer), 24000000, "clk1-freq", 56 56 - &err); 48 48 + object_property_set_int(OBJECT(&a10->timer), 24000000, "clk1-freq", &err); 57 49 if (err != NULL) { 58 50 error_reportf_err(err, "Couldn't set clk1 frequency: "); 59 51 exit(1); 60 52 } 61 53 62 62 - object_property_set_bool(OBJECT(s->a10), true, "realized", &err); 54 54 + object_property_set_bool(OBJECT(a10), true, "realized", &err); 63 55 if (err != NULL) { 64 56 error_reportf_err(err, "Couldn't realize Allwinner A10: "); 65 57 exit(1); 66 58 } 67 59 68 68 - memory_region_allocate_system_memory(&s->sdram, NULL, "cubieboard.ram", 69 69 - machine->ram_size); 70 60 memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE, 71 71 - &s->sdram); 61 61 + machine->ram); 72 62 73 63 /* TODO create and connect IDE devices for ide_drive_get() */ 74 64 75 65 cubieboard_binfo.ram_size = machine->ram_size; 76 76 - arm_load_kernel(&s->a10->cpu, machine, &cubieboard_binfo); 66 66 + arm_load_kernel(&a10->cpu, machine, &cubieboard_binfo); 77 67 } 78 68 79 69 static void cubieboard_machine_init(MachineClass *mc) ··· 84 74 mc->block_default_type = IF_IDE; 85 75 mc->units_per_default_bus = 1; 86 76 mc->ignore_memory_transaction_failures = true; 77 77 + mc->default_ram_id = "cubieboard.ram"; 87 78 } 88 79 89 80 DEFINE_MACHINE("cubieboard", cubieboard_machine_init)

+20 -18

hw/arm/digic_boards.c

··· 35 35 #include "hw/loader.h" 36 36 #include "sysemu/sysemu.h" 37 37 #include "sysemu/qtest.h" 38 38 + #include "qemu/units.h" 39 39 + #include "qemu/cutils.h" 38 40 39 41 #define DIGIC4_ROM0_BASE 0xf0000000 40 42 #define DIGIC4_ROM1_BASE 0xf8000000 41 43 #define DIGIC4_ROM_MAX_SIZE 0x08000000 42 44 43 43 - typedef struct DigicBoardState { 44 44 - DigicState *digic; 45 45 - MemoryRegion ram; 46 46 - } DigicBoardState; 47 47 - 48 45 typedef struct DigicBoard { 49 49 - hwaddr ram_size; 50 50 - void (*add_rom0)(DigicBoardState *, hwaddr, const char *); 46 46 + void (*add_rom0)(DigicState *, hwaddr, const char *); 51 47 const char *rom0_def_filename; 52 52 - void (*add_rom1)(DigicBoardState *, hwaddr, const char *); 48 48 + void (*add_rom1)(DigicState *, hwaddr, const char *); 53 49 const char *rom1_def_filename; 54 50 } DigicBoard; 55 51 56 56 - static void digic4_board_init(DigicBoard *board) 52 52 + static void digic4_board_init(MachineState *machine, DigicBoard *board) 57 53 { 58 54 Error *err = NULL; 55 55 + DigicState *s = DIGIC(object_new(TYPE_DIGIC)); 56 56 + MachineClass *mc = MACHINE_GET_CLASS(machine); 59 57 60 60 - DigicBoardState *s = g_new(DigicBoardState, 1); 58 58 + if (machine->ram_size != mc->default_ram_size) { 59 59 + char *sz = size_to_str(mc->default_ram_size); 60 60 + error_report("Invalid RAM size, should be %s", sz); 61 61 + g_free(sz); 62 62 + exit(EXIT_FAILURE); 63 63 + } 61 64 62 62 - s->digic = DIGIC(object_new(TYPE_DIGIC)); 63 63 - object_property_set_bool(OBJECT(s->digic), true, "realized", &err); 65 65 + object_property_set_bool(OBJECT(s), true, "realized", &err); 64 66 if (err != NULL) { 65 67 error_reportf_err(err, "Couldn't realize DIGIC SoC: "); 66 68 exit(1); 67 69 } 68 70 69 69 - memory_region_allocate_system_memory(&s->ram, NULL, "ram", board->ram_size); 70 70 - memory_region_add_subregion(get_system_memory(), 0, &s->ram); 71 71 + memory_region_add_subregion(get_system_memory(), 0, machine->ram); 71 72 72 73 if (board->add_rom0) { 73 74 board->add_rom0(s, DIGIC4_ROM0_BASE, board->rom0_def_filename); ··· 78 79 } 79 80 } 80 81 81 81 - static void digic_load_rom(DigicBoardState *s, hwaddr addr, 82 82 + static void digic_load_rom(DigicState *s, hwaddr addr, 82 83 hwaddr max_size, const char *def_filename) 83 84 { 84 85 target_long rom_size; ··· 118 119 * Samsung K8P3215UQB 119 120 * 64M Bit (4Mx16) Page Mode / Multi-Bank NOR Flash Memory 120 121 */ 121 121 - static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr, 122 122 + static void digic4_add_k8p3215uqb_rom(DigicState *s, hwaddr addr, 122 123 const char *def_filename) 123 124 { 124 125 #define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024) ··· 135 136 } 136 137 137 138 static DigicBoard digic4_board_canon_a1100 = { 138 138 - .ram_size = 64 * 1024 * 1024, 139 139 .add_rom1 = digic4_add_k8p3215uqb_rom, 140 140 .rom1_def_filename = "canon-a1100-rom1.bin", 141 141 }; 142 142 143 143 static void canon_a1100_init(MachineState *machine) 144 144 { 145 145 - digic4_board_init(&digic4_board_canon_a1100); 145 145 + digic4_board_init(machine, &digic4_board_canon_a1100); 146 146 } 147 147 148 148 static void canon_a1100_machine_init(MachineClass *mc) ··· 150 150 mc->desc = "Canon PowerShot A1100 IS"; 151 151 mc->init = &canon_a1100_init; 152 152 mc->ignore_memory_transaction_failures = true; 153 153 + mc->default_ram_size = 64 * MiB; 154 154 + mc->default_ram_id = "ram"; 153 155 } 154 156 155 157 DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init)

+4 -6

hw/arm/highbank.c

··· 236 236 */ 237 237 static void calxeda_init(MachineState *machine, enum cxmachines machine_id) 238 238 { 239 239 - ram_addr_t ram_size = machine->ram_size; 240 239 DeviceState *dev = NULL; 241 240 SysBusDevice *busdev; 242 241 qemu_irq pic[128]; ··· 247 246 qemu_irq cpu_virq[4]; 248 247 qemu_irq cpu_vfiq[4]; 249 248 MemoryRegion *sysram; 250 250 - MemoryRegion *dram; 251 249 MemoryRegion *sysmem; 252 250 char *sysboot_filename; 253 251 ··· 290 288 } 291 289 292 290 sysmem = get_system_memory(); 293 293 - dram = g_new(MemoryRegion, 1); 294 294 - memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size); 295 291 /* SDRAM at address zero. */ 296 296 - memory_region_add_subregion(sysmem, 0, dram); 292 292 + memory_region_add_subregion(sysmem, 0, machine->ram); 297 293 298 294 sysram = g_new(MemoryRegion, 1); 299 295 memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, ··· 387 383 388 384 /* TODO create and connect IDE devices for ide_drive_get() */ 389 385 390 390 - highbank_binfo.ram_size = ram_size; 386 386 + highbank_binfo.ram_size = machine->ram_size; 391 387 /* highbank requires a dtb in order to boot, and the dtb will override 392 388 * the board ID. The following value is ignored, so set it to -1 to be 393 389 * clear that the value is meaningless. ··· 430 426 mc->units_per_default_bus = 1; 431 427 mc->max_cpus = 4; 432 428 mc->ignore_memory_transaction_failures = true; 429 429 + mc->default_ram_id = "highbank.dram"; 433 430 } 434 431 435 432 static const TypeInfo highbank_type = { ··· 448 445 mc->units_per_default_bus = 1; 449 446 mc->max_cpus = 4; 450 447 mc->ignore_memory_transaction_failures = true; 448 448 + mc->default_ram_id = "highbank.dram"; 451 449 } 452 450 453 451 static const TypeInfo midway_type = {

+10 -9

hw/arm/imx25_pdk.c

··· 32 32 #include "exec/address-spaces.h" 33 33 #include "sysemu/qtest.h" 34 34 #include "hw/i2c/i2c.h" 35 35 + #include "qemu/cutils.h" 35 36 36 37 /* Memory map for PDK Emulation Baseboard: 37 38 * 0x00000000-0x7fffffff See i.MX25 SOC fr support ··· 58 59 59 60 typedef struct IMX25PDK { 60 61 FslIMX25State soc; 61 61 - MemoryRegion ram; 62 62 MemoryRegion ram_alias; 63 63 } IMX25PDK; 64 64 ··· 66 66 67 67 static void imx25_pdk_init(MachineState *machine) 68 68 { 69 69 + MachineClass *mc = MACHINE_GET_CLASS(machine); 69 70 IMX25PDK *s = g_new0(IMX25PDK, 1); 70 71 unsigned int ram_size; 71 72 unsigned int alias_offset; ··· 78 79 79 80 /* We need to initialize our memory */ 80 81 if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) { 81 81 - warn_report("RAM size " RAM_ADDR_FMT " above max supported, " 82 82 - "reduced to %x", machine->ram_size, 83 83 - FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE); 84 84 - machine->ram_size = FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE; 82 82 + char *sz = size_to_str(mc->default_ram_size); 83 83 + error_report("Invalid RAM size, should be %s", sz); 84 84 + g_free(sz); 85 85 + exit(EXIT_FAILURE); 85 86 } 86 87 87 87 - memory_region_allocate_system_memory(&s->ram, NULL, "imx25.ram", 88 88 - machine->ram_size); 89 88 memory_region_add_subregion(get_system_memory(), FSL_IMX25_SDRAM0_ADDR, 90 90 - &s->ram); 89 89 + machine->ram); 91 90 92 91 /* initialize the alias memory if any */ 93 92 for (i = 0, ram_size = machine->ram_size, alias_offset = 0; ··· 107 106 108 107 if (size < ram[i].size) { 109 108 memory_region_init_alias(&s->ram_alias, NULL, "ram.alias", 110 110 - &s->ram, alias_offset, ram[i].size - size); 109 109 + machine->ram, 110 110 + alias_offset, ram[i].size - size); 111 111 memory_region_add_subregion(get_system_memory(), 112 112 ram[i].addr + size, &s->ram_alias); 113 113 } ··· 135 135 mc->desc = "ARM i.MX25 PDK board (ARM926)"; 136 136 mc->init = imx25_pdk_init; 137 137 mc->ignore_memory_transaction_failures = true; 138 138 + mc->default_ram_id = "imx25.ram"; 138 139 } 139 140 140 141 DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init)

+4 -5

hw/arm/integratorcp.c

··· 585 585 Object *cpuobj; 586 586 ARMCPU *cpu; 587 587 MemoryRegion *address_space_mem = get_system_memory(); 588 588 - MemoryRegion *ram = g_new(MemoryRegion, 1); 589 588 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 590 589 qemu_irq pic[32]; 591 590 DeviceState *dev, *sic, *icp; ··· 605 604 606 605 cpu = ARM_CPU(cpuobj); 607 606 608 608 - memory_region_allocate_system_memory(ram, NULL, "integrator.ram", 609 609 - ram_size); 610 607 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 611 608 /* ??? RAM should repeat to fill physical memory space. */ 612 609 /* SDRAM at address zero*/ 613 613 - memory_region_add_subregion(address_space_mem, 0, ram); 610 610 + memory_region_add_subregion(address_space_mem, 0, machine->ram); 614 611 /* And again at address 0x80000000 */ 615 615 - memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 612 612 + memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram, 613 613 + 0, ram_size); 616 614 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 617 615 618 616 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); ··· 660 658 mc->init = integratorcp_init; 661 659 mc->ignore_memory_transaction_failures = true; 662 660 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 661 661 + mc->default_ram_id = "integrator.ram"; 663 662 } 664 663 665 664 DEFINE_MACHINE("integratorcp", integratorcp_machine_init)

+9 -9

hw/arm/kzm.c

··· 25 25 #include "hw/char/serial.h" 26 26 #include "sysemu/qtest.h" 27 27 #include "sysemu/sysemu.h" 28 28 + #include "qemu/cutils.h" 28 29 29 30 /* Memory map for Kzm Emulation Baseboard: 30 31 * 0x00000000-0x7fffffff See i.MX31 SOC for support ··· 51 52 52 53 typedef struct IMX31KZM { 53 54 FslIMX31State soc; 54 54 - MemoryRegion ram; 55 55 MemoryRegion ram_alias; 56 56 } IMX31KZM; 57 57 ··· 78 78 79 79 /* Check the amount of memory is compatible with the SOC */ 80 80 if (machine->ram_size > (FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE)) { 81 81 - warn_report("RAM size " RAM_ADDR_FMT " above max supported, " 82 82 - "reduced to %x", machine->ram_size, 83 83 - FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE); 84 84 - machine->ram_size = FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE; 81 81 + char *sz = size_to_str(FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE); 82 82 + error_report("RAM size more than %s is not supported", sz); 83 83 + g_free(sz); 84 84 + exit(EXIT_FAILURE); 85 85 } 86 86 87 87 - memory_region_allocate_system_memory(&s->ram, NULL, "kzm.ram", 88 88 - machine->ram_size); 89 87 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SDRAM0_ADDR, 90 90 - &s->ram); 88 88 + machine->ram); 91 89 92 90 /* initialize the alias memory if any */ 93 91 for (i = 0, ram_size = machine->ram_size, alias_offset = 0; ··· 107 105 108 106 if (size < ram[i].size) { 109 107 memory_region_init_alias(&s->ram_alias, NULL, "ram.alias", 110 110 - &s->ram, alias_offset, ram[i].size - size); 108 108 + machine->ram, 109 109 + alias_offset, ram[i].size - size); 111 110 memory_region_add_subregion(get_system_memory(), 112 111 ram[i].addr + size, &s->ram_alias); 113 112 } ··· 139 138 mc->desc = "ARM KZM Emulation Baseboard (ARM1136)"; 140 139 mc->init = kzm_init; 141 140 mc->ignore_memory_transaction_failures = true; 141 141 + mc->default_ram_id = "kzm.ram"; 142 142 } 143 143 144 144 DEFINE_MACHINE("kzm", kzm_machine_init)

+9 -16

hw/arm/mcimx6ul-evk.c

··· 19 19 #include "qemu/error-report.h" 20 20 #include "sysemu/qtest.h" 21 21 22 22 - typedef struct { 23 23 - FslIMX6ULState soc; 24 24 - MemoryRegion ram; 25 25 - } MCIMX6ULEVK; 26 26 - 27 22 static void mcimx6ul_evk_init(MachineState *machine) 28 23 { 29 24 static struct arm_boot_info boot_info; 30 30 - MCIMX6ULEVK *s = g_new0(MCIMX6ULEVK, 1); 25 25 + FslIMX6ULState *s; 31 26 int i; 32 27 33 28 if (machine->ram_size > FSL_IMX6UL_MMDC_SIZE) { ··· 43 38 .nb_cpus = machine->smp.cpus, 44 39 }; 45 40 46 46 - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 47 47 - TYPE_FSL_IMX6UL, &error_fatal, NULL); 41 41 + s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL)); 42 42 + object_property_add_child(OBJECT(machine), "soc", OBJECT(s), &error_fatal); 43 43 + object_property_set_bool(OBJECT(s), true, "realized", &error_fatal); 48 44 49 49 - object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); 50 50 - 51 51 - memory_region_allocate_system_memory(&s->ram, NULL, "mcimx6ul-evk.ram", 52 52 - machine->ram_size); 53 53 - memory_region_add_subregion(get_system_memory(), 54 54 - FSL_IMX6UL_MMDC_ADDR, &s->ram); 45 45 + memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR, 46 46 + machine->ram); 55 47 56 48 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { 57 49 BusState *bus; ··· 61 53 62 54 di = drive_get_next(IF_SD); 63 55 blk = di ? blk_by_legacy_dinfo(di) : NULL; 64 64 - bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus"); 56 56 + bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); 65 57 carddev = qdev_create(bus, TYPE_SD_CARD); 66 58 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 67 59 object_property_set_bool(OBJECT(carddev), true, ··· 69 61 } 70 62 71 63 if (!qtest_enabled()) { 72 72 - arm_load_kernel(&s->soc.cpu, machine, &boot_info); 64 64 + arm_load_kernel(&s->cpu, machine, &boot_info); 73 65 } 74 66 } 75 67 ··· 78 70 mc->desc = "Freescale i.MX6UL Evaluation Kit (Cortex A7)"; 79 71 mc->init = mcimx6ul_evk_init; 80 72 mc->max_cpus = FSL_IMX6UL_NUM_CPUS; 73 73 + mc->default_ram_id = "mcimx6ul-evk.ram"; 81 74 } 82 75 DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)

+9 -16

hw/arm/mcimx7d-sabre.c

··· 21 21 #include "qemu/error-report.h" 22 22 #include "sysemu/qtest.h" 23 23 24 24 - typedef struct { 25 25 - FslIMX7State soc; 26 26 - MemoryRegion ram; 27 27 - } MCIMX7Sabre; 28 28 - 29 24 static void mcimx7d_sabre_init(MachineState *machine) 30 25 { 31 26 static struct arm_boot_info boot_info; 32 32 - MCIMX7Sabre *s = g_new0(MCIMX7Sabre, 1); 27 27 + FslIMX7State *s; 33 28 int i; 34 29 35 30 if (machine->ram_size > FSL_IMX7_MMDC_SIZE) { ··· 45 40 .nb_cpus = machine->smp.cpus, 46 41 }; 47 42 48 48 - object_initialize_child(OBJECT(machine), "soc", 49 49 - &s->soc, sizeof(s->soc), 50 50 - TYPE_FSL_IMX7, &error_fatal, NULL); 51 51 - object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); 43 43 + s = FSL_IMX7(object_new(TYPE_FSL_IMX7)); 44 44 + object_property_add_child(OBJECT(machine), "soc", OBJECT(s), &error_fatal); 45 45 + object_property_set_bool(OBJECT(s), true, "realized", &error_fatal); 52 46 53 53 - memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram", 54 54 - machine->ram_size); 55 55 - memory_region_add_subregion(get_system_memory(), 56 56 - FSL_IMX7_MMDC_ADDR, &s->ram); 47 47 + memory_region_add_subregion(get_system_memory(), FSL_IMX7_MMDC_ADDR, 48 48 + machine->ram); 57 49 58 50 for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { 59 51 BusState *bus; ··· 63 55 64 56 di = drive_get_next(IF_SD); 65 57 blk = di ? blk_by_legacy_dinfo(di) : NULL; 66 66 - bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus"); 58 58 + bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); 67 59 carddev = qdev_create(bus, TYPE_SD_CARD); 68 60 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 69 61 object_property_set_bool(OBJECT(carddev), true, ··· 71 63 } 72 64 73 65 if (!qtest_enabled()) { 74 74 - arm_load_kernel(&s->soc.cpu[0], machine, &boot_info); 66 66 + arm_load_kernel(&s->cpu[0], machine, &boot_info); 75 67 } 76 68 } 77 69 ··· 80 72 mc->desc = "Freescale i.MX7 DUAL SABRE (Cortex A7)"; 81 73 mc->init = mcimx7d_sabre_init; 82 74 mc->max_cpus = FSL_IMX7_NUM_CPUS; 75 75 + mc->default_ram_id = "mcimx7d-sabre.ram"; 83 76 } 84 77 DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init)

+11 -4

hw/arm/mps2-tz.c

··· 39 39 40 40 #include "qemu/osdep.h" 41 41 #include "qemu/units.h" 42 42 + #include "qemu/cutils.h" 42 43 #include "qapi/error.h" 43 44 #include "qemu/error-report.h" 44 45 #include "hw/arm/boot.h" ··· 79 80 MachineState parent; 80 81 81 82 ARMSSE iotkit; 82 82 - MemoryRegion psram; 83 83 MemoryRegion ssram[3]; 84 84 MemoryRegion ssram1_m; 85 85 MPS2SCC scc; ··· 388 388 exit(1); 389 389 } 390 390 391 391 + if (machine->ram_size != mc->default_ram_size) { 392 392 + char *sz = size_to_str(mc->default_ram_size); 393 393 + error_report("Invalid RAM size, should be %s", sz); 394 394 + g_free(sz); 395 395 + exit(EXIT_FAILURE); 396 396 + } 397 397 + 391 398 sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, 392 399 sizeof(mms->iotkit), mmc->armsse_type); 393 400 iotkitdev = DEVICE(&mms->iotkit); ··· 458 465 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily 459 466 * call the 16MB our "system memory", as it's the largest lump. 460 467 */ 461 461 - memory_region_allocate_system_memory(&mms->psram, 462 462 - NULL, "mps.ram", 16 * MiB); 463 463 - memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); 468 468 + memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 464 469 465 470 /* The overflow IRQs for all UARTs are ORed together. 466 471 * Tx, Rx and "combined" IRQs are sent to the NVIC separately. ··· 642 647 643 648 mc->init = mps2tz_common_init; 644 649 iic->check = mps2_tz_idau_check; 650 650 + mc->default_ram_size = 16 * MiB; 651 651 + mc->default_ram_id = "mps.ram"; 645 652 } 646 653 647 654 static void mps2tz_an505_class_init(ObjectClass *oc, void *data)

+11 -4

hw/arm/mps2.c

··· 24 24 25 25 #include "qemu/osdep.h" 26 26 #include "qemu/units.h" 27 27 + #include "qemu/cutils.h" 27 28 #include "qapi/error.h" 28 29 #include "qemu/error-report.h" 29 30 #include "hw/arm/boot.h" ··· 55 56 MachineState parent; 56 57 57 58 ARMv7MState armv7m; 58 58 - MemoryRegion psram; 59 59 MemoryRegion ssram1; 60 60 MemoryRegion ssram1_m; 61 61 MemoryRegion ssram23; ··· 118 118 exit(1); 119 119 } 120 120 121 121 + if (machine->ram_size != mc->default_ram_size) { 122 122 + char *sz = size_to_str(mc->default_ram_size); 123 123 + error_report("Invalid RAM size, should be %s", sz); 124 124 + g_free(sz); 125 125 + exit(EXIT_FAILURE); 126 126 + } 127 127 + 121 128 /* The FPGA images have an odd combination of different RAMs, 122 129 * because in hardware they are different implementations and 123 130 * connected to different buses, giving varying performance/size ··· 146 153 * This is of no use for QEMU so we don't implement it (as if 147 154 * zbt_boot_ctrl is always zero). 148 155 */ 149 149 - memory_region_allocate_system_memory(&mms->psram, 150 150 - NULL, "mps.ram", 16 * MiB); 151 151 - memory_region_add_subregion(system_memory, 0x21000000, &mms->psram); 156 156 + memory_region_add_subregion(system_memory, 0x21000000, machine->ram); 152 157 153 158 switch (mmc->fpga_type) { 154 159 case FPGA_AN385: ··· 338 343 339 344 mc->init = mps2_common_init; 340 345 mc->max_cpus = 1; 346 346 + mc->default_ram_size = 16 * MiB; 347 347 + mc->default_ram_id = "mps.ram"; 341 348 } 342 349 343 350 static void mps2_an385_class_init(ObjectClass *oc, void *data)

+13 -5

hw/arm/musicpal.c

··· 32 32 #include "sysemu/runstate.h" 33 33 #include "exec/address-spaces.h" 34 34 #include "ui/pixel_ops.h" 35 35 + #include "qemu/cutils.h" 35 36 36 37 #define MP_MISC_BASE 0x80002000 37 38 #define MP_MISC_SIZE 0x00001000 ··· 1589 1590 int i; 1590 1591 unsigned long flash_size; 1591 1592 DriveInfo *dinfo; 1593 1593 + MachineClass *mc = MACHINE_GET_CLASS(machine); 1592 1594 MemoryRegion *address_space_mem = get_system_memory(); 1593 1593 - MemoryRegion *ram = g_new(MemoryRegion, 1); 1594 1595 MemoryRegion *sram = g_new(MemoryRegion, 1); 1595 1596 1597 1597 + /* For now we use a fixed - the original - RAM size */ 1598 1598 + if (machine->ram_size != mc->default_ram_size) { 1599 1599 + char *sz = size_to_str(mc->default_ram_size); 1600 1600 + error_report("Invalid RAM size, should be %s", sz); 1601 1601 + g_free(sz); 1602 1602 + exit(EXIT_FAILURE); 1603 1603 + } 1604 1604 + 1596 1605 cpu = ARM_CPU(cpu_create(machine->cpu_type)); 1597 1606 1598 1598 - /* For now we use a fixed - the original - RAM size */ 1599 1599 - memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", 1600 1600 - MP_RAM_DEFAULT_SIZE); 1601 1601 - memory_region_add_subregion(address_space_mem, 0, ram); 1607 1607 + memory_region_add_subregion(address_space_mem, 0, machine->ram); 1602 1608 1603 1609 memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, 1604 1610 &error_fatal); ··· 1714 1720 mc->init = musicpal_init; 1715 1721 mc->ignore_memory_transaction_failures = true; 1716 1722 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 1723 1723 + mc->default_ram_size = MP_RAM_DEFAULT_SIZE; 1724 1724 + mc->default_ram_id = "musicpal.ram"; 1717 1725 } 1718 1726 1719 1727 DEFINE_MACHINE("musicpal", musicpal_machine_init)

+19 -13

hw/arm/nseries.c

··· 47 47 48 48 /* Nokia N8x0 support */ 49 49 struct n800_s { 50 50 - MemoryRegion sdram; 51 50 struct omap_mpu_state_s *mpu; 52 51 53 52 struct rfbi_chip_s blizzard; ··· 1311 1310 struct arm_boot_info *binfo, int model) 1312 1311 { 1313 1312 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); 1314 1314 - uint64_t sdram_size = binfo->ram_size; 1313 1313 + MachineClass *mc = MACHINE_GET_CLASS(machine); 1315 1314 1316 1316 - memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram", 1317 1317 - sdram_size); 1318 1318 - memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE, &s->sdram); 1315 1315 + if (machine->ram_size != mc->default_ram_size) { 1316 1316 + char *sz = size_to_str(mc->default_ram_size); 1317 1317 + error_report("Invalid RAM size, should be %s", sz); 1318 1318 + g_free(sz); 1319 1319 + exit(EXIT_FAILURE); 1320 1320 + } 1319 1321 1320 1320 - s->mpu = omap2420_mpu_init(&s->sdram, machine->cpu_type); 1322 1322 + memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE, 1323 1323 + machine->ram); 1324 1324 + 1325 1325 + s->mpu = omap2420_mpu_init(machine->ram, machine->cpu_type); 1321 1326 1322 1327 /* Setup peripherals 1323 1328 * ··· 1383 1388 * 1384 1389 * The code above is for loading the `zImage' file from Nokia 1385 1390 * images. */ 1386 1386 - load_image_targphys(option_rom[0].name, 1387 1387 - OMAP2_Q2_BASE + 0x400000, 1388 1388 - sdram_size - 0x400000); 1391 1391 + load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000, 1392 1392 + machine->ram_size - 0x400000); 1389 1393 1390 1394 n800_setup_nolo_tags(nolo_tags); 1391 1395 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); ··· 1395 1399 1396 1400 static struct arm_boot_info n800_binfo = { 1397 1401 .loader_start = OMAP2_Q2_BASE, 1398 1398 - /* Actually two chips of 0x4000000 bytes each */ 1399 1399 - .ram_size = 0x08000000, 1400 1402 .board_id = 0x4f7, 1401 1403 .atag_board = n800_atag_setup, 1402 1404 }; 1403 1405 1404 1406 static struct arm_boot_info n810_binfo = { 1405 1407 .loader_start = OMAP2_Q2_BASE, 1406 1406 - /* Actually two chips of 0x4000000 bytes each */ 1407 1407 - .ram_size = 0x08000000, 1408 1408 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not 1409 1409 * used by some older versions of the bootloader and 5555 is used 1410 1410 * instead (including versions that shipped with many devices). */ ··· 1431 1431 mc->default_boot_order = ""; 1432 1432 mc->ignore_memory_transaction_failures = true; 1433 1433 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); 1434 1434 + /* Actually two chips of 0x4000000 bytes each */ 1435 1435 + mc->default_ram_size = 0x08000000; 1436 1436 + mc->default_ram_id = "omap2.dram"; 1434 1437 } 1435 1438 1436 1439 static const TypeInfo n800_type = { ··· 1448 1451 mc->default_boot_order = ""; 1449 1452 mc->ignore_memory_transaction_failures = true; 1450 1453 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); 1454 1454 + /* Actually two chips of 0x4000000 bytes each */ 1455 1455 + mc->default_ram_size = 0x08000000; 1456 1456 + mc->default_ram_id = "omap2.dram"; 1451 1457 } 1452 1458 1453 1459 static const TypeInfo n810_type = {

+15 -5

hw/arm/omap_sx1.c

··· 35 35 #include "sysemu/qtest.h" 36 36 #include "exec/address-spaces.h" 37 37 #include "cpu.h" 38 38 + #include "qemu/cutils.h" 38 39 39 40 /*****************************************************************************/ 40 41 /* Siemens SX1 Cellphone V1 */ ··· 102 103 static void sx1_init(MachineState *machine, const int version) 103 104 { 104 105 struct omap_mpu_state_s *mpu; 106 106 + MachineClass *mc = MACHINE_GET_CLASS(machine); 105 107 MemoryRegion *address_space = get_system_memory(); 106 106 - MemoryRegion *dram = g_new(MemoryRegion, 1); 107 108 MemoryRegion *flash = g_new(MemoryRegion, 1); 108 109 MemoryRegion *cs = g_new(MemoryRegion, 4); 109 110 static uint32_t cs0val = 0x00213090; ··· 114 115 int fl_idx; 115 116 uint32_t flash_size = flash0_size; 116 117 int be; 118 118 + 119 119 + if (machine->ram_size != mc->default_ram_size) { 120 120 + char *sz = size_to_str(mc->default_ram_size); 121 121 + error_report("Invalid RAM size, should be %s", sz); 122 122 + g_free(sz); 123 123 + exit(EXIT_FAILURE); 124 124 + } 117 125 118 126 if (version == 2) { 119 127 flash_size = flash2_size; 120 128 } 121 129 122 122 - memory_region_allocate_system_memory(dram, NULL, "omap1.dram", 123 123 - sx1_binfo.ram_size); 124 124 - memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, dram); 130 130 + memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram); 125 131 126 126 - mpu = omap310_mpu_init(dram, machine->cpu_type); 132 132 + mpu = omap310_mpu_init(machine->ram, machine->cpu_type); 127 133 128 134 /* External Flash (EMIFS) */ 129 135 memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size, ··· 223 229 mc->init = sx1_init_v2; 224 230 mc->ignore_memory_transaction_failures = true; 225 231 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); 232 232 + mc->default_ram_size = sdram_size; 233 233 + mc->default_ram_id = "omap1.dram"; 226 234 } 227 235 228 236 static const TypeInfo sx1_machine_v2_type = { ··· 239 247 mc->init = sx1_init_v1; 240 248 mc->ignore_memory_transaction_failures = true; 241 249 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); 250 250 + mc->default_ram_size = sdram_size; 251 251 + mc->default_ram_id = "omap1.dram"; 242 252 } 243 253 244 254 static const TypeInfo sx1_machine_v1_type = {

+14 -5

hw/arm/palm.c

··· 31 31 #include "hw/loader.h" 32 32 #include "exec/address-spaces.h" 33 33 #include "cpu.h" 34 34 + #include "qemu/cutils.h" 34 35 35 36 static uint64_t static_read(void *opaque, hwaddr offset, unsigned size) 36 37 { ··· 195 196 static uint32_t cs2val = 0x0000e1a0; 196 197 static uint32_t cs3val = 0xe1a0e1a0; 197 198 int rom_size, rom_loaded = 0; 198 198 - MemoryRegion *dram = g_new(MemoryRegion, 1); 199 199 + MachineClass *mc = MACHINE_GET_CLASS(machine); 199 200 MemoryRegion *flash = g_new(MemoryRegion, 1); 200 201 MemoryRegion *cs = g_new(MemoryRegion, 4); 201 202 202 202 - memory_region_allocate_system_memory(dram, NULL, "omap1.dram", 203 203 - palmte_binfo.ram_size); 204 204 - memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE, dram); 203 203 + if (machine->ram_size != mc->default_ram_size) { 204 204 + char *sz = size_to_str(mc->default_ram_size); 205 205 + error_report("Invalid RAM size, should be %s", sz); 206 206 + g_free(sz); 207 207 + exit(EXIT_FAILURE); 208 208 + } 205 209 206 206 - mpu = omap310_mpu_init(dram, machine->cpu_type); 210 210 + memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE, 211 211 + machine->ram); 212 212 + 213 213 + mpu = omap310_mpu_init(machine->ram, machine->cpu_type); 207 214 208 215 /* External Flash (EMIFS) */ 209 216 memory_region_init_ram(flash, NULL, "palmte.flash", flash_size, ··· 265 272 mc->init = palmte_init; 266 273 mc->ignore_memory_transaction_failures = true; 267 274 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); 275 275 + mc->default_ram_size = 0x02000000; 276 276 + mc->default_ram_id = "omap1.dram"; 268 277 } 269 278 270 279 DEFINE_MACHINE("cheetah", palmte_machine_init)

+4 -6

hw/arm/raspi.c

··· 39 39 MachineState parent_obj; 40 40 /*< public >*/ 41 41 BCM283XState soc; 42 42 - MemoryRegion ram; 43 42 } RaspiMachineState; 44 43 45 44 typedef struct RaspiMachineClass { ··· 277 276 exit(1); 278 277 } 279 278 280 280 - /* Allocate and map RAM */ 281 281 - memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram", 282 282 - machine->ram_size); 283 279 /* FIXME: Remove when we have custom CPU address space support */ 284 284 - memory_region_add_subregion_overlap(get_system_memory(), 0, &s->ram, 0); 280 280 + memory_region_add_subregion_overlap(get_system_memory(), 0, 281 281 + machine->ram, 0); 285 282 286 283 /* Setup the SOC */ 287 284 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 288 285 board_soc_type(board_rev), &error_abort, NULL); 289 289 - object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), 286 286 + object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram), 290 287 &error_abort); 291 288 object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", 292 289 &error_abort); ··· 324 321 mc->no_cdrom = 1; 325 322 mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); 326 323 mc->default_ram_size = board_ram_size(board_rev); 324 324 + mc->default_ram_id = "ram"; 327 325 if (board_version(board_rev) == 2) { 328 326 mc->ignore_memory_transaction_failures = true; 329 327 }

+8 -15

hw/arm/sabrelite.c

··· 19 19 #include "qemu/error-report.h" 20 20 #include "sysemu/qtest.h" 21 21 22 22 - typedef struct IMX6Sabrelite { 23 23 - FslIMX6State soc; 24 24 - MemoryRegion ram; 25 25 - } IMX6Sabrelite; 26 26 - 27 22 static struct arm_boot_info sabrelite_binfo = { 28 23 /* DDR memory start */ 29 24 .loader_start = FSL_IMX6_MMDC_ADDR, ··· 45 40 46 41 static void sabrelite_init(MachineState *machine) 47 42 { 48 48 - IMX6Sabrelite *s = g_new0(IMX6Sabrelite, 1); 43 43 + FslIMX6State *s; 49 44 Error *err = NULL; 50 45 51 46 /* Check the amount of memory is compatible with the SOC */ ··· 55 50 exit(1); 56 51 } 57 52 58 58 - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 59 59 - TYPE_FSL_IMX6, &error_abort, NULL); 60 60 - 61 61 - object_property_set_bool(OBJECT(&s->soc), true, "realized", &err); 53 53 + s = FSL_IMX6(object_new(TYPE_FSL_IMX6)); 54 54 + object_property_add_child(OBJECT(machine), "soc", OBJECT(s), &error_fatal); 55 55 + object_property_set_bool(OBJECT(s), true, "realized", &err); 62 56 if (err != NULL) { 63 57 error_report("%s", error_get_pretty(err)); 64 58 exit(1); 65 59 } 66 60 67 67 - memory_region_allocate_system_memory(&s->ram, NULL, "sabrelite.ram", 68 68 - machine->ram_size); 69 61 memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR, 70 70 - &s->ram); 62 62 + machine->ram); 71 63 72 64 { 73 65 /* ··· 78 70 /* Add the sst25vf016b NOR FLASH memory to first SPI */ 79 71 Object *spi_dev; 80 72 81 81 - spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1"); 73 73 + spi_dev = object_resolve_path_component(OBJECT(s), "spi1"); 82 74 if (spi_dev) { 83 75 SSIBus *spi_bus; 84 76 ··· 109 101 sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary; 110 102 111 103 if (!qtest_enabled()) { 112 112 - arm_load_kernel(&s->soc.cpu[0], machine, &sabrelite_binfo); 104 104 + arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo); 113 105 } 114 106 } 115 107 ··· 119 111 mc->init = sabrelite_init; 120 112 mc->max_cpus = FSL_IMX6_NUM_CPUS; 121 113 mc->ignore_memory_transaction_failures = true; 114 114 + mc->default_ram_id = "sabrelite.ram"; 122 115 } 123 116 124 117 DEFINE_MACHINE("sabrelite", sabrelite_machine_init)

+3 -4

hw/arm/sbsa-ref.c

··· 593 593 MachineClass *mc = MACHINE_GET_CLASS(machine); 594 594 MemoryRegion *sysmem = get_system_memory(); 595 595 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); 596 596 - MemoryRegion *ram = g_new(MemoryRegion, 1); 597 596 bool firmware_loaded; 598 597 const CPUArchIdList *possible_cpus; 599 598 int n, sbsa_max_cpus; ··· 685 684 object_unref(cpuobj); 686 685 } 687 686 688 688 - memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram", 689 689 - machine->ram_size); 690 690 - memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram); 687 687 + memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, 688 688 + machine->ram); 691 689 692 690 create_fdt(sms); 693 691 ··· 785 783 mc->block_default_type = IF_IDE; 786 784 mc->no_cdrom = 1; 787 785 mc->default_ram_size = 1 * GiB; 786 786 + mc->default_ram_id = "sbsa-ref.ram"; 788 787 mc->default_cpus = 4; 789 788 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; 790 789 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;

+3 -4

hw/arm/versatilepb.c

··· 184 184 Object *cpuobj; 185 185 ARMCPU *cpu; 186 186 MemoryRegion *sysmem = get_system_memory(); 187 187 - MemoryRegion *ram = g_new(MemoryRegion, 1); 188 187 qemu_irq pic[32]; 189 188 qemu_irq sic[32]; 190 189 DeviceState *dev, *sysctl; ··· 220 219 221 220 cpu = ARM_CPU(cpuobj); 222 221 223 223 - memory_region_allocate_system_memory(ram, NULL, "versatile.ram", 224 224 - machine->ram_size); 225 222 /* ??? RAM should repeat to fill physical memory space. */ 226 223 /* SDRAM at address zero. */ 227 227 - memory_region_add_subregion(sysmem, 0, ram); 224 224 + memory_region_add_subregion(sysmem, 0, machine->ram); 228 225 229 226 sysctl = qdev_create(NULL, "realview_sysctl"); 230 227 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); ··· 398 395 mc->block_default_type = IF_SCSI; 399 396 mc->ignore_memory_transaction_failures = true; 400 397 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 398 398 + mc->default_ram_id = "versatile.ram"; 401 399 } 402 400 403 401 static const TypeInfo versatilepb_type = { ··· 415 413 mc->block_default_type = IF_SCSI; 416 414 mc->ignore_memory_transaction_failures = true; 417 415 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 416 416 + mc->default_ram_id = "versatile.ram"; 418 417 } 419 418 420 419 static const TypeInfo versatileab_type = {

+5 -9

hw/arm/vexpress.c

··· 273 273 { 274 274 MachineState *machine = MACHINE(vms); 275 275 MemoryRegion *sysmem = get_system_memory(); 276 276 - MemoryRegion *ram = g_new(MemoryRegion, 1); 277 276 MemoryRegion *lowram = g_new(MemoryRegion, 1); 278 277 ram_addr_t low_ram_size; 279 278 ··· 283 282 exit(1); 284 283 } 285 284 286 286 - memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 287 287 - ram_size); 288 285 low_ram_size = ram_size; 289 286 if (low_ram_size > 0x4000000) { 290 287 low_ram_size = 0x4000000; ··· 293 290 * address space should in theory be remappable to various 294 291 * things including ROM or RAM; we always map the RAM there. 295 292 */ 296 296 - memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); 293 293 + memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram, 294 294 + 0, low_ram_size); 297 295 memory_region_add_subregion(sysmem, 0x0, lowram); 298 298 - memory_region_add_subregion(sysmem, 0x60000000, ram); 296 296 + memory_region_add_subregion(sysmem, 0x60000000, machine->ram); 299 297 300 298 /* 0x1e000000 A9MPCore (SCU) private memory region */ 301 299 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, ··· 360 358 { 361 359 MachineState *machine = MACHINE(vms); 362 360 MemoryRegion *sysmem = get_system_memory(); 363 363 - MemoryRegion *ram = g_new(MemoryRegion, 1); 364 361 MemoryRegion *sram = g_new(MemoryRegion, 1); 365 362 366 363 { ··· 375 372 } 376 373 } 377 374 378 378 - memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", 379 379 - ram_size); 380 375 /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ 381 381 - memory_region_add_subregion(sysmem, 0x80000000, ram); 376 376 + memory_region_add_subregion(sysmem, 0x80000000, machine->ram); 382 377 383 378 /* 0x2c000000 A15MPCore private memory region (GIC) */ 384 379 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV, ··· 795 790 mc->init = vexpress_common_init; 796 791 mc->max_cpus = 4; 797 792 mc->ignore_memory_transaction_failures = true; 793 793 + mc->default_ram_id = "vexpress.highmem"; 798 794 } 799 795 800 796 static void vexpress_a9_class_init(ObjectClass *oc, void *data)

+3 -4

hw/arm/virt.c

··· 1512 1512 MemoryRegion *sysmem = get_system_memory(); 1513 1513 MemoryRegion *secure_sysmem = NULL; 1514 1514 int n, virt_max_cpus; 1515 1515 - MemoryRegion *ram = g_new(MemoryRegion, 1); 1516 1515 bool firmware_loaded; 1517 1516 bool aarch64 = true; 1518 1517 bool has_ged = !vmc->no_ged; ··· 1706 1705 } 1707 1706 } 1708 1707 1709 1709 - memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", 1710 1710 - machine->ram_size); 1711 1711 - memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); 1708 1708 + memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 1709 1709 + machine->ram); 1712 1710 if (machine->device_memory) { 1713 1711 memory_region_add_subregion(sysmem, machine->device_memory->base, 1714 1712 &machine->device_memory->mr); ··· 2058 2056 hc->unplug_request = virt_machine_device_unplug_request_cb; 2059 2057 mc->numa_mem_supported = true; 2060 2058 mc->auto_enable_numa_with_memhp = true; 2059 2059 + mc->default_ram_id = "mach-virt.ram"; 2061 2060 } 2062 2061 2063 2062 static void virt_instance_init(Object *obj)

+9 -11

hw/arm/xilinx_zynq.c

··· 158 158 159 159 static void zynq_init(MachineState *machine) 160 160 { 161 161 - ram_addr_t ram_size = machine->ram_size; 162 161 ARMCPU *cpu; 163 162 MemoryRegion *address_space_mem = get_system_memory(); 164 164 - MemoryRegion *ext_ram = g_new(MemoryRegion, 1); 165 163 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); 166 164 DeviceState *dev; 167 165 SysBusDevice *busdev; 168 166 qemu_irq pic[64]; 169 167 int n; 168 168 + 169 169 + /* max 2GB ram */ 170 170 + if (machine->ram_size > 2 * GiB) { 171 171 + error_report("RAM size more than 2 GiB is not supported"); 172 172 + exit(EXIT_FAILURE); 173 173 + } 170 174 171 175 cpu = ARM_CPU(object_new(machine->cpu_type)); 172 176 ··· 184 188 &error_fatal); 185 189 object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); 186 190 187 187 - /* max 2GB ram */ 188 188 - if (ram_size > 0x80000000) { 189 189 - ram_size = 0x80000000; 190 190 - } 191 191 - 192 191 /* DDR remapped to address zero. */ 193 193 - memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram", 194 194 - ram_size); 195 195 - memory_region_add_subregion(address_space_mem, 0, ext_ram); 192 192 + memory_region_add_subregion(address_space_mem, 0, machine->ram); 196 193 197 194 /* 256K of on-chip memory */ 198 195 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, ··· 300 297 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); 301 298 sysbus_mmio_map(busdev, 0, 0xF8007000); 302 299 303 303 - zynq_binfo.ram_size = ram_size; 300 300 + zynq_binfo.ram_size = machine->ram_size; 304 301 zynq_binfo.nb_cpus = 1; 305 302 zynq_binfo.board_id = 0xd32; 306 303 zynq_binfo.loader_start = 0; ··· 318 315 mc->no_sdcard = 1; 319 316 mc->ignore_memory_transaction_failures = true; 320 317 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); 318 318 + mc->default_ram_id = "zynq.ext_ram"; 321 319 } 322 320 323 321 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)

+2 -5

hw/arm/xlnx-versal-virt.c

··· 30 30 MachineState parent_obj; 31 31 32 32 Versal soc; 33 33 - MemoryRegion mr_ddr; 34 33 35 34 void *fdt; 36 35 int fdt_size; ··· 414 413 psci_conduit = QEMU_PSCI_CONDUIT_SMC; 415 414 } 416 415 417 417 - memory_region_allocate_system_memory(&s->mr_ddr, NULL, "ddr", 418 418 - machine->ram_size); 419 419 - 420 416 sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc, 421 417 sizeof(s->soc), TYPE_XLNX_VERSAL); 422 422 - object_property_set_link(OBJECT(&s->soc), OBJECT(&s->mr_ddr), 418 418 + object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram), 423 419 "ddr", &error_abort); 424 420 object_property_set_int(OBJECT(&s->soc), psci_conduit, 425 421 "psci-conduit", &error_abort); ··· 473 469 mc->max_cpus = XLNX_VERSAL_NR_ACPUS; 474 470 mc->default_cpus = XLNX_VERSAL_NR_ACPUS; 475 471 mc->no_cdrom = true; 472 472 + mc->default_ram_id = "ddr"; 476 473 } 477 474 478 475 static const TypeInfo versal_virt_machine_init_typeinfo = {

+2 -5

hw/arm/xlnx-zcu102.c

··· 28 28 MachineState parent_obj; 29 29 30 30 XlnxZynqMPState soc; 31 31 - MemoryRegion ddr_ram; 32 31 33 32 bool secure; 34 33 bool virt; ··· 87 86 ram_size); 88 87 } 89 88 90 90 - memory_region_allocate_system_memory(&s->ddr_ram, NULL, "ddr-ram", 91 91 - ram_size); 92 92 - 93 89 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 94 90 TYPE_XLNX_ZYNQMP, &error_abort, NULL); 95 91 96 96 - object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram), 92 92 + object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram), 97 93 "ddr-ram", &error_abort); 98 94 object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", 99 95 &error_fatal); ··· 211 207 mc->ignore_memory_transaction_failures = true; 212 208 mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; 213 209 mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; 210 210 + mc->default_ram_id = "ddr-ram"; 214 211 } 215 212 216 213 static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {

+48

hw/core/machine.c

··· 26 26 #include "sysemu/qtest.h" 27 27 #include "hw/pci/pci.h" 28 28 #include "hw/mem/nvdimm.h" 29 29 + #include "migration/vmstate.h" 29 30 30 31 GlobalProperty hw_compat_4_2[] = { 31 32 { "virtio-blk-device", "queue-size", "128"}, ··· 510 511 } 511 512 } 512 513 514 514 + static char *machine_get_memdev(Object *obj, Error **errp) 515 515 + { 516 516 + MachineState *ms = MACHINE(obj); 517 517 + 518 518 + return g_strdup(ms->ram_memdev_id); 519 519 + } 520 520 + 521 521 + static void machine_set_memdev(Object *obj, const char *value, Error **errp) 522 522 + { 523 523 + MachineState *ms = MACHINE(obj); 524 524 + 525 525 + g_free(ms->ram_memdev_id); 526 526 + ms->ram_memdev_id = g_strdup(value); 527 527 + } 528 528 + 529 529 + 513 530 static void machine_init_notify(Notifier *notifier, void *data) 514 531 { 515 532 MachineState *machine = MACHINE(qdev_get_machine()); ··· 891 908 "Table (HMAT)", NULL); 892 909 } 893 910 911 911 + object_property_add_str(obj, "memory-backend", 912 912 + machine_get_memdev, machine_set_memdev, 913 913 + &error_abort); 914 914 + object_property_set_description(obj, "memory-backend", 915 915 + "Set RAM backend" 916 916 + "Valid value is ID of hostmem based backend", 917 917 + &error_abort); 918 918 + 894 919 /* Register notifier when init is done for sysbus sanity checks */ 895 920 ms->sysbus_notifier.notify = machine_init_notify; 896 921 qemu_add_machine_init_done_notifier(&ms->sysbus_notifier); ··· 1037 1062 g_string_free(s, true); 1038 1063 } 1039 1064 1065 1065 + MemoryRegion *machine_consume_memdev(MachineState *machine, 1066 1066 + HostMemoryBackend *backend) 1067 1067 + { 1068 1068 + MemoryRegion *ret = host_memory_backend_get_memory(backend); 1069 1069 + 1070 1070 + if (memory_region_is_mapped(ret)) { 1071 1071 + char *path = object_get_canonical_path_component(OBJECT(backend)); 1072 1072 + error_report("memory backend %s can't be used multiple times.", path); 1073 1073 + g_free(path); 1074 1074 + exit(EXIT_FAILURE); 1075 1075 + } 1076 1076 + host_memory_backend_set_mapped(backend, true); 1077 1077 + vmstate_register_ram_global(ret); 1078 1078 + return ret; 1079 1079 + } 1080 1080 + 1040 1081 void machine_run_board_init(MachineState *machine) 1041 1082 { 1042 1083 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1084 1084 + 1085 1085 + if (machine->ram_memdev_id) { 1086 1086 + Object *o; 1087 1087 + o = object_resolve_path_type(machine->ram_memdev_id, 1088 1088 + TYPE_MEMORY_BACKEND, NULL); 1089 1089 + machine->ram = machine_consume_memdev(machine, MEMORY_BACKEND(o)); 1090 1090 + } 1043 1091 1044 1092 if (machine->numa_state) { 1045 1093 numa_complete_configuration(machine);

+3 -5

hw/core/null-machine.c

··· 32 32 } 33 33 34 34 /* RAM at address zero */ 35 35 - if (mch->ram_size) { 36 36 - MemoryRegion *ram = g_new(MemoryRegion, 1); 37 37 - 38 38 - memory_region_allocate_system_memory(ram, NULL, "ram", mch->ram_size); 39 39 - memory_region_add_subregion(get_system_memory(), 0, ram); 35 35 + if (mch->ram) { 36 36 + memory_region_add_subregion(get_system_memory(), 0, mch->ram); 40 37 } 41 38 42 39 if (mch->kernel_filename) { ··· 52 49 mc->init = machine_none_init; 53 50 mc->max_cpus = 1; 54 51 mc->default_ram_size = 0; 52 52 + mc->default_ram_id = "ram"; 55 53 } 56 54 57 55 DEFINE_MACHINE("none", machine_none_machine_init)

+28 -73

hw/core/numa.c

··· 52 52 }; 53 53 54 54 static int have_memdevs; 55 55 + bool numa_uses_legacy_mem(void) 56 56 + { 57 57 + return !have_memdevs; 58 58 + } 59 59 + 55 60 static int have_mem; 56 61 static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one. 57 62 * For all nodes, nodeid < max_numa_nodeid ··· 652 657 nodes[i].node_mem = size - usedmem; 653 658 } 654 659 660 660 + static void numa_init_memdev_container(MachineState *ms, MemoryRegion *ram) 661 661 + { 662 662 + int i; 663 663 + uint64_t addr = 0; 664 664 + 665 665 + for (i = 0; i < ms->numa_state->num_nodes; i++) { 666 666 + uint64_t size = ms->numa_state->nodes[i].node_mem; 667 667 + HostMemoryBackend *backend = ms->numa_state->nodes[i].node_memdev; 668 668 + if (!backend) { 669 669 + continue; 670 670 + } 671 671 + MemoryRegion *seg = machine_consume_memdev(ms, backend); 672 672 + memory_region_add_subregion(ram, addr, seg); 673 673 + addr += size; 674 674 + } 675 675 + } 676 676 + 655 677 void numa_complete_configuration(MachineState *ms) 656 678 { 657 679 int i; ··· 734 756 exit(1); 735 757 } 736 758 759 759 + if (!numa_uses_legacy_mem() && mc->default_ram_id) { 760 760 + ms->ram = g_new(MemoryRegion, 1); 761 761 + memory_region_init(ms->ram, OBJECT(ms), mc->default_ram_id, 762 762 + ram_size); 763 763 + numa_init_memdev_container(ms, ms->ram); 764 764 + } 737 765 /* QEMU needs at least all unique node pair distances to build 738 766 * the whole NUMA distance table. QEMU treats the distance table 739 767 * as symmetric by default, i.e. distance A->B == distance B->A. ··· 775 803 } else if (node_id != slot->props.node_id) { 776 804 error_setg(errp, "invalid node-id, must be %"PRId64, 777 805 slot->props.node_id); 778 778 - } 779 779 - } 780 780 - 781 781 - static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner, 782 782 - const char *name, 783 783 - uint64_t ram_size) 784 784 - { 785 785 - if (mem_path) { 786 786 - #ifdef __linux__ 787 787 - Error *err = NULL; 788 788 - memory_region_init_ram_from_file(mr, owner, name, ram_size, 0, 0, 789 789 - mem_path, &err); 790 790 - if (err) { 791 791 - error_report_err(err); 792 792 - if (mem_prealloc) { 793 793 - exit(1); 794 794 - } 795 795 - warn_report("falling back to regular RAM allocation"); 796 796 - error_printf("This is deprecated. Make sure that -mem-path " 797 797 - " specified path has sufficient resources to allocate" 798 798 - " -m specified RAM amount\n"); 799 799 - /* Legacy behavior: if allocation failed, fall back to 800 800 - * regular RAM allocation. 801 801 - */ 802 802 - mem_path = NULL; 803 803 - memory_region_init_ram_nomigrate(mr, owner, name, ram_size, &error_fatal); 804 804 - } 805 805 - #else 806 806 - fprintf(stderr, "-mem-path not supported on this host\n"); 807 807 - exit(1); 808 808 - #endif 809 809 - } else { 810 810 - memory_region_init_ram_nomigrate(mr, owner, name, ram_size, &error_fatal); 811 811 - } 812 812 - vmstate_register_ram_global(mr); 813 813 - } 814 814 - 815 815 - void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, 816 816 - const char *name, 817 817 - uint64_t ram_size) 818 818 - { 819 819 - uint64_t addr = 0; 820 820 - int i; 821 821 - MachineState *ms = MACHINE(qdev_get_machine()); 822 822 - 823 823 - if (ms->numa_state == NULL || 824 824 - ms->numa_state->num_nodes == 0 || !have_memdevs) { 825 825 - allocate_system_memory_nonnuma(mr, owner, name, ram_size); 826 826 - return; 827 827 - } 828 828 - 829 829 - memory_region_init(mr, owner, name, ram_size); 830 830 - for (i = 0; i < ms->numa_state->num_nodes; i++) { 831 831 - uint64_t size = ms->numa_state->nodes[i].node_mem; 832 832 - HostMemoryBackend *backend = ms->numa_state->nodes[i].node_memdev; 833 833 - if (!backend) { 834 834 - continue; 835 835 - } 836 836 - MemoryRegion *seg = host_memory_backend_get_memory(backend); 837 837 - 838 838 - if (memory_region_is_mapped(seg)) { 839 839 - char *path = object_get_canonical_path_component(OBJECT(backend)); 840 840 - error_report("memory backend %s is used multiple times. Each " 841 841 - "-numa option must use a different memdev value.", 842 842 - path); 843 843 - g_free(path); 844 844 - exit(1); 845 845 - } 846 846 - 847 847 - host_memory_backend_set_mapped(backend, true); 848 848 - memory_region_add_subregion(mr, addr, seg); 849 849 - vmstate_register_ram_global(seg); 850 850 - addr += size; 851 806 } 852 807 } 853 808

+2 -6

hw/cris/axis_dev88.c

··· 249 249 static 250 250 void axisdev88_init(MachineState *machine) 251 251 { 252 252 - ram_addr_t ram_size = machine->ram_size; 253 252 const char *kernel_filename = machine->kernel_filename; 254 253 const char *kernel_cmdline = machine->kernel_cmdline; 255 254 CRISCPU *cpu; ··· 261 260 struct etraxfs_dma_client *dma_eth; 262 261 int i; 263 262 MemoryRegion *address_space_mem = get_system_memory(); 264 264 - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 265 263 MemoryRegion *phys_intmem = g_new(MemoryRegion, 1); 266 264 267 265 /* init CPUs */ 268 266 cpu = CRIS_CPU(cpu_create(machine->cpu_type)); 269 267 270 270 - /* allocate RAM */ 271 271 - memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram", 272 272 - ram_size); 273 273 - memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram); 268 268 + memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram); 274 269 275 270 /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 276 271 internal memory. */ ··· 351 346 mc->init = axisdev88_init; 352 347 mc->is_default = 1; 353 348 mc->default_cpu_type = CRIS_CPU_TYPE_NAME("crisv32"); 349 349 + mc->default_ram_id = "axisdev88.ram"; 354 350 } 355 351 356 352 DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)

+3 -7

hw/hppa/machine.c

··· 71 71 uint64_t kernel_entry = 0, kernel_low, kernel_high; 72 72 MemoryRegion *addr_space = get_system_memory(); 73 73 MemoryRegion *rom_region; 74 74 - MemoryRegion *ram_region; 75 74 MemoryRegion *cpu_region; 76 75 long i; 77 76 unsigned int smp_cpus = machine->smp.cpus; 78 77 SysBusDevice *s; 79 79 - 80 80 - ram_size = machine->ram_size; 81 78 82 79 /* Create CPUs. */ 83 80 for (i = 0; i < smp_cpus; i++) { ··· 97 94 error_report("RAM size is currently restricted to 3GB"); 98 95 exit(EXIT_FAILURE); 99 96 } 100 100 - ram_region = g_new(MemoryRegion, 1); 101 101 - memory_region_allocate_system_memory(ram_region, OBJECT(machine), 102 102 - "ram", ram_size); 103 103 - memory_region_add_subregion_overlap(addr_space, 0, ram_region, -1); 97 97 + memory_region_add_subregion_overlap(addr_space, 0, machine->ram, -1); 98 98 + 104 99 105 100 /* Init Lasi chip */ 106 101 lasi_init(addr_space); ··· 298 293 mc->is_default = 1; 299 294 mc->default_ram_size = 512 * MiB; 300 295 mc->default_boot_order = "cd"; 296 296 + mc->default_ram_id = "ram"; 301 297 } 302 298 303 299 DEFINE_MACHINE("hppa", machine_hppa_machine_init)

+5 -7

hw/i386/microvm.c

··· 167 167 { 168 168 MachineState *machine = MACHINE(mms); 169 169 X86MachineState *x86ms = X86_MACHINE(mms); 170 170 - MemoryRegion *ram, *ram_below_4g, *ram_above_4g; 170 170 + MemoryRegion *ram_below_4g, *ram_above_4g; 171 171 MemoryRegion *system_memory = get_system_memory(); 172 172 FWCfgState *fw_cfg; 173 173 ram_addr_t lowmem; ··· 214 214 x86ms->below_4g_mem_size = machine->ram_size; 215 215 } 216 216 217 217 - ram = g_malloc(sizeof(*ram)); 218 218 - memory_region_allocate_system_memory(ram, NULL, "microvm.ram", 219 219 - machine->ram_size); 220 220 - 221 217 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 222 222 - memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 218 218 + memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 223 219 0, x86ms->below_4g_mem_size); 224 220 memory_region_add_subregion(system_memory, 0, ram_below_4g); 225 221 ··· 227 223 228 224 if (x86ms->above_4g_mem_size > 0) { 229 225 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 230 230 - memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 226 226 + memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 227 227 + machine->ram, 231 228 x86ms->below_4g_mem_size, 232 229 x86ms->above_4g_mem_size); 233 230 memory_region_add_subregion(system_memory, 0x100000000ULL, ··· 502 499 mc->auto_enable_numa_with_memhp = false; 503 500 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 504 501 mc->nvdimm_supported = false; 502 502 + mc->default_ram_id = "microvm.ram"; 505 503 506 504 /* Avoid relying too much on kernel components */ 507 505 mc->default_kernel_irqchip_split = true;

+9 -10

hw/i386/pc.c

··· 937 937 MemoryRegion **ram_memory) 938 938 { 939 939 int linux_boot, i; 940 940 - MemoryRegion *ram, *option_rom_mr; 940 940 + MemoryRegion *option_rom_mr; 941 941 MemoryRegion *ram_below_4g, *ram_above_4g; 942 942 FWCfgState *fw_cfg; 943 943 MachineState *machine = MACHINE(pcms); ··· 950 950 951 951 linux_boot = (machine->kernel_filename != NULL); 952 952 953 953 - /* Allocate RAM. We allocate it as a single memory region and use 954 954 - * aliases to address portions of it, mostly for backwards compatibility 955 955 - * with older qemus that used qemu_ram_alloc(). 953 953 + /* 954 954 + * Split single memory region and use aliases to address portions of it, 955 955 + * done for backwards compatibility with older qemus. 956 956 */ 957 957 - ram = g_malloc(sizeof(*ram)); 958 958 - memory_region_allocate_system_memory(ram, NULL, "pc.ram", 959 959 - machine->ram_size); 960 960 - *ram_memory = ram; 957 957 + *ram_memory = machine->ram; 961 958 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 962 962 - memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 959 959 + memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 963 960 0, x86ms->below_4g_mem_size); 964 961 memory_region_add_subregion(system_memory, 0, ram_below_4g); 965 962 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 966 963 if (x86ms->above_4g_mem_size > 0) { 967 964 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 968 968 - memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 965 965 + memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 966 966 + machine->ram, 969 967 x86ms->below_4g_mem_size, 970 968 x86ms->above_4g_mem_size); 971 969 memory_region_add_subregion(system_memory, 0x100000000ULL, ··· 1952 1950 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1953 1951 mc->nvdimm_supported = true; 1954 1952 mc->numa_mem_supported = true; 1953 1953 + mc->default_ram_id = "pc.ram"; 1955 1954 1956 1955 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1957 1956 pc_machine_get_device_memory_region_size, NULL,

+26 -13

hw/lm32/lm32_boards.c

··· 19 19 20 20 #include "qemu/osdep.h" 21 21 #include "qemu/units.h" 22 22 + #include "qemu/cutils.h" 22 23 #include "qemu/error-report.h" 23 24 #include "cpu.h" 24 25 #include "hw/sysbus.h" ··· 75 76 76 77 static void lm32_evr_init(MachineState *machine) 77 78 { 79 79 + MachineClass *mc = MACHINE_GET_CLASS(machine); 78 80 const char *kernel_filename = machine->kernel_filename; 79 81 LM32CPU *cpu; 80 82 CPULM32State *env; 81 83 DriveInfo *dinfo; 82 84 MemoryRegion *address_space_mem = get_system_memory(); 83 83 - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 84 85 qemu_irq irq[32]; 85 86 ResetInfo *reset_info; 86 87 int i; 88 88 + 89 89 + if (machine->ram_size != mc->default_ram_size) { 90 90 + char *sz = size_to_str(mc->default_ram_size); 91 91 + error_report("Invalid RAM size, should be %s", sz); 92 92 + g_free(sz); 93 93 + exit(EXIT_FAILURE); 94 94 + } 87 95 88 96 /* memory map */ 89 97 hwaddr flash_base = 0x04000000; 90 98 size_t flash_sector_size = 256 * KiB; 91 99 size_t flash_size = 32 * MiB; 92 100 hwaddr ram_base = 0x08000000; 93 93 - size_t ram_size = 64 * MiB; 94 101 hwaddr timer0_base = 0x80002000; 95 102 hwaddr uart0_base = 0x80006000; 96 103 hwaddr timer1_base = 0x8000a000; ··· 107 114 108 115 reset_info->flash_base = flash_base; 109 116 110 110 - memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram", 111 111 - ram_size); 112 112 - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); 117 117 + memory_region_add_subregion(address_space_mem, ram_base, machine->ram); 113 118 114 119 dinfo = drive_get(IF_PFLASH, 0, 0); 115 120 /* Spansion S29NS128P */ ··· 144 149 145 150 if (kernel_size < 0) { 146 151 kernel_size = load_image_targphys(kernel_filename, ram_base, 147 147 - ram_size); 152 152 + machine->ram_size); 148 153 reset_info->bootstrap_pc = ram_base; 149 154 } 150 155 ··· 159 164 160 165 static void lm32_uclinux_init(MachineState *machine) 161 166 { 167 167 + MachineClass *mc = MACHINE_GET_CLASS(machine); 162 168 const char *kernel_filename = machine->kernel_filename; 163 169 const char *kernel_cmdline = machine->kernel_cmdline; 164 170 const char *initrd_filename = machine->initrd_filename; ··· 166 172 CPULM32State *env; 167 173 DriveInfo *dinfo; 168 174 MemoryRegion *address_space_mem = get_system_memory(); 169 169 - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 170 175 qemu_irq irq[32]; 171 176 HWSetup *hw; 172 177 ResetInfo *reset_info; 173 178 int i; 174 179 180 180 + if (machine->ram_size != mc->default_ram_size) { 181 181 + char *sz = size_to_str(mc->default_ram_size); 182 182 + error_report("Invalid RAM size, should be %s", sz); 183 183 + g_free(sz); 184 184 + exit(EXIT_FAILURE); 185 185 + } 186 186 + 175 187 /* memory map */ 176 188 hwaddr flash_base = 0x04000000; 177 189 size_t flash_sector_size = 256 * KiB; 178 190 size_t flash_size = 32 * MiB; 179 191 hwaddr ram_base = 0x08000000; 180 180 - size_t ram_size = 64 * MiB; 181 192 hwaddr uart0_base = 0x80000000; 182 193 hwaddr timer0_base = 0x80002000; 183 194 hwaddr timer1_base = 0x80010000; ··· 200 211 201 212 reset_info->flash_base = flash_base; 202 213 203 203 - memory_region_allocate_system_memory(phys_ram, NULL, 204 204 - "lm32_uclinux.sdram", ram_size); 205 205 - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); 214 214 + memory_region_add_subregion(address_space_mem, ram_base, machine->ram); 206 215 207 216 dinfo = drive_get(IF_PFLASH, 0, 0); 208 217 /* Spansion S29NS128P */ ··· 238 247 239 248 if (kernel_size < 0) { 240 249 kernel_size = load_image_targphys(kernel_filename, ram_base, 241 241 - ram_size); 250 250 + machine->ram_size); 242 251 reset_info->bootstrap_pc = ram_base; 243 252 } 244 253 ··· 252 261 hw = hwsetup_init(); 253 262 hwsetup_add_cpu(hw, "LM32", 75000000); 254 263 hwsetup_add_flash(hw, "flash", flash_base, flash_size); 255 255 - hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size); 264 264 + hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, machine->ram_size); 256 265 hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq); 257 266 hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq); 258 267 hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq); ··· 288 297 mc->init = lm32_evr_init; 289 298 mc->is_default = 1; 290 299 mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); 300 300 + mc->default_ram_size = 64 * MiB; 301 301 + mc->default_ram_id = "lm32_evr.sdram"; 291 302 } 292 303 293 304 static const TypeInfo lm32_evr_type = { ··· 304 315 mc->init = lm32_uclinux_init; 305 316 mc->is_default = 0; 306 317 mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); 318 318 + mc->default_ram_size = 64 * MiB; 319 319 + mc->default_ram_id = "lm32_uclinux.sdram"; 307 320 } 308 321 309 322 static const TypeInfo lm32_uclinux_type = {

+14 -7

hw/lm32/milkymist.c

··· 36 36 #include "hw/display/milkymist_tmu2.h" 37 37 #include "lm32.h" 38 38 #include "exec/address-spaces.h" 39 39 + #include "qemu/cutils.h" 39 40 40 41 #define BIOS_FILENAME "mmone-bios.bin" 41 42 #define BIOS_OFFSET 0x00860000 ··· 82 83 static void 83 84 milkymist_init(MachineState *machine) 84 85 { 86 86 + MachineClass *mc = MACHINE_GET_CLASS(machine); 85 87 const char *kernel_filename = machine->kernel_filename; 86 88 const char *kernel_cmdline = machine->kernel_cmdline; 87 89 const char *initrd_filename = machine->initrd_filename; ··· 90 92 int kernel_size; 91 93 DriveInfo *dinfo; 92 94 MemoryRegion *address_space_mem = get_system_memory(); 93 93 - MemoryRegion *phys_sdram = g_new(MemoryRegion, 1); 94 95 qemu_irq irq[32]; 95 96 int i; 96 97 char *bios_filename; 97 98 ResetInfo *reset_info; 98 99 100 100 + if (machine->ram_size != mc->default_ram_size) { 101 101 + char *sz = size_to_str(mc->default_ram_size); 102 102 + error_report("Invalid RAM size, should be %s", sz); 103 103 + g_free(sz); 104 104 + exit(EXIT_FAILURE); 105 105 + } 106 106 + 99 107 /* memory map */ 100 108 hwaddr flash_base = 0x00000000; 101 109 size_t flash_sector_size = 128 * KiB; 102 110 size_t flash_size = 32 * MiB; 103 111 hwaddr sdram_base = 0x40000000; 104 104 - size_t sdram_size = 128 * MiB; 105 112 106 113 hwaddr initrd_base = sdram_base + 0x1002000; 107 114 hwaddr cmdline_base = sdram_base + 0x1000000; 108 108 - size_t initrd_max = sdram_size - 0x1002000; 115 115 + size_t initrd_max = machine->ram_size - 0x1002000; 109 116 110 117 reset_info = g_malloc0(sizeof(ResetInfo)); 111 118 ··· 116 123 117 124 cpu_lm32_set_phys_msb_ignore(env, 1); 118 125 119 119 - memory_region_allocate_system_memory(phys_sdram, NULL, "milkymist.sdram", 120 120 - sdram_size); 121 121 - memory_region_add_subregion(address_space_mem, sdram_base, phys_sdram); 126 126 + memory_region_add_subregion(address_space_mem, sdram_base, machine->ram); 122 127 123 128 dinfo = drive_get(IF_PFLASH, 0, 0); 124 129 /* Numonyx JS28F256J3F105 */ ··· 183 188 184 189 if (kernel_size < 0) { 185 190 kernel_size = load_image_targphys(kernel_filename, sdram_base, 186 186 - sdram_size); 191 191 + machine->ram_size); 187 192 reset_info->bootstrap_pc = sdram_base; 188 193 } 189 194 ··· 216 221 mc->init = milkymist_init; 217 222 mc->is_default = 0; 218 223 mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); 224 224 + mc->default_ram_size = 128 * MiB; 225 225 + mc->default_ram_id = "milkymist.sdram"; 219 226 } 220 227 221 228 DEFINE_MACHINE("milkymist", milkymist_machine_init)

+2 -3

hw/m68k/an5206.c

··· 33 33 uint64_t elf_entry; 34 34 hwaddr entry; 35 35 MemoryRegion *address_space_mem = get_system_memory(); 36 36 - MemoryRegion *ram = g_new(MemoryRegion, 1); 37 36 MemoryRegion *sram = g_new(MemoryRegion, 1); 38 37 39 38 cpu = M68K_CPU(cpu_create(machine->cpu_type)); ··· 46 45 env->rambar0 = AN5206_RAMBAR_ADDR | 1; 47 46 48 47 /* DRAM at address zero */ 49 49 - memory_region_allocate_system_memory(ram, NULL, "an5206.ram", ram_size); 50 50 - memory_region_add_subregion(address_space_mem, 0, ram); 48 48 + memory_region_add_subregion(address_space_mem, 0, machine->ram); 51 49 52 50 /* Internal SRAM. */ 53 51 memory_region_init_ram(sram, NULL, "an5206.sram", 512, &error_fatal); ··· 89 87 mc->desc = "Arnewsh 5206"; 90 88 mc->init = an5206_init; 91 89 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5206"); 90 90 + mc->default_ram_id = "an5206.ram"; 92 91 } 93 92 94 93 DEFINE_MACHINE("an5206", an5206_machine_init)

+2 -3

hw/m68k/mcf5208.c

··· 234 234 qemu_irq *pic; 235 235 MemoryRegion *address_space_mem = get_system_memory(); 236 236 MemoryRegion *rom = g_new(MemoryRegion, 1); 237 237 - MemoryRegion *ram = g_new(MemoryRegion, 1); 238 237 MemoryRegion *sram = g_new(MemoryRegion, 1); 239 238 240 239 cpu = M68K_CPU(cpu_create(machine->cpu_type)); ··· 249 248 memory_region_add_subregion(address_space_mem, 0x00000000, rom); 250 249 251 250 /* DRAM at 0x40000000 */ 252 252 - memory_region_allocate_system_memory(ram, NULL, "mcf5208.ram", ram_size); 253 253 - memory_region_add_subregion(address_space_mem, 0x40000000, ram); 251 251 + memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram); 254 252 255 253 /* Internal SRAM. */ 256 254 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal); ··· 354 352 mc->init = mcf5208evb_init; 355 353 mc->is_default = 1; 356 354 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208"); 355 355 + mc->default_ram_id = "mcf5208.ram"; 357 356 } 358 357 359 358 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init)

+2 -3

hw/m68k/next-cube.c

··· 860 860 { 861 861 M68kCPU *cpu; 862 862 CPUM68KState *env; 863 863 - MemoryRegion *ram = g_new(MemoryRegion, 1); 864 863 MemoryRegion *rom = g_new(MemoryRegion, 1); 865 864 MemoryRegion *mmiomem = g_new(MemoryRegion, 1); 866 865 MemoryRegion *scrmem = g_new(MemoryRegion, 1); ··· 893 892 memcpy(ns->rtc.ram, rtc_ram2, 32); 894 893 895 894 /* 64MB RAM starting at 0x04000000 */ 896 896 - memory_region_allocate_system_memory(ram, NULL, "next.ram", ram_size); 897 897 - memory_region_add_subregion(sysmem, 0x04000000, ram); 895 895 + memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 898 896 899 897 /* Framebuffer */ 900 898 dev = qdev_create(NULL, TYPE_NEXTFB); ··· 967 965 mc->desc = "NeXT Cube"; 968 966 mc->init = next_cube_init; 969 967 mc->default_ram_size = RAM_SIZE; 968 968 + mc->default_ram_id = "next.ram"; 970 969 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 971 970 } 972 971

+2 -4

hw/m68k/q800.c

··· 160 160 ram_addr_t initrd_base; 161 161 int32_t initrd_size; 162 162 MemoryRegion *rom; 163 163 - MemoryRegion *ram; 164 163 MemoryRegion *io; 165 164 const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1; 166 165 int i; ··· 194 193 qemu_register_reset(main_cpu_reset, cpu); 195 194 196 195 /* RAM */ 197 197 - ram = g_malloc(sizeof(*ram)); 198 198 - memory_region_init_ram(ram, NULL, "m68k_mac.ram", ram_size, &error_abort); 199 199 - memory_region_add_subregion(get_system_memory(), 0, ram); 196 196 + memory_region_add_subregion(get_system_memory(), 0, machine->ram); 200 197 201 198 /* 202 199 * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated ··· 443 440 mc->max_cpus = 1; 444 441 mc->is_default = 0; 445 442 mc->block_default_type = IF_SCSI; 443 443 + mc->default_ram_id = "m68k_mac.ram"; 446 444 } 447 445 448 446 static const TypeInfo q800_machine_typeinfo = {

+5 -6

hw/mips/boston.c

··· 427 427 DeviceState *dev; 428 428 BostonState *s; 429 429 Error *err = NULL; 430 430 - MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg; 430 430 + MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; 431 431 MemoryRegion *sys_mem = get_system_memory(); 432 432 XilinxPCIEHost *pcie2; 433 433 PCIDevice *ahci; ··· 473 473 memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err); 474 474 memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); 475 475 476 476 - ddr = g_new(MemoryRegion, 1); 477 477 - memory_region_allocate_system_memory(ddr, NULL, "boston.ddr", 478 478 - machine->ram_size); 479 479 - memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0); 476 476 + memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0); 480 477 481 478 ddr_low_alias = g_new(MemoryRegion, 1); 482 479 memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", 483 483 - ddr, 0, MIN(machine->ram_size, (256 * MiB))); 480 480 + machine->ram, 0, 481 481 + MIN(machine->ram_size, (256 * MiB))); 484 482 memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); 485 483 486 484 xilinx_pcie_init(sys_mem, 0, ··· 552 550 mc->init = boston_mach_init; 553 551 mc->block_default_type = IF_IDE; 554 552 mc->default_ram_size = 1 * GiB; 553 553 + mc->default_ram_id = "boston.ddr"; 555 554 mc->max_cpus = 16; 556 555 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); 557 556 }

+8 -7

hw/mips/mips_fulong2e.c

··· 294 294 const char *initrd_filename = machine->initrd_filename; 295 295 char *filename; 296 296 MemoryRegion *address_space_mem = get_system_memory(); 297 297 - MemoryRegion *ram = g_new(MemoryRegion, 1); 298 297 MemoryRegion *bios = g_new(MemoryRegion, 1); 299 299 - ram_addr_t ram_size = machine->ram_size; 300 298 long bios_size; 301 299 uint8_t *spd_data; 302 300 Error *err = NULL; ··· 315 313 qemu_register_reset(main_cpu_reset, cpu); 316 314 317 315 /* TODO: support more than 256M RAM as highmem */ 318 318 - ram_size = 256 * MiB; 316 316 + if (machine->ram_size != 256 * MiB) { 317 317 + error_report("Invalid RAM size, should be 256MB"); 318 318 + exit(EXIT_FAILURE); 319 319 + } 319 320 320 321 /* allocate RAM */ 321 321 - memory_region_allocate_system_memory(ram, NULL, "fulong2e.ram", ram_size); 322 322 memory_region_init_ram(bios, NULL, "fulong2e.bios", BIOS_SIZE, 323 323 &error_fatal); 324 324 memory_region_set_readonly(bios, true); 325 325 326 326 - memory_region_add_subregion(address_space_mem, 0, ram); 326 326 + memory_region_add_subregion(address_space_mem, 0, machine->ram); 327 327 memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); 328 328 329 329 /* ··· 332 332 */ 333 333 334 334 if (kernel_filename) { 335 335 - loaderparams.ram_size = ram_size; 335 335 + loaderparams.ram_size = machine->ram_size; 336 336 loaderparams.kernel_filename = kernel_filename; 337 337 loaderparams.kernel_cmdline = kernel_cmdline; 338 338 loaderparams.initrd_filename = initrd_filename; ··· 378 378 } 379 379 380 380 /* Populate SPD eeprom data */ 381 381 - spd_data = spd_data_generate(DDR, ram_size, &err); 381 381 + spd_data = spd_data_generate(DDR, machine->ram_size, &err); 382 382 if (err) { 383 383 warn_report_err(err); 384 384 } ··· 399 399 mc->block_default_type = IF_IDE; 400 400 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E"); 401 401 mc->default_ram_size = 256 * MiB; 402 402 + mc->default_ram_id = "fulong2e.ram"; 402 403 } 403 404 404 405 DEFINE_MACHINE("fulong2e", mips_fulong2e_machine_init)

+8 -4

hw/mips/mips_jazz.c

··· 159 159 ISABus *isa_bus; 160 160 ISADevice *pit; 161 161 DriveInfo *fds[MAX_FD]; 162 162 - MemoryRegion *ram = g_new(MemoryRegion, 1); 163 162 MemoryRegion *bios = g_new(MemoryRegion, 1); 164 163 MemoryRegion *bios2 = g_new(MemoryRegion, 1); 165 164 SysBusESPState *sysbus_esp; 166 165 ESPState *esp; 166 166 + 167 167 + if (machine->ram_size > 256 * MiB) { 168 168 + error_report("RAM size more than 256Mb is not supported"); 169 169 + exit(EXIT_FAILURE); 170 170 + } 167 171 168 172 /* init CPUs */ 169 173 cpu = MIPS_CPU(cpu_create(machine->cpu_type)); ··· 191 195 cc->do_transaction_failed = mips_jazz_do_transaction_failed; 192 196 193 197 /* allocate RAM */ 194 194 - memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", 195 195 - machine->ram_size); 196 196 - memory_region_add_subregion(address_space, 0, ram); 198 198 + memory_region_add_subregion(address_space, 0, machine->ram); 197 199 198 200 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, 199 201 &error_fatal); ··· 393 395 mc->init = mips_magnum_init; 394 396 mc->block_default_type = IF_SCSI; 395 397 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 398 398 + mc->default_ram_id = "mips_jazz.ram"; 396 399 } 397 400 398 401 static const TypeInfo mips_magnum_type = { ··· 409 412 mc->init = mips_pica61_init; 410 413 mc->block_default_type = IF_SCSI; 411 414 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); 415 415 + mc->default_ram_id = "mips_jazz.ram"; 412 416 } 413 417 414 418 static const TypeInfo mips_pica61_type = {

+4 -6

hw/mips/mips_malta.c

··· 1224 1224 char *filename; 1225 1225 PFlashCFI01 *fl; 1226 1226 MemoryRegion *system_memory = get_system_memory(); 1227 1227 - MemoryRegion *ram_high = g_new(MemoryRegion, 1); 1228 1227 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); 1229 1228 MemoryRegion *ram_low_postio; 1230 1229 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); ··· 1262 1261 } 1263 1262 1264 1263 /* register RAM at high address where it is undisturbed by IO */ 1265 1265 - memory_region_allocate_system_memory(ram_high, NULL, "mips_malta.ram", 1266 1266 - ram_size); 1267 1267 - memory_region_add_subregion(system_memory, 0x80000000, ram_high); 1264 1264 + memory_region_add_subregion(system_memory, 0x80000000, machine->ram); 1268 1265 1269 1266 /* alias for pre IO hole access */ 1270 1267 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", 1271 1271 - ram_high, 0, MIN(ram_size, 256 * MiB)); 1268 1268 + machine->ram, 0, MIN(ram_size, 256 * MiB)); 1272 1269 memory_region_add_subregion(system_memory, 0, ram_low_preio); 1273 1270 1274 1271 /* alias for post IO hole access, if there is enough RAM */ ··· 1276 1273 ram_low_postio = g_new(MemoryRegion, 1); 1277 1274 memory_region_init_alias(ram_low_postio, NULL, 1278 1275 "mips_malta_low_postio.ram", 1279 1279 - ram_high, 512 * MiB, 1276 1276 + machine->ram, 512 * MiB, 1280 1277 ram_size - 512 * MiB); 1281 1278 memory_region_add_subregion(system_memory, 512 * MiB, 1282 1279 ram_low_postio); ··· 1448 1445 #else 1449 1446 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); 1450 1447 #endif 1448 1448 + mc->default_ram_id = "mips_malta.ram"; 1451 1449 } 1452 1450 1453 1451 DEFINE_MACHINE("malta", mips_malta_machine_init)

+3 -6

hw/mips/mips_mipssim.c

··· 143 143 static void 144 144 mips_mipssim_init(MachineState *machine) 145 145 { 146 146 - ram_addr_t ram_size = machine->ram_size; 147 146 const char *kernel_filename = machine->kernel_filename; 148 147 const char *kernel_cmdline = machine->kernel_cmdline; 149 148 const char *initrd_filename = machine->initrd_filename; 150 149 char *filename; 151 150 MemoryRegion *address_space_mem = get_system_memory(); 152 151 MemoryRegion *isa = g_new(MemoryRegion, 1); 153 153 - MemoryRegion *ram = g_new(MemoryRegion, 1); 154 152 MemoryRegion *bios = g_new(MemoryRegion, 1); 155 153 MIPSCPU *cpu; 156 154 CPUMIPSState *env; ··· 167 165 qemu_register_reset(main_cpu_reset, reset_info); 168 166 169 167 /* Allocate RAM. */ 170 170 - memory_region_allocate_system_memory(ram, NULL, "mips_mipssim.ram", 171 171 - ram_size); 172 168 memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE, 173 169 &error_fatal); 174 170 memory_region_set_readonly(bios, true); 175 171 176 176 - memory_region_add_subregion(address_space_mem, 0, ram); 172 172 + memory_region_add_subregion(address_space_mem, 0, machine->ram); 177 173 178 174 /* Map the BIOS / boot exception handler. */ 179 175 memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); ··· 200 196 } 201 197 202 198 if (kernel_filename) { 203 203 - loaderparams.ram_size = ram_size; 199 199 + loaderparams.ram_size = machine->ram_size; 204 200 loaderparams.kernel_filename = kernel_filename; 205 201 loaderparams.kernel_cmdline = kernel_cmdline; 206 202 loaderparams.initrd_filename = initrd_filename; ··· 245 241 #else 246 242 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); 247 243 #endif 244 244 + mc->default_ram_id = "mips_mipssim.ram"; 248 245 } 249 246 250 247 DEFINE_MACHINE("mipssim", mips_mipssim_machine_init)

+4 -8

hw/mips/mips_r4k.c

··· 171 171 static 172 172 void mips_r4k_init(MachineState *machine) 173 173 { 174 174 - ram_addr_t ram_size = machine->ram_size; 175 174 const char *kernel_filename = machine->kernel_filename; 176 175 const char *kernel_cmdline = machine->kernel_cmdline; 177 176 const char *initrd_filename = machine->initrd_filename; 178 177 char *filename; 179 178 MemoryRegion *address_space_mem = get_system_memory(); 180 180 - MemoryRegion *ram = g_new(MemoryRegion, 1); 181 179 MemoryRegion *bios; 182 180 MemoryRegion *iomem = g_new(MemoryRegion, 1); 183 181 MemoryRegion *isa_io = g_new(MemoryRegion, 1); ··· 203 201 qemu_register_reset(main_cpu_reset, reset_info); 204 202 205 203 /* allocate RAM */ 206 206 - if (ram_size > 256 * MiB) { 204 204 + if (machine->ram_size > 256 * MiB) { 207 205 error_report("Too much memory for this machine: %" PRId64 "MB," 208 206 " maximum 256MB", ram_size / MiB); 209 207 exit(1); 210 208 } 211 211 - memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_size); 212 212 - 213 213 - memory_region_add_subregion(address_space_mem, 0, ram); 209 209 + memory_region_add_subregion(address_space_mem, 0, machine->ram); 214 210 215 211 memory_region_init_io(iomem, NULL, &mips_qemu_ops, 216 212 NULL, "mips-qemu", 0x10000); ··· 261 257 g_free(filename); 262 258 263 259 if (kernel_filename) { 264 264 - loaderparams.ram_size = ram_size; 260 260 + loaderparams.ram_size = machine->ram_size; 265 261 loaderparams.kernel_filename = kernel_filename; 266 262 loaderparams.kernel_cmdline = kernel_cmdline; 267 263 loaderparams.initrd_filename = initrd_filename; ··· 316 312 #else 317 313 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); 318 314 #endif 319 319 - 315 315 + mc->default_ram_id = "mips_r4k.ram"; 320 316 } 321 317 322 318 DEFINE_MACHINE("mips", mips_machine_init)

+64 -19

hw/misc/aspeed_sdmc.c

··· 17 17 #include "migration/vmstate.h" 18 18 #include "qapi/error.h" 19 19 #include "trace.h" 20 20 + #include "qemu/units.h" 21 21 + #include "qemu/cutils.h" 22 22 + #include "qapi/visitor.h" 20 23 21 24 /* Protection Key Register */ 22 25 #define R_PROT (0x00 / 4) ··· 160 163 case 512: 161 164 return ASPEED_SDMC_DRAM_512MB; 162 165 default: 166 166 + g_assert_not_reached(); 163 167 break; 164 168 } 165 165 - 166 166 - /* use a common default */ 167 167 - warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M", 168 168 - s->ram_size); 169 169 - s->ram_size = 256 << 20; 170 170 - return ASPEED_SDMC_DRAM_256MB; 171 169 } 172 170 173 171 static int ast2500_rambits(AspeedSDMCState *s) ··· 182 180 case 1024: 183 181 return ASPEED_SDMC_AST2500_1024MB; 184 182 default: 183 183 + g_assert_not_reached(); 185 184 break; 186 185 } 187 187 - 188 188 - /* use a common default */ 189 189 - warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M", 190 190 - s->ram_size); 191 191 - s->ram_size = 512 << 20; 192 192 - return ASPEED_SDMC_AST2500_512MB; 193 186 } 194 187 195 188 static int ast2600_rambits(AspeedSDMCState *s) ··· 204 197 case 2048: 205 198 return ASPEED_SDMC_AST2600_2048MB; 206 199 default: 200 200 + g_assert_not_reached(); 207 201 break; 208 202 } 209 209 - 210 210 - /* use a common default */ 211 211 - warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 1024M", 212 212 - s->ram_size); 213 213 - s->ram_size = 1024 << 20; 214 214 - return ASPEED_SDMC_AST2600_1024MB; 215 203 } 216 204 217 205 static void aspeed_sdmc_reset(DeviceState *dev) ··· 225 213 s->regs[R_CONF] = asc->compute_conf(s, 0); 226 214 } 227 215 216 216 + static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name, 217 217 + void *opaque, Error **errp) 218 218 + { 219 219 + AspeedSDMCState *s = ASPEED_SDMC(obj); 220 220 + int64_t value = s->ram_size; 221 221 + 222 222 + visit_type_int(v, name, &value, errp); 223 223 + } 224 224 + 225 225 + static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name, 226 226 + void *opaque, Error **errp) 227 227 + { 228 228 + int i; 229 229 + char *sz; 230 230 + int64_t value; 231 231 + Error *local_err = NULL; 232 232 + AspeedSDMCState *s = ASPEED_SDMC(obj); 233 233 + AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); 234 234 + 235 235 + visit_type_int(v, name, &value, &local_err); 236 236 + if (local_err) { 237 237 + error_propagate(errp, local_err); 238 238 + return; 239 239 + } 240 240 + 241 241 + for (i = 0; asc->valid_ram_sizes[i]; i++) { 242 242 + if (value == asc->valid_ram_sizes[i]) { 243 243 + s->ram_size = value; 244 244 + return; 245 245 + } 246 246 + } 247 247 + 248 248 + sz = size_to_str(value); 249 249 + error_setg(&local_err, "Invalid RAM size %s", sz); 250 250 + g_free(sz); 251 251 + error_propagate(errp, local_err); 252 252 + } 253 253 + 254 254 + static void aspeed_sdmc_initfn(Object *obj) 255 255 + { 256 256 + object_property_add(obj, "ram-size", "int", 257 257 + aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size, 258 258 + NULL, NULL, NULL); 259 259 + } 260 260 + 228 261 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) 229 262 { 230 263 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); ··· 249 282 }; 250 283 251 284 static Property aspeed_sdmc_properties[] = { 252 252 - DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0), 253 285 DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), 254 286 DEFINE_PROP_END_OF_LIST(), 255 287 }; ··· 268 300 .name = TYPE_ASPEED_SDMC, 269 301 .parent = TYPE_SYS_BUS_DEVICE, 270 302 .instance_size = sizeof(AspeedSDMCState), 303 303 + .instance_init = aspeed_sdmc_initfn, 271 304 .class_init = aspeed_sdmc_class_init, 272 305 .class_size = sizeof(AspeedSDMCClass), 273 306 .abstract = true, ··· 298 331 s->regs[reg] = data; 299 332 } 300 333 334 334 + static const uint64_t 335 335 + aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0}; 336 336 + 301 337 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) 302 338 { 303 339 DeviceClass *dc = DEVICE_CLASS(klass); ··· 307 343 asc->max_ram_size = 512 << 20; 308 344 asc->compute_conf = aspeed_2400_sdmc_compute_conf; 309 345 asc->write = aspeed_2400_sdmc_write; 346 346 + asc->valid_ram_sizes = aspeed_2400_ram_sizes; 310 347 } 311 348 312 349 static const TypeInfo aspeed_2400_sdmc_info = { ··· 350 387 351 388 s->regs[reg] = data; 352 389 } 390 390 + 391 391 + static const uint64_t 392 392 + aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0}; 353 393 354 394 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) 355 395 { ··· 360 400 asc->max_ram_size = 1024 << 20; 361 401 asc->compute_conf = aspeed_2500_sdmc_compute_conf; 362 402 asc->write = aspeed_2500_sdmc_write; 403 403 + asc->valid_ram_sizes = aspeed_2500_ram_sizes; 363 404 } 364 405 365 406 static const TypeInfo aspeed_2500_sdmc_info = { ··· 404 445 s->regs[reg] = data; 405 446 } 406 447 448 448 + static const uint64_t 449 449 + aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0}; 450 450 + 407 451 static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) 408 452 { 409 453 DeviceClass *dc = DEVICE_CLASS(klass); ··· 413 457 asc->max_ram_size = 2048 << 20; 414 458 asc->compute_conf = aspeed_2600_sdmc_compute_conf; 415 459 asc->write = aspeed_2600_sdmc_write; 460 460 + asc->valid_ram_sizes = aspeed_2600_ram_sizes; 416 461 } 417 462 418 463 static const TypeInfo aspeed_2600_sdmc_info = {

+8 -9

hw/ppc/e500.c

··· 832 832 void ppce500_init(MachineState *machine) 833 833 { 834 834 MemoryRegion *address_space_mem = get_system_memory(); 835 835 - MemoryRegion *ram = g_new(MemoryRegion, 1); 836 835 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 837 836 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 838 837 PCIBus *pci_bus; ··· 907 906 908 907 env = firstenv; 909 908 910 910 - /* Fixup Memory size on a alignment boundary */ 911 911 - ram_size &= ~(RAM_SIZES_ALIGN - 1); 912 912 - machine->ram_size = ram_size; 909 909 + if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { 910 910 + error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); 911 911 + exit(EXIT_FAILURE); 912 912 + } 913 913 914 914 /* Register Memory */ 915 915 - memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 916 916 - memory_region_add_subregion(address_space_mem, 0, ram); 915 915 + memory_region_add_subregion(address_space_mem, 0, machine->ram); 917 916 918 917 dev = qdev_create(NULL, "e500-ccsr"); 919 918 object_property_add_child(qdev_get_machine(), "e500-ccsr", ··· 1084 1083 kernel_base = cur_base; 1085 1084 kernel_size = load_image_targphys(machine->kernel_filename, 1086 1085 cur_base, 1087 1087 - ram_size - cur_base); 1086 1086 + machine->ram_size - cur_base); 1088 1087 if (kernel_size < 0) { 1089 1088 error_report("could not load kernel '%s'", 1090 1089 machine->kernel_filename); ··· 1098 1097 if (machine->initrd_filename) { 1099 1098 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1100 1099 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1101 1101 - ram_size - initrd_base); 1100 1100 + machine->ram_size - initrd_base); 1102 1101 1103 1102 if (initrd_size < 0) { 1104 1103 error_report("could not load initial ram disk '%s'", ··· 1116 1115 * ensures enough space between kernel and initrd. 1117 1116 */ 1118 1117 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1119 1119 - if (dt_base + DTB_MAX_SIZE > ram_size) { 1118 1118 + if (dt_base + DTB_MAX_SIZE > machine->ram_size) { 1120 1119 error_report("not enough memory for device tree"); 1121 1120 exit(1); 1122 1121 }

+1

hw/ppc/e500plat.c

··· 97 97 mc->init = e500plat_init; 98 98 mc->max_cpus = 32; 99 99 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30"); 100 100 + mc->default_ram_id = "mpc8544ds.ram"; 100 101 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ETSEC_COMMON); 101 102 } 102 103

+3 -3

hw/ppc/mac_newworld.c

··· 118 118 char *filename; 119 119 IrqLines *openpic_irqs; 120 120 int linux_boot, i, j, k; 121 121 - MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 121 121 + MemoryRegion *bios = g_new(MemoryRegion, 1); 122 122 hwaddr kernel_base, initrd_base, cmdline_base = 0; 123 123 long kernel_size, initrd_size; 124 124 UNINHostState *uninorth_pci; ··· 152 152 } 153 153 154 154 /* allocate RAM */ 155 155 - memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 156 156 - memory_region_add_subregion(get_system_memory(), 0, ram); 155 155 + memory_region_add_subregion(get_system_memory(), 0, machine->ram); 157 156 158 157 /* allocate and load BIOS */ 159 158 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, ··· 586 585 #else 587 586 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 588 587 #endif 588 588 + mc->default_ram_id = "ppc_core99.ram"; 589 589 mc->ignore_boot_device_suffixes = true; 590 590 fwc->get_dev_path = core99_fw_dev_path; 591 591 }

+2 -4

hw/ppc/mac_oldworld.c

··· 91 91 CPUPPCState *env = NULL; 92 92 char *filename; 93 93 int linux_boot, i; 94 94 - MemoryRegion *ram = g_new(MemoryRegion, 1); 95 94 MemoryRegion *bios = g_new(MemoryRegion, 1); 96 95 uint32_t kernel_base, initrd_base, cmdline_base = 0; 97 96 int32_t kernel_size, initrd_size; ··· 127 126 exit(1); 128 127 } 129 128 130 130 - memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram", 131 131 - ram_size); 132 132 - memory_region_add_subregion(sysmem, 0, ram); 129 129 + memory_region_add_subregion(sysmem, 0, machine->ram); 133 130 134 131 /* allocate and load BIOS */ 135 132 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, ··· 446 443 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 447 444 mc->default_display = "std"; 448 445 mc->ignore_boot_device_suffixes = true; 446 446 + mc->default_ram_id = "ppc_heathrow.ram"; 449 447 fwc->get_dev_path = heathrow_fw_dev_path; 450 448 } 451 449

+1

hw/ppc/mpc8544ds.c

··· 55 55 mc->init = mpc8544ds_init; 56 56 mc->max_cpus = 15; 57 57 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30"); 58 58 + mc->default_ram_id = "mpc8544ds.ram"; 58 59 } 59 60 60 61 #define TYPE_MPC8544DS_MACHINE MACHINE_TYPE_NAME("mpc8544ds")

+2 -6

hw/ppc/pnv.c

··· 692 692 { 693 693 PnvMachineState *pnv = PNV_MACHINE(machine); 694 694 MachineClass *mc = MACHINE_GET_CLASS(machine); 695 695 - MemoryRegion *ram; 696 695 char *fw_filename; 697 696 long fw_size; 698 697 int i; ··· 704 703 if (machine->ram_size < (1 * GiB)) { 705 704 warn_report("skiboot may not work with < 1GB of RAM"); 706 705 } 707 707 - 708 708 - ram = g_new(MemoryRegion, 1); 709 709 - memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 710 710 - machine->ram_size); 711 711 - memory_region_add_subregion(get_system_memory(), 0, ram); 706 706 + memory_region_add_subregion(get_system_memory(), 0, machine->ram); 712 707 713 708 /* 714 709 * Create our simple PNOR device ··· 1978 1973 * enough to fit the maximum initrd size at it's load address 1979 1974 */ 1980 1975 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1976 1976 + mc->default_ram_id = "pnv.ram"; 1981 1977 ispc->print_info = pnv_pic_print_info; 1982 1978 1983 1979 object_class_property_add_bool(oc, "hb-mode",

+30 -18

hw/ppc/ppc405_boards.c

··· 40 40 #include "qemu/error-report.h" 41 41 #include "hw/loader.h" 42 42 #include "exec/address-spaces.h" 43 43 + #include "qemu/cutils.h" 43 44 44 45 #define BIOS_FILENAME "ppc405_rom.bin" 45 46 #define BIOS_SIZE (2 * MiB) ··· 137 138 138 139 static void ref405ep_init(MachineState *machine) 139 140 { 140 140 - ram_addr_t ram_size = machine->ram_size; 141 141 + MachineClass *mc = MACHINE_GET_CLASS(machine); 141 142 const char *kernel_filename = machine->kernel_filename; 142 143 const char *kernel_cmdline = machine->kernel_cmdline; 143 144 const char *initrd_filename = machine->initrd_filename; ··· 161 162 DriveInfo *dinfo; 162 163 MemoryRegion *sysmem = get_system_memory(); 163 164 165 165 + if (machine->ram_size != mc->default_ram_size) { 166 166 + char *sz = size_to_str(mc->default_ram_size); 167 167 + error_report("Invalid RAM size, should be %s", sz); 168 168 + g_free(sz); 169 169 + exit(EXIT_FAILURE); 170 170 + } 171 171 + 164 172 /* XXX: fix this */ 165 165 - memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", 166 166 - 0x08000000); 173 173 + memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias", 174 174 + machine->ram, 0, machine->ram_size); 167 175 ram_bases[0] = 0; 168 168 - ram_sizes[0] = 0x08000000; 176 176 + ram_sizes[0] = machine->ram_size; 169 177 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); 170 178 ram_bases[1] = 0x00000000; 171 179 ram_sizes[1] = 0x00000000; 172 172 - ram_size = 128 * MiB; 173 180 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 174 181 33333333, &pic, kernel_filename == NULL ? 0 : 1); 175 182 /* allocate SRAM */ ··· 227 234 if (linux_boot) { 228 235 memset(&bd, 0, sizeof(bd)); 229 236 bd.bi_memstart = 0x00000000; 230 230 - bd.bi_memsize = ram_size; 237 237 + bd.bi_memsize = machine->ram_size; 231 238 bd.bi_flashstart = -bios_size; 232 239 bd.bi_flashsize = -bios_size; 233 240 bd.bi_flashoffset = 0; ··· 255 262 kernel_base = KERNEL_LOAD_ADDR; 256 263 /* now we can load the kernel */ 257 264 kernel_size = load_image_targphys(kernel_filename, kernel_base, 258 258 - ram_size - kernel_base); 265 265 + machine->ram_size - kernel_base); 259 266 if (kernel_size < 0) { 260 267 error_report("could not load kernel '%s'", kernel_filename); 261 268 exit(1); ··· 266 273 if (initrd_filename) { 267 274 initrd_base = INITRD_LOAD_ADDR; 268 275 initrd_size = load_image_targphys(initrd_filename, initrd_base, 269 269 - ram_size - initrd_base); 276 276 + machine->ram_size - initrd_base); 270 277 if (initrd_size < 0) { 271 278 error_report("could not load initial ram disk '%s'", 272 279 initrd_filename); ··· 304 311 305 312 mc->desc = "ref405ep"; 306 313 mc->init = ref405ep_init; 314 314 + mc->default_ram_size = 0x08000000; 315 315 + mc->default_ram_id = "ef405ep.ram"; 307 316 } 308 317 309 318 static const TypeInfo ref405ep_type = { ··· 408 417 409 418 static void taihu_405ep_init(MachineState *machine) 410 419 { 411 411 - ram_addr_t ram_size = machine->ram_size; 420 420 + MachineClass *mc = MACHINE_GET_CLASS(machine); 412 421 const char *kernel_filename = machine->kernel_filename; 413 422 const char *initrd_filename = machine->initrd_filename; 414 423 char *filename; ··· 416 425 MemoryRegion *sysmem = get_system_memory(); 417 426 MemoryRegion *bios; 418 427 MemoryRegion *ram_memories = g_new(MemoryRegion, 2); 419 419 - MemoryRegion *ram = g_malloc0(sizeof(*ram)); 420 428 hwaddr ram_bases[2], ram_sizes[2]; 421 429 long bios_size; 422 430 target_ulong kernel_base, initrd_base; ··· 425 433 int fl_idx; 426 434 DriveInfo *dinfo; 427 435 428 428 - /* RAM is soldered to the board so the size cannot be changed */ 429 429 - ram_size = 0x08000000; 430 430 - memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", 431 431 - ram_size); 436 436 + if (machine->ram_size != mc->default_ram_size) { 437 437 + char *sz = size_to_str(mc->default_ram_size); 438 438 + error_report("Invalid RAM size, should be %s", sz); 439 439 + g_free(sz); 440 440 + exit(EXIT_FAILURE); 441 441 + } 432 442 433 443 ram_bases[0] = 0; 434 444 ram_sizes[0] = 0x04000000; 435 445 memory_region_init_alias(&ram_memories[0], NULL, 436 436 - "taihu_405ep.ram-0", ram, ram_bases[0], 446 446 + "taihu_405ep.ram-0", machine->ram, ram_bases[0], 437 447 ram_sizes[0]); 438 448 ram_bases[1] = 0x04000000; 439 449 ram_sizes[1] = 0x04000000; 440 450 memory_region_init_alias(&ram_memories[1], NULL, 441 441 - "taihu_405ep.ram-1", ram, ram_bases[1], 451 451 + "taihu_405ep.ram-1", machine->ram, ram_bases[1], 442 452 ram_sizes[1]); 443 453 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 444 454 33333333, &pic, kernel_filename == NULL ? 0 : 1); ··· 500 510 kernel_base = KERNEL_LOAD_ADDR; 501 511 /* now we can load the kernel */ 502 512 kernel_size = load_image_targphys(kernel_filename, kernel_base, 503 503 - ram_size - kernel_base); 513 513 + machine->ram_size - kernel_base); 504 514 if (kernel_size < 0) { 505 515 error_report("could not load kernel '%s'", kernel_filename); 506 516 exit(1); ··· 509 519 if (initrd_filename) { 510 520 initrd_base = INITRD_LOAD_ADDR; 511 521 initrd_size = load_image_targphys(initrd_filename, initrd_base, 512 512 - ram_size - initrd_base); 522 522 + machine->ram_size - initrd_base); 513 523 if (initrd_size < 0) { 514 524 error_report("could not load initial ram disk '%s'", 515 525 initrd_filename); ··· 533 543 534 544 mc->desc = "taihu"; 535 545 mc->init = taihu_405ep_init; 546 546 + mc->default_ram_size = 0x08000000; 547 547 + mc->default_ram_id = "taihu_405ep.ram"; 536 548 } 537 549 538 550 static const TypeInfo taihu_type = {

+5 -7

hw/ppc/ppc440_bamboo.c

··· 158 158 159 159 static void bamboo_init(MachineState *machine) 160 160 { 161 161 - ram_addr_t ram_size = machine->ram_size; 162 161 const char *kernel_filename = machine->kernel_filename; 163 162 const char *kernel_cmdline = machine->kernel_cmdline; 164 163 const char *initrd_filename = machine->initrd_filename; ··· 203 202 /* SDRAM controller */ 204 203 memset(ram_bases, 0, sizeof(ram_bases)); 205 204 memset(ram_sizes, 0, sizeof(ram_sizes)); 206 206 - ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS, 207 207 - ram_memories, 208 208 - ram_bases, ram_sizes, 209 209 - ppc440ep_sdram_bank_sizes); 205 205 + ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, 206 206 + ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); 210 207 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ 211 208 ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, 212 209 ram_bases, ram_sizes, 1); ··· 268 265 /* Load initrd. */ 269 266 if (initrd_filename) { 270 267 initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, 271 271 - ram_size - RAMDISK_ADDR); 268 268 + machine->ram_size - RAMDISK_ADDR); 272 269 273 270 if (initrd_size < 0) { 274 271 error_report("could not load ram disk '%s' at %x", ··· 279 276 280 277 /* If we're loading a kernel directly, we must load the device tree too. */ 281 278 if (kernel_filename) { 282 282 - if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR, 279 279 + if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, 283 280 initrd_size, kernel_cmdline) < 0) { 284 281 error_report("couldn't load device tree"); 285 282 exit(1); ··· 292 289 mc->desc = "bamboo"; 293 290 mc->init = bamboo_init; 294 291 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); 292 292 + mc->default_ram_id = "ppc4xx.sdram"; 295 293 } 296 294 297 295 DEFINE_MACHINE("bamboo", bamboo_machine_init)

+33 -34

hw/ppc/ppc4xx_devs.c

··· 666 666 sdram_map_bcr(sdram); 667 667 } 668 668 669 669 - /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory. 669 669 + /* 670 670 + * Split RAM between SDRAM banks. 670 671 * 671 671 - * sdram_bank_sizes[] must be 0-terminated. 672 672 + * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1] 673 673 + * and must be 0-terminated. 672 674 * 673 675 * The 4xx SDRAM controller supports a small number of banks, and each bank 674 676 * must be one of a small set of sizes. The number of banks and the supported 675 675 - * sizes varies by SoC. */ 676 676 - ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, 677 677 - MemoryRegion ram_memories[], 678 678 - hwaddr ram_bases[], 679 679 - hwaddr ram_sizes[], 680 680 - const ram_addr_t sdram_bank_sizes[]) 677 677 + * sizes varies by SoC. 678 678 + */ 679 679 + void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 680 680 + MemoryRegion ram_memories[], 681 681 + hwaddr ram_bases[], hwaddr ram_sizes[], 682 682 + const ram_addr_t sdram_bank_sizes[]) 681 683 { 682 682 - MemoryRegion *ram = g_malloc0(sizeof(*ram)); 683 683 - ram_addr_t size_left = ram_size; 684 684 + ram_addr_t size_left = memory_region_size(ram); 684 685 ram_addr_t base = 0; 685 686 ram_addr_t bank_size; 686 687 int i; ··· 690 691 for (j = 0; sdram_bank_sizes[j] != 0; j++) { 691 692 bank_size = sdram_bank_sizes[j]; 692 693 if (bank_size <= size_left) { 694 694 + char name[32]; 695 695 + 696 696 + ram_bases[i] = base; 697 697 + ram_sizes[i] = bank_size; 698 698 + base += bank_size; 693 699 size_left -= bank_size; 700 700 + snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); 701 701 + memory_region_init_alias(&ram_memories[i], NULL, name, ram, 702 702 + ram_bases[i], ram_sizes[i]); 703 703 + break; 694 704 } 695 705 } 696 706 if (!size_left) { ··· 699 709 } 700 710 } 701 711 702 702 - ram_size -= size_left; 703 712 if (size_left) { 704 704 - error_report("Truncating memory to %" PRId64 " MiB to fit SDRAM" 705 705 - " controller limits", ram_size / MiB); 706 706 - } 713 713 + ram_addr_t used_size = memory_region_size(ram) - size_left; 714 714 + GString *s = g_string_new(NULL); 707 715 708 708 - memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size); 716 716 + for (i = 0; sdram_bank_sizes[i]; i++) { 717 717 + g_string_append_printf(s, "%" PRIi64 "%s", 718 718 + sdram_bank_sizes[i] / MiB, 719 719 + sdram_bank_sizes[i + 1] ? " ," : ""); 720 720 + } 721 721 + error_report("Max %d banks of %s MB DIMM/bank supported", 722 722 + nr_banks, s->str); 723 723 + error_report("Possible valid RAM size: %" PRIi64, 724 724 + used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); 709 725 710 710 - size_left = ram_size; 711 711 - for (i = 0; i < nr_banks && size_left; i++) { 712 712 - for (j = 0; sdram_bank_sizes[j] != 0; j++) { 713 713 - bank_size = sdram_bank_sizes[j]; 714 714 - 715 715 - if (bank_size <= size_left) { 716 716 - char name[32]; 717 717 - snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); 718 718 - memory_region_init_alias(&ram_memories[i], NULL, name, ram, 719 719 - base, bank_size); 720 720 - ram_bases[i] = base; 721 721 - ram_sizes[i] = bank_size; 722 722 - base += bank_size; 723 723 - size_left -= bank_size; 724 724 - break; 725 725 - } 726 726 - } 726 726 + g_string_free(s, true); 727 727 + exit(EXIT_FAILURE); 727 728 } 728 728 - 729 729 - return ram_size; 730 729 } 731 730 732 731 /*****************************************************************************/

+3 -3

hw/ppc/sam460ex.c

··· 324 324 /* SDRAM controller */ 325 325 /* put all RAM on first bank because board has one slot 326 326 * and firmware only checks that */ 327 327 - machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1, 328 328 - ram_memories, ram_bases, ram_sizes, 329 329 - ppc460ex_sdram_bank_sizes); 327 327 + ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes, 328 328 + ppc460ex_sdram_bank_sizes); 330 329 331 330 /* FIXME: does 460EX have ECC interrupts? */ 332 331 ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories, ··· 485 484 mc->init = sam460ex_init; 486 485 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); 487 486 mc->default_ram_size = 512 * MiB; 487 487 + mc->default_ram_id = "ppc4xx.sdram"; 488 488 } 489 489 490 490 DEFINE_MACHINE("sam460ex", sam460ex_machine_init)

+3 -5

hw/ppc/spapr.c

··· 2652 2652 PCIHostState *phb; 2653 2653 int i; 2654 2654 MemoryRegion *sysmem = get_system_memory(); 2655 2655 - MemoryRegion *ram = g_new(MemoryRegion, 1); 2656 2655 hwaddr node0_size = spapr_node0_size(machine); 2657 2656 long load_limit, fw_size; 2658 2657 char *filename; ··· 2831 2830 kvmppc_enable_h_page_init(); 2832 2831 } 2833 2832 2834 2834 - /* allocate RAM */ 2835 2835 - memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2836 2836 - machine->ram_size); 2837 2837 - memory_region_add_subregion(sysmem, 0, ram); 2833 2833 + /* map RAM */ 2834 2834 + memory_region_add_subregion(sysmem, 0, machine->ram); 2838 2835 2839 2836 /* always allocate the device memory information */ 2840 2837 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); ··· 4473 4470 mc->no_parallel = 1; 4474 4471 mc->default_boot_order = ""; 4475 4472 mc->default_ram_size = 512 * MiB; 4473 4473 + mc->default_ram_id = "ppc_spapr.ram"; 4476 4474 mc->default_display = "std"; 4477 4475 mc->kvm_type = spapr_kvm_type; 4478 4476 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);

+5 -7

hw/ppc/virtex_ml507.c

··· 194 194 195 195 static void virtex_init(MachineState *machine) 196 196 { 197 197 - ram_addr_t ram_size = machine->ram_size; 198 197 const char *kernel_filename = machine->kernel_filename; 199 198 const char *kernel_cmdline = machine->kernel_cmdline; 200 199 hwaddr initrd_base = 0; ··· 205 204 CPUPPCState *env; 206 205 hwaddr ram_base = 0; 207 206 DriveInfo *dinfo; 208 208 - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 209 207 qemu_irq irq[32], *cpu_irq; 210 208 int kernel_size; 211 209 int i; ··· 222 220 223 221 qemu_register_reset(main_cpu_reset, cpu); 224 222 225 225 - memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size); 226 226 - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); 223 223 + memory_region_add_subregion(address_space_mem, ram_base, machine->ram); 227 224 228 225 dinfo = drive_get(IF_PFLASH, 0, 0); 229 226 pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE, ··· 266 263 /* If we failed loading ELF's try a raw image. */ 267 264 kernel_size = load_image_targphys(kernel_filename, 268 265 boot_offset, 269 269 - ram_size); 266 266 + machine->ram_size); 270 267 boot_info.bootstrap_pc = boot_offset; 271 268 high = boot_info.bootstrap_pc + kernel_size + 8192; 272 269 } ··· 277 274 if (machine->initrd_filename) { 278 275 initrd_base = high = ROUND_UP(high, 4); 279 276 initrd_size = load_image_targphys(machine->initrd_filename, 280 280 - high, ram_size - high); 277 277 + high, machine->ram_size - high); 281 278 282 279 if (initrd_size < 0) { 283 280 error_report("couldn't load ram disk '%s'", ··· 291 288 boot_info.fdt = high + (8192 * 2); 292 289 boot_info.fdt &= ~8191; 293 290 294 294 - xilinx_load_device_tree(boot_info.fdt, ram_size, 291 291 + xilinx_load_device_tree(boot_info.fdt, machine->ram_size, 295 292 initrd_base, initrd_size, 296 293 kernel_cmdline); 297 294 } ··· 303 300 mc->desc = "Xilinx Virtex ML507 reference design"; 304 301 mc->init = virtex_init; 305 302 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx"); 303 303 + mc->default_ram_id = "ram"; 306 304 } 307 305 308 306 DEFINE_MACHINE("virtex-ml507", virtex_machine_init)

+3 -4

hw/s390x/s390-virtio-ccw.c

··· 154 154 virtio_ccw_hcall_early_printk); 155 155 } 156 156 157 157 - static void s390_memory_init(ram_addr_t mem_size) 157 157 + static void s390_memory_init(MemoryRegion *ram) 158 158 { 159 159 MemoryRegion *sysmem = get_system_memory(); 160 160 - MemoryRegion *ram = g_new(MemoryRegion, 1); 161 160 Error *local_err = NULL; 162 161 163 162 /* allocate RAM for core */ 164 164 - memory_region_allocate_system_memory(ram, NULL, "s390.ram", mem_size); 165 163 memory_region_add_subregion(sysmem, 0, ram); 166 164 167 165 /* ··· 245 243 246 244 s390_sclp_init(); 247 245 /* init memory + setup max page size. Required for the CPU model */ 248 248 - s390_memory_init(machine->ram_size); 246 246 + s390_memory_init(machine->ram); 249 247 250 248 /* init CPUs (incl. CPU model) early so s390_has_feature() works */ 251 249 s390_init_cpus(machine); ··· 471 469 hc->plug = s390_machine_device_plug; 472 470 hc->unplug_request = s390_machine_device_unplug_request; 473 471 nc->nmi_monitor_handler = s390_nmi; 472 472 + mc->default_ram_id = "s390.ram"; 474 473 } 475 474 476 475 static inline bool machine_get_aes_key_wrap(Object *obj, Error **errp)

+3 -3

hw/sparc/leon3.c

··· 189 189 SPARCCPU *cpu; 190 190 CPUSPARCState *env; 191 191 MemoryRegion *address_space_mem = get_system_memory(); 192 192 - MemoryRegion *ram = g_new(MemoryRegion, 1); 193 192 MemoryRegion *prom = g_new(MemoryRegion, 1); 194 193 int ret; 195 194 char *filename; ··· 251 250 exit(1); 252 251 } 253 252 254 254 - memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size); 255 255 - memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram); 253 253 + memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, 254 254 + machine->ram); 256 255 257 256 /* Allocate BIOS */ 258 257 prom_size = 8 * MiB; ··· 358 357 mc->desc = "Leon-3 generic"; 359 358 mc->init = leon3_generic_hw_init; 360 359 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3"); 360 360 + mc->default_ram_id = "leon3.ram"; 361 361 } 362 362 363 363 DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)

+37 -37

hw/sparc/sun4m.c

··· 777 777 778 778 typedef struct RamDevice { 779 779 SysBusDevice parent_obj; 780 780 - 781 781 - MemoryRegion ram; 782 782 - uint64_t size; 780 780 + HostMemoryBackend *memdev; 783 781 } RamDevice; 784 782 785 783 /* System RAM */ 786 784 static void ram_realize(DeviceState *dev, Error **errp) 787 785 { 788 786 RamDevice *d = SUN4M_RAM(dev); 789 789 - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 787 787 + MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); 790 788 791 791 - memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", 792 792 - d->size); 793 793 - sysbus_init_mmio(sbd, &d->ram); 789 789 + sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); 794 790 } 795 791 796 796 - static void ram_init(hwaddr addr, ram_addr_t RAM_size, 797 797 - uint64_t max_mem) 792 792 + static void ram_initfn(Object *obj) 798 793 { 799 799 - DeviceState *dev; 800 800 - SysBusDevice *s; 801 801 - RamDevice *d; 802 802 - 803 803 - /* allocate RAM */ 804 804 - if ((uint64_t)RAM_size > max_mem) { 805 805 - error_report("Too much memory for this machine: %" PRId64 "," 806 806 - " maximum %" PRId64, 807 807 - RAM_size / MiB, max_mem / MiB); 808 808 - exit(1); 809 809 - } 810 810 - dev = qdev_create(NULL, "memory"); 811 811 - s = SYS_BUS_DEVICE(dev); 812 812 - 813 813 - d = SUN4M_RAM(dev); 814 814 - d->size = RAM_size; 815 815 - qdev_init_nofail(dev); 816 816 - 817 817 - sysbus_mmio_map(s, 0, addr); 794 794 + RamDevice *d = SUN4M_RAM(obj); 795 795 + object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, 796 796 + (Object **)&d->memdev, 797 797 + object_property_allow_set_link, 798 798 + OBJ_PROP_LINK_STRONG, &error_abort); 799 799 + object_property_set_description(obj, "memdev", "Set RAM backend" 800 800 + "Valid value is ID of a hostmem backend", 801 801 + &error_abort); 818 802 } 819 803 820 820 - static Property ram_properties[] = { 821 821 - DEFINE_PROP_UINT64("size", RamDevice, size, 0), 822 822 - DEFINE_PROP_END_OF_LIST(), 823 823 - }; 824 824 - 825 804 static void ram_class_init(ObjectClass *klass, void *data) 826 805 { 827 806 DeviceClass *dc = DEVICE_CLASS(klass); 828 807 829 808 dc->realize = ram_realize; 830 830 - device_class_set_props(dc, ram_properties); 831 809 } 832 810 833 811 static const TypeInfo ram_info = { 834 812 .name = TYPE_SUN4M_MEMORY, 835 813 .parent = TYPE_SYS_BUS_DEVICE, 836 814 .instance_size = sizeof(RamDevice), 815 815 + .instance_init = ram_initfn, 837 816 .class_init = ram_class_init, 838 817 }; 839 818 ··· 879 858 SysBusDevice *s; 880 859 unsigned int smp_cpus = machine->smp.cpus; 881 860 unsigned int max_cpus = machine->smp.max_cpus; 861 861 + Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id, 862 862 + TYPE_MEMORY_BACKEND, NULL); 863 863 + 864 864 + if (machine->ram_size > hwdef->max_mem) { 865 865 + error_report("Too much memory for this machine: %" PRId64 "," 866 866 + " maximum %" PRId64, 867 867 + machine->ram_size / MiB, hwdef->max_mem / MiB); 868 868 + exit(1); 869 869 + } 882 870 883 871 /* init CPUs */ 884 872 for(i = 0; i < smp_cpus; i++) { ··· 888 876 for (i = smp_cpus; i < MAX_CPUS; i++) 889 877 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 890 878 879 879 + /* Create and map RAM frontend */ 880 880 + dev = qdev_create(NULL, "memory"); 881 881 + object_property_set_link(OBJECT(dev), ram_memdev, "memdev", &error_fatal); 882 882 + qdev_init_nofail(dev); 883 883 + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 891 884 892 892 - /* set up devices */ 893 893 - ram_init(0, machine->ram_size, hwdef->max_mem); 894 885 /* models without ECC don't trap when missing ram is accessed */ 895 886 if (!hwdef->ecc_base) { 896 887 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); ··· 1078 1069 1079 1070 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1080 1071 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1081 1081 - fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1072 1072 + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 1082 1073 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1083 1074 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1084 1075 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); ··· 1415 1406 mc->default_boot_order = "c"; 1416 1407 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1417 1408 mc->default_display = "tcx"; 1409 1409 + mc->default_ram_id = "sun4m.ram"; 1418 1410 } 1419 1411 1420 1412 static const TypeInfo ss5_type = { ··· 1434 1426 mc->default_boot_order = "c"; 1435 1427 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1436 1428 mc->default_display = "tcx"; 1429 1429 + mc->default_ram_id = "sun4m.ram"; 1437 1430 } 1438 1431 1439 1432 static const TypeInfo ss10_type = { ··· 1453 1446 mc->default_boot_order = "c"; 1454 1447 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1455 1448 mc->default_display = "tcx"; 1449 1449 + mc->default_ram_id = "sun4m.ram"; 1456 1450 } 1457 1451 1458 1452 static const TypeInfo ss600mp_type = { ··· 1472 1466 mc->default_boot_order = "c"; 1473 1467 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1474 1468 mc->default_display = "tcx"; 1469 1469 + mc->default_ram_id = "sun4m.ram"; 1475 1470 } 1476 1471 1477 1472 static const TypeInfo ss20_type = { ··· 1490 1485 mc->default_boot_order = "c"; 1491 1486 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1492 1487 mc->default_display = "tcx"; 1488 1488 + mc->default_ram_id = "sun4m.ram"; 1493 1489 } 1494 1490 1495 1491 static const TypeInfo voyager_type = { ··· 1508 1504 mc->default_boot_order = "c"; 1509 1505 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1510 1506 mc->default_display = "tcx"; 1507 1507 + mc->default_ram_id = "sun4m.ram"; 1511 1508 } 1512 1509 1513 1510 static const TypeInfo ss_lx_type = { ··· 1526 1523 mc->default_boot_order = "c"; 1527 1524 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1528 1525 mc->default_display = "tcx"; 1526 1526 + mc->default_ram_id = "sun4m.ram"; 1529 1527 } 1530 1528 1531 1529 static const TypeInfo ss4_type = { ··· 1544 1542 mc->default_boot_order = "c"; 1545 1543 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1546 1544 mc->default_display = "tcx"; 1545 1545 + mc->default_ram_id = "sun4m.ram"; 1547 1546 } 1548 1547 1549 1548 static const TypeInfo scls_type = { ··· 1562 1561 mc->default_boot_order = "c"; 1563 1562 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1564 1563 mc->default_display = "tcx"; 1564 1564 + mc->default_ram_id = "sun4m.ram"; 1565 1565 } 1566 1566 1567 1567 static const TypeInfo sbook_type = {

+2 -5

hw/sparc64/niagara.c

··· 40 40 41 41 typedef struct NiagaraBoardState { 42 42 MemoryRegion hv_ram; 43 43 - MemoryRegion partition_ram; 44 43 MemoryRegion nvram; 45 44 MemoryRegion md_rom; 46 45 MemoryRegion hv_rom; ··· 111 110 NIAGARA_HV_RAM_SIZE, &error_fatal); 112 111 memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram); 113 112 114 114 - memory_region_allocate_system_memory(&s->partition_ram, NULL, 115 115 - "sun4v-partition.ram", 116 116 - machine->ram_size); 117 113 memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE, 118 118 - &s->partition_ram); 114 114 + machine->ram); 119 115 120 116 memory_region_init_ram(&s->nvram, NULL, "sun4v.nvram", NIAGARA_NVRAM_SIZE, 121 117 &error_fatal); ··· 173 169 mc->max_cpus = 1; /* XXX for now */ 174 170 mc->default_boot_order = "c"; 175 171 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 172 172 + mc->default_ram_id = "sun4v-partition.ram"; 176 173 } 177 174 178 175 static const TypeInfo niagara_type = {

+21 -33

include/hw/boards.h

··· 4 4 #define HW_BOARDS_H 5 5 6 6 #include "exec/memory.h" 7 7 + #include "sysemu/hostmem.h" 7 8 #include "sysemu/blockdev.h" 8 9 #include "sysemu/accel.h" 9 10 #include "qapi/qapi-types-machine.h" ··· 11 12 #include "qom/object.h" 12 13 #include "hw/core/cpu.h" 13 14 14 14 - /** 15 15 - * memory_region_allocate_system_memory - Allocate a board's main memory 16 16 - * @mr: the #MemoryRegion to be initialized 17 17 - * @owner: the object that tracks the region's reference count 18 18 - * @name: name of the memory region 19 19 - * @ram_size: size of the region in bytes 20 20 - * 21 21 - * This function allocates the main memory for a board model, and 22 22 - * initializes @mr appropriately. It also arranges for the memory 23 23 - * to be migrated (by calling vmstate_register_ram_global()). 24 24 - * 25 25 - * Memory allocated via this function will be backed with the memory 26 26 - * backend the user provided using "-mem-path" or "-numa node,memdev=..." 27 27 - * if appropriate; this is typically used to cause host huge pages to be 28 28 - * used. This function should therefore be called by a board exactly once, 29 29 - * for the primary or largest RAM area it implements. 30 30 - * 31 31 - * For boards where the major RAM is split into two parts in the memory 32 32 - * map, you can deal with this by calling memory_region_allocate_system_memory() 33 33 - * once to get a MemoryRegion with enough RAM for both parts, and then 34 34 - * creating alias MemoryRegions via memory_region_init_alias() which 35 35 - * alias into different parts of the RAM MemoryRegion and can be mapped 36 36 - * into the memory map in the appropriate places. 37 37 - * 38 38 - * Smaller pieces of memory (display RAM, static RAMs, etc) don't need 39 39 - * to be backed via the -mem-path memory backend and can simply 40 40 - * be created via memory_region_init_ram(). 41 41 - */ 42 42 - void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, 43 43 - const char *name, 44 44 - uint64_t ram_size); 45 45 - 46 15 #define TYPE_MACHINE_SUFFIX "-machine" 47 16 48 17 /* Machine class name that needs to be used for class-name-based machine ··· 72 41 Error **errp); 73 42 74 43 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type); 75 75 - 44 44 + /* 45 45 + * Checks that backend isn't used, preps it for exclusive usage and 46 46 + * returns migratable MemoryRegion provided by backend. 47 47 + */ 48 48 + MemoryRegion *machine_consume_memdev(MachineState *machine, 49 49 + HostMemoryBackend *backend); 76 50 77 51 /** 78 52 * CPUArchId: ··· 169 143 * false is returned, an error must be set to show the reason of 170 144 * the rejection. If the hook is not provided, all hotplug will be 171 145 * allowed. 146 146 + * @default_ram_id: 147 147 + * Specifies inital RAM MemoryRegion name to be used for default backend 148 148 + * creation if user explicitly hasn't specified backend with "memory-backend" 149 149 + * property. 150 150 + * It also will be used as a way to optin into "-m" option support. 151 151 + * If it's not set by board, '-m' will be ignored and generic code will 152 152 + * not create default RAM MemoryRegion. 172 153 */ 173 154 struct MachineClass { 174 155 /*< private >*/ ··· 225 206 bool nvdimm_supported; 226 207 bool numa_mem_supported; 227 208 bool auto_enable_numa; 209 209 + const char *default_ram_id; 228 210 229 211 HotplugHandler *(*get_hotplug_handler)(MachineState *machine, 230 212 DeviceState *dev); ··· 285 267 bool enforce_config_section; 286 268 bool enable_graphics; 287 269 char *memory_encryption; 270 270 + char *ram_memdev_id; 271 271 + /* 272 272 + * convenience alias to ram_memdev_id backend memory region 273 273 + * or to numa container memory region 274 274 + */ 275 275 + MemoryRegion *ram; 288 276 DeviceMemoryState *device_memory; 289 277 290 278 ram_addr_t ram_size;

+1

include/hw/misc/aspeed_sdmc.h

··· 40 40 SysBusDeviceClass parent_class; 41 41 42 42 uint64_t max_ram_size; 43 43 + const uint64_t *valid_ram_sizes; 43 44 uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data); 44 45 void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data); 45 46 } AspeedSDMCClass;

+4 -5

include/hw/ppc/ppc4xx.h

··· 42 42 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, 43 43 uint32_t dcr_base, int has_ssr, int has_vr); 44 44 45 45 - ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, 46 46 - MemoryRegion ram_memories[], 47 47 - hwaddr ram_bases[], 48 48 - hwaddr ram_sizes[], 49 49 - const ram_addr_t sdram_bank_sizes[]); 45 45 + void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 46 46 + MemoryRegion ram_memories[], 47 47 + hwaddr ram_bases[], hwaddr ram_sizes[], 48 48 + const ram_addr_t sdram_bank_sizes[]); 50 49 51 50 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, 52 51 MemoryRegion ram_memories[],

+19 -1

include/sysemu/hostmem.h

··· 27 27 #define MEMORY_BACKEND_CLASS(klass) \ 28 28 OBJECT_CLASS_CHECK(HostMemoryBackendClass, (klass), TYPE_MEMORY_BACKEND) 29 29 30 30 + /* hostmem-ram.c */ 31 31 + /** 32 32 + * @TYPE_MEMORY_BACKEND_RAM: 33 33 + * name of backend that uses mmap on the anonymous RAM 34 34 + */ 35 35 + 36 36 + #define TYPE_MEMORY_BACKEND_RAM "memory-backend-ram" 37 37 + 38 38 + /* hostmem-file.c */ 39 39 + /** 40 40 + * @TYPE_MEMORY_BACKEND_FILE: 41 41 + * name of backend that uses mmap on a file descriptor 42 42 + */ 43 43 + #define TYPE_MEMORY_BACKEND_FILE "memory-backend-file" 44 44 + 45 45 + typedef struct HostMemoryBackend HostMemoryBackend; 30 46 typedef struct HostMemoryBackendClass HostMemoryBackendClass; 31 47 32 48 /** ··· 45 61 * @parent: opaque parent object container 46 62 * @size: amount of memory backend provides 47 63 * @mr: MemoryRegion representing host memory belonging to backend 64 64 + * @prealloc_threads: number of threads to be used for preallocatining RAM 48 65 */ 49 66 struct HostMemoryBackend { 50 67 /* private */ ··· 53 70 /* protected */ 54 71 uint64_t size; 55 72 bool merge, dump, use_canonical_path; 56 56 - bool prealloc, force_prealloc, is_mapped, share; 73 73 + bool prealloc, is_mapped, share; 74 74 + uint32_t prealloc_threads; 57 75 DECLARE_BITMAP(host_nodes, MAX_NODES + 1); 58 76 HostMemPolicy policy; 59 77

+1

include/sysemu/numa.h

··· 112 112 int nb_nodes, ram_addr_t size); 113 113 void numa_cpu_pre_plug(const struct CPUArchId *slot, DeviceState *dev, 114 114 Error **errp); 115 115 + bool numa_uses_legacy_mem(void); 115 116 116 117 #endif

-2

include/sysemu/sysemu.h

··· 50 50 extern bool enable_mlock; 51 51 extern bool enable_cpu_pm; 52 52 extern QEMUClockType rtc_clock; 53 53 - extern const char *mem_path; 54 54 - extern int mem_prealloc; 55 53 56 54 #define MAX_OPTION_ROMS 16 57 55 typedef struct QEMUOptionRom {

-9

qemu-deprecated.texi

··· 113 113 Use @option{memdev} with @var{memory-backend-ram} backend or @option{mem} (if 114 114 it's supported by used machine type) to define mapping explictly instead. 115 115 116 116 - @subsection -mem-path fallback to RAM (since 4.1) 117 117 - Currently if guest RAM allocation from file pointed by @option{mem-path} 118 118 - fails, QEMU falls back to allocating from RAM, which might result 119 119 - in unpredictable behavior since the backing file specified by the user 120 120 - is ignored. In the future, users will be responsible for making sure 121 121 - the backing storage specified with @option{-mem-path} can actually provide 122 122 - the guest RAM configured with @option{-m} and QEMU will fail to start up if 123 123 - RAM allocation is unsuccessful. 124 124 - 125 116 @subsection RISC-V -bios (since 4.1) 126 117 127 118 QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the

+63 -15

softmmu/vl.c

··· 56 56 #include "ui/input.h" 57 57 #include "sysemu/sysemu.h" 58 58 #include "sysemu/numa.h" 59 59 + #include "sysemu/hostmem.h" 59 60 #include "exec/gdbstub.h" 60 61 #include "qemu/timer.h" 61 62 #include "chardev/char.h" ··· 120 121 int display_opengl; 121 122 const char* keyboard_layout = NULL; 122 123 ram_addr_t ram_size; 123 123 - const char *mem_path = NULL; 124 124 - int mem_prealloc = 0; /* force preallocation of physical target memory */ 125 124 bool enable_mlock = false; 126 125 bool enable_cpu_pm = false; 127 126 int nb_nics; ··· 2635 2634 exit(EXIT_FAILURE); 2636 2635 } 2637 2636 2637 2637 + if (current_machine->ram_memdev_id) { 2638 2638 + Object *backend; 2639 2639 + ram_addr_t backend_size; 2640 2640 + 2641 2641 + backend = object_resolve_path_type(current_machine->ram_memdev_id, 2642 2642 + TYPE_MEMORY_BACKEND, NULL); 2643 2643 + backend_size = object_property_get_uint(backend, "size", &error_abort); 2644 2644 + if (mem_str && backend_size != ram_size) { 2645 2645 + error_report("Size specified by -m option must match size of " 2646 2646 + "explicitly specified 'memory-backend' property"); 2647 2647 + exit(EXIT_FAILURE); 2648 2648 + } 2649 2649 + ram_size = backend_size; 2650 2650 + } 2651 2651 + 2652 2652 + if (!xen_enabled()) { 2653 2653 + /* On 32-bit hosts, QEMU is limited by virtual address space */ 2654 2654 + if (ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 2655 2655 + error_report("at most 2047 MB RAM can be simulated"); 2656 2656 + exit(1); 2657 2657 + } 2658 2658 + } 2659 2659 + 2638 2660 loc_pop(&loc); 2639 2661 } 2640 2662 ··· 2786 2808 } 2787 2809 } 2788 2810 2811 2811 + static void create_default_memdev(MachineState *ms, const char *path) 2812 2812 + { 2813 2813 + Object *obj; 2814 2814 + MachineClass *mc = MACHINE_GET_CLASS(ms); 2815 2815 + 2816 2816 + obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 2817 2817 + if (path) { 2818 2818 + object_property_set_str(obj, path, "mem-path", &error_fatal); 2819 2819 + } 2820 2820 + object_property_set_int(obj, ms->ram_size, "size", &error_fatal); 2821 2821 + object_property_add_child(object_get_objects_root(), mc->default_ram_id, 2822 2822 + obj, &error_fatal); 2823 2823 + user_creatable_complete(USER_CREATABLE(obj), &error_fatal); 2824 2824 + object_unref(obj); 2825 2825 + object_property_set_str(OBJECT(ms), mc->default_ram_id, "memory-backend", 2826 2826 + &error_fatal); 2827 2827 + } 2828 2828 + 2789 2829 void qemu_init(int argc, char **argv, char **envp) 2790 2830 { 2791 2831 int i; ··· 2820 2860 Error *err = NULL; 2821 2861 bool list_data_dirs = false; 2822 2862 char *dir, **dirs; 2863 2863 + const char *mem_path = NULL; 2823 2864 BlockdevOptionsQueue bdo_queue = QSIMPLEQ_HEAD_INITIALIZER(bdo_queue); 2824 2865 QemuPluginList plugin_list = QTAILQ_HEAD_INITIALIZER(plugin_list); 2866 2866 + int mem_prealloc = 0; /* force preallocation of physical target memory */ 2825 2867 2826 2868 os_set_line_buffering(); 2827 2869 ··· 3779 3821 machine_class = select_machine(); 3780 3822 object_set_machine_compat_props(machine_class->compat_props); 3781 3823 3782 3782 - set_memory_options(&ram_slots, &maxram_size, machine_class); 3783 3783 - 3784 3824 os_daemonize(); 3785 3825 3786 3826 /* ··· 3929 3969 exit(1); 3930 3970 } 3931 3971 3972 3972 + if (mem_prealloc) { 3973 3973 + char *val; 3974 3974 + 3975 3975 + val = g_strdup_printf("%d", current_machine->smp.cpus); 3976 3976 + object_register_sugar_prop("memory-backend", "prealloc-threads", val); 3977 3977 + g_free(val); 3978 3978 + object_register_sugar_prop("memory-backend", "prealloc", "on"); 3979 3979 + } 3980 3980 + 3932 3981 /* 3933 3982 * Get the default machine options from the machine if it is not already 3934 3983 * specified either by the configuration file or by the command line. ··· 4092 4141 machine_opts = qemu_get_machine_opts(); 4093 4142 qemu_opt_foreach(machine_opts, machine_set_property, current_machine, 4094 4143 &error_fatal); 4095 4095 - current_machine->ram_size = ram_size; 4096 4096 - current_machine->maxram_size = maxram_size; 4097 4097 - current_machine->ram_slots = ram_slots; 4098 4144 4099 4145 /* 4100 4146 * Note: uses machine properties such as kernel-irqchip, must run ··· 4205 4251 4206 4252 tpm_init(); 4207 4253 4208 4208 - if (!xen_enabled()) { 4209 4209 - /* On 32-bit hosts, QEMU is limited by virtual address space */ 4210 4210 - if (ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 4211 4211 - error_report("at most 2047 MB RAM can be simulated"); 4212 4212 - exit(1); 4213 4213 - } 4214 4214 - } 4215 4215 - 4216 4254 blk_mig_init(); 4217 4255 ram_mig_init(); 4218 4256 dirty_bitmap_mig_init(); ··· 4257 4295 if (cpu_option) { 4258 4296 current_machine->cpu_type = parse_cpu_option(cpu_option); 4259 4297 } 4298 4298 + 4299 4299 + set_memory_options(&ram_slots, &maxram_size, machine_class); 4300 4300 + current_machine->ram_size = ram_size; 4301 4301 + current_machine->maxram_size = maxram_size; 4302 4302 + current_machine->ram_slots = ram_slots; 4303 4303 + 4260 4304 parse_numa_opts(current_machine); 4261 4305 4306 4306 + if (machine_class->default_ram_id && current_machine->ram_size && 4307 4307 + numa_uses_legacy_mem() && !current_machine->ram_memdev_id) { 4308 4308 + create_default_memdev(current_machine, mem_path); 4309 4309 + } 4262 4310 /* do monitor/qmp handling at preconfig state if requested */ 4263 4311 qemu_main_loop(); 4264 4312

+72 -66

tests/qtest/numa-test.c

··· 14 14 #include "qapi/qmp/qdict.h" 15 15 #include "qapi/qmp/qlist.h" 16 16 17 17 - static char *make_cli(const char *generic_cli, const char *test_cli) 17 17 + static char *make_cli(const GString *generic_cli, const char *test_cli) 18 18 { 19 19 - return g_strdup_printf("%s %s", generic_cli ? generic_cli : "", test_cli); 19 19 + return g_strdup_printf("%s %s", generic_cli->str, test_cli); 20 20 } 21 21 22 22 static void test_mon_explicit(const void *data) 23 23 { 24 24 - char *s; 25 25 - char *cli; 26 24 QTestState *qts; 25 25 + g_autofree char *s = NULL; 26 26 + g_autofree char *cli = NULL; 27 27 28 28 - cli = make_cli(data, "-smp 8 " 29 29 - "-numa node,nodeid=0,cpus=0-3 " 30 30 - "-numa node,nodeid=1,cpus=4-7 "); 28 28 + cli = make_cli(data, "-smp 8 -numa node,nodeid=0,memdev=ram,cpus=0-3 " 29 29 + "-numa node,nodeid=1,cpus=4-7"); 31 30 qts = qtest_init(cli); 32 31 33 32 s = qtest_hmp(qts, "info numa"); 34 33 g_assert(strstr(s, "node 0 cpus: 0 1 2 3")); 35 34 g_assert(strstr(s, "node 1 cpus: 4 5 6 7")); 36 36 - g_free(s); 37 35 38 36 qtest_quit(qts); 39 39 - g_free(cli); 40 37 } 41 38 42 42 - static void test_mon_default(const void *data) 39 39 + static void test_def_cpu_split(const void *data) 43 40 { 44 44 - char *s; 45 45 - char *cli; 46 41 QTestState *qts; 42 42 + g_autofree char *s = NULL; 43 43 + g_autofree char *cli = NULL; 47 44 48 48 - cli = make_cli(data, "-smp 8 -numa node -numa node"); 45 45 + cli = make_cli(data, "-smp 8 -numa node,memdev=ram -numa node"); 49 46 qts = qtest_init(cli); 50 47 51 48 s = qtest_hmp(qts, "info numa"); 52 49 g_assert(strstr(s, "node 0 cpus: 0 2 4 6")); 53 50 g_assert(strstr(s, "node 1 cpus: 1 3 5 7")); 54 54 - g_free(s); 55 51 56 52 qtest_quit(qts); 57 57 - g_free(cli); 58 53 } 59 54 60 55 static void test_mon_partial(const void *data) 61 56 { 62 62 - char *s; 63 63 - char *cli; 64 57 QTestState *qts; 58 58 + g_autofree char *s = NULL; 59 59 + g_autofree char *cli = NULL; 65 60 66 61 cli = make_cli(data, "-smp 8 " 67 67 - "-numa node,nodeid=0,cpus=0-1 " 62 62 + "-numa node,nodeid=0,memdev=ram,cpus=0-1 " 68 63 "-numa node,nodeid=1,cpus=4-5 "); 69 64 qts = qtest_init(cli); 70 65 71 66 s = qtest_hmp(qts, "info numa"); 72 67 g_assert(strstr(s, "node 0 cpus: 0 1 2 3 6 7")); 73 68 g_assert(strstr(s, "node 1 cpus: 4 5")); 74 74 - g_free(s); 75 69 76 70 qtest_quit(qts); 77 77 - g_free(cli); 78 71 } 79 72 80 73 static QList *get_cpus(QTestState *qts, QDict **resp) ··· 87 80 88 81 static void test_query_cpus(const void *data) 89 82 { 90 90 - char *cli; 91 83 QDict *resp; 92 84 QList *cpus; 93 85 QObject *e; 94 86 QTestState *qts; 87 87 + g_autofree char *cli = NULL; 95 88 96 96 - cli = make_cli(data, "-smp 8 -numa node,cpus=0-3 -numa node,cpus=4-7"); 89 89 + cli = make_cli(data, "-smp 8 -numa node,memdev=ram,cpus=0-3 " 90 90 + "-numa node,cpus=4-7"); 97 91 qts = qtest_init(cli); 98 92 cpus = get_cpus(qts, &resp); 99 93 g_assert(cpus); ··· 120 114 121 115 qobject_unref(resp); 122 116 qtest_quit(qts); 123 123 - g_free(cli); 124 117 } 125 118 126 119 static void pc_numa_cpu(const void *data) 127 120 { 128 128 - char *cli; 129 121 QDict *resp; 130 122 QList *cpus; 131 123 QObject *e; 132 124 QTestState *qts; 125 125 + g_autofree char *cli = NULL; 133 126 134 127 cli = make_cli(data, "-cpu pentium -smp 8,sockets=2,cores=2,threads=2 " 135 135 - "-numa node,nodeid=0 -numa node,nodeid=1 " 128 128 + "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " 136 129 "-numa cpu,node-id=1,socket-id=0 " 137 130 "-numa cpu,node-id=0,socket-id=1,core-id=0 " 138 131 "-numa cpu,node-id=0,socket-id=1,core-id=1,thread-id=0 " ··· 174 167 175 168 qobject_unref(resp); 176 169 qtest_quit(qts); 177 177 - g_free(cli); 178 170 } 179 171 180 172 static void spapr_numa_cpu(const void *data) 181 173 { 182 182 - char *cli; 183 174 QDict *resp; 184 175 QList *cpus; 185 176 QObject *e; 186 177 QTestState *qts; 178 178 + g_autofree char *cli = NULL; 187 179 188 180 cli = make_cli(data, "-smp 4,cores=4 " 189 189 - "-numa node,nodeid=0 -numa node,nodeid=1 " 181 181 + "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " 190 182 "-numa cpu,node-id=0,core-id=0 " 191 183 "-numa cpu,node-id=0,core-id=1 " 192 184 "-numa cpu,node-id=0,core-id=2 " ··· 220 212 221 213 qobject_unref(resp); 222 214 qtest_quit(qts); 223 223 - g_free(cli); 224 215 } 225 216 226 217 static void aarch64_numa_cpu(const void *data) 227 218 { 228 228 - char *cli; 229 219 QDict *resp; 230 220 QList *cpus; 231 221 QObject *e; 232 222 QTestState *qts; 223 223 + g_autofree char *cli = NULL; 233 224 234 225 cli = make_cli(data, "-smp 2 " 235 235 - "-numa node,nodeid=0 -numa node,nodeid=1 " 226 226 + "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " 236 227 "-numa cpu,node-id=1,thread-id=0 " 237 228 "-numa cpu,node-id=0,thread-id=1"); 238 229 qts = qtest_init(cli); ··· 264 255 265 256 qobject_unref(resp); 266 257 qtest_quit(qts); 267 267 - g_free(cli); 268 258 } 269 259 270 260 static void pc_dynamic_cpu_cfg(const void *data) ··· 273 263 QDict *resp; 274 264 QList *cpus; 275 265 QTestState *qs; 266 266 + g_autofree char *cli = NULL; 276 267 277 277 - qs = qtest_initf("%s -nodefaults --preconfig -smp 2", 278 278 - data ? (char *)data : ""); 268 268 + cli = make_cli(data, "-nodefaults --preconfig -smp 2"); 269 269 + qs = qtest_init(cli); 279 270 280 271 /* create 2 numa nodes */ 281 272 g_assert(!qmp_rsp_is_err(qtest_qmp(qs, "{ 'execute': 'set-numa-node'," 282 282 - " 'arguments': { 'type': 'node', 'nodeid': 0 } }"))); 273 273 + " 'arguments': { 'type': 'node', 'nodeid': 0, 'memdev': 'ram' } }"))); 283 274 g_assert(!qmp_rsp_is_err(qtest_qmp(qs, "{ 'execute': 'set-numa-node'," 284 275 " 'arguments': { 'type': 'node', 'nodeid': 1 } }"))); 285 276 ··· 329 320 330 321 static void pc_hmat_build_cfg(const void *data) 331 322 { 332 332 - QTestState *qs = qtest_initf("%s -nodefaults --preconfig -machine hmat=on " 333 333 - "-smp 2,sockets=2 " 334 334 - "-m 128M,slots=2,maxmem=1G " 335 335 - "-object memory-backend-ram,size=64M,id=m0 " 336 336 - "-object memory-backend-ram,size=64M,id=m1 " 337 337 - "-numa node,nodeid=0,memdev=m0 " 338 338 - "-numa node,nodeid=1,memdev=m1,initiator=0 " 339 339 - "-numa cpu,node-id=0,socket-id=0 " 340 340 - "-numa cpu,node-id=0,socket-id=1", 341 341 - data ? (char *)data : ""); 323 323 + QTestState *qs; 324 324 + g_autofree char *cli = NULL; 325 325 + 326 326 + cli = make_cli(data, "-nodefaults --preconfig -machine hmat=on " 327 327 + "-smp 2,sockets=2 " 328 328 + "-m 128M,slots=2,maxmem=1G " 329 329 + "-object memory-backend-ram,size=64M,id=m0 " 330 330 + "-object memory-backend-ram,size=64M,id=m1 " 331 331 + "-numa node,nodeid=0,memdev=m0 " 332 332 + "-numa node,nodeid=1,memdev=m1,initiator=0 " 333 333 + "-numa cpu,node-id=0,socket-id=0 " 334 334 + "-numa cpu,node-id=0,socket-id=1"); 335 335 + qs = qtest_init(cli); 342 336 343 337 /* Fail: Initiator should be less than the number of nodes */ 344 338 g_assert_true(qmp_rsp_is_err(qtest_qmp(qs, "{ 'execute': 'set-numa-node'," ··· 455 449 456 450 static void pc_hmat_off_cfg(const void *data) 457 451 { 458 458 - QTestState *qs = qtest_initf("%s -nodefaults --preconfig " 459 459 - "-smp 2,sockets=2 " 460 460 - "-m 128M,slots=2,maxmem=1G " 461 461 - "-object memory-backend-ram,size=64M,id=m0 " 462 462 - "-object memory-backend-ram,size=64M,id=m1 " 463 463 - "-numa node,nodeid=0,memdev=m0", 464 464 - data ? (char *)data : ""); 452 452 + QTestState *qs; 453 453 + g_autofree char *cli = NULL; 454 454 + 455 455 + cli = make_cli(data, "-nodefaults --preconfig " 456 456 + "-smp 2,sockets=2 " 457 457 + "-m 128M,slots=2,maxmem=1G " 458 458 + "-object memory-backend-ram,size=64M,id=m0 " 459 459 + "-object memory-backend-ram,size=64M,id=m1 " 460 460 + "-numa node,nodeid=0,memdev=m0"); 461 461 + qs = qtest_init(cli); 465 462 466 463 /* 467 464 * Fail: Enable HMAT with -machine hmat=on ··· 491 488 492 489 static void pc_hmat_erange_cfg(const void *data) 493 490 { 494 494 - QTestState *qs = qtest_initf("%s -nodefaults --preconfig -machine hmat=on " 495 495 - "-smp 2,sockets=2 " 496 496 - "-m 128M,slots=2,maxmem=1G " 497 497 - "-object memory-backend-ram,size=64M,id=m0 " 498 498 - "-object memory-backend-ram,size=64M,id=m1 " 499 499 - "-numa node,nodeid=0,memdev=m0 " 500 500 - "-numa node,nodeid=1,memdev=m1,initiator=0 " 501 501 - "-numa cpu,node-id=0,socket-id=0 " 502 502 - "-numa cpu,node-id=0,socket-id=1", 503 503 - data ? (char *)data : ""); 491 491 + QTestState *qs; 492 492 + g_autofree char *cli = NULL; 493 493 + 494 494 + cli = make_cli(data, "-nodefaults --preconfig -machine hmat=on " 495 495 + "-smp 2,sockets=2 " 496 496 + "-m 128M,slots=2,maxmem=1G " 497 497 + "-object memory-backend-ram,size=64M,id=m0 " 498 498 + "-object memory-backend-ram,size=64M,id=m1 " 499 499 + "-numa node,nodeid=0,memdev=m0 " 500 500 + "-numa node,nodeid=1,memdev=m1,initiator=0 " 501 501 + "-numa cpu,node-id=0,socket-id=0 " 502 502 + "-numa cpu,node-id=0,socket-id=1"); 503 503 + qs = qtest_init(cli); 504 504 505 505 /* Can't store the compressed latency */ 506 506 g_assert_false(qmp_rsp_is_err(qtest_qmp(qs, "{ 'execute': 'set-numa-node'," ··· 539 539 540 540 int main(int argc, char **argv) 541 541 { 542 542 - const char *args = NULL; 542 542 + g_autoptr(GString) args = g_string_new(NULL); 543 543 const char *arch = qtest_get_arch(); 544 544 545 545 - if (strcmp(arch, "aarch64") == 0) { 546 546 - args = "-machine virt"; 545 545 + if (g_str_equal(arch, "ppc64")) { 546 546 + g_string_append(args, " -object memory-backend-ram,id=ram,size=512M"); 547 547 + } else { 548 548 + g_string_append(args, " -object memory-backend-ram,id=ram,size=128M"); 549 549 + } 550 550 + 551 551 + if (g_str_equal(arch, "aarch64")) { 552 552 + g_string_append(args, " -machine virt"); 547 553 } 548 554 549 555 g_test_init(&argc, &argv, NULL); 550 556 551 551 - qtest_add_data_func("/numa/mon/default", args, test_mon_default); 557 557 + qtest_add_data_func("/numa/mon/cpus/default", args, test_def_cpu_split); 552 558 qtest_add_data_func("/numa/mon/cpus/explicit", args, test_mon_explicit); 553 559 qtest_add_data_func("/numa/mon/cpus/partial", args, test_mon_partial); 554 560 qtest_add_data_func("/numa/qmp/cpus/query-cpus", args, test_query_cpus);