hw/mips: Add CPU IRQ3 delivery for KVM

qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add
IP3 delivery as well, because Loongson-3 based machine use both IRQ2
(CPU's IP2) and IRQ3 (CPU's IP3).

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1588501221-1205-4-git-send-email-chenhc@lemote.com>

authored by

Huacai Chen and committed by

Aleksandar Markovic 5 years ago c3173a35 aa2953fd

+1 -1

1 changed file

expand all

mips

mips_int.c

+1 -1

hw/mips/mips_int.c

··· 51 51 env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); 52 52 } 53 53 54 - if (kvm_enabled() && irq == 2) { 54 + if (kvm_enabled() && (irq == 2 || irq == 3)) { 55 55 kvm_mips_set_interrupt(cpu, irq, level); 56 56 } 57 57