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qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models

The power7_set_irq() and power9_set_irq() functions set this but it is
never used actually. Modern Book3s compatible CPUs are only supported
by the pnv and spapr machines. They have an interrupt controller, XICS
for POWER7/8 and XIVE for POWER9, whose models don't require to track
IRQ input states at the CPU level.

Drop these lines to avoid confusion.

Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <157548862861.3650476.16622818876928044450.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

authored by

Greg Kurz and committed by
David Gibson c1ad0b89 4febcdd8

+5 -15
+2 -14
hw/ppc/ppc.c
··· 275 275 static void power7_set_irq(void *opaque, int pin, int level) 276 276 { 277 277 PowerPCCPU *cpu = opaque; 278 - CPUPPCState *env = &cpu->env; 279 278 280 279 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 281 - env, pin, level); 280 + &cpu->env, pin, level); 282 281 283 282 switch (pin) { 284 283 case POWER7_INPUT_INT: ··· 291 290 /* Unknown pin - do nothing */ 292 291 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 293 292 return; 294 - } 295 - if (level) { 296 - env->irq_input_state |= 1 << pin; 297 - } else { 298 - env->irq_input_state &= ~(1 << pin); 299 293 } 300 294 } 301 295 ··· 311 305 static void power9_set_irq(void *opaque, int pin, int level) 312 306 { 313 307 PowerPCCPU *cpu = opaque; 314 - CPUPPCState *env = &cpu->env; 315 308 316 309 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 317 - env, pin, level); 310 + &cpu->env, pin, level); 318 311 319 312 switch (pin) { 320 313 case POWER9_INPUT_INT: ··· 333 326 /* Unknown pin - do nothing */ 334 327 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 335 328 return; 336 - } 337 - if (level) { 338 - env->irq_input_state |= 1 << pin; 339 - } else { 340 - env->irq_input_state &= ~(1 << pin); 341 329 } 342 330 } 343 331
+3 -1
target/ppc/cpu.h
··· 1090 1090 #if !defined(CONFIG_USER_ONLY) 1091 1091 /* 1092 1092 * This is the IRQ controller, which is implementation dependent 1093 - * and only relevant when emulating a complete machine. 1093 + * and only relevant when emulating a complete machine. Note that 1094 + * this isn't used by recent Book3s compatible CPUs (POWER7 and 1095 + * newer). 1094 1096 */ 1095 1097 uint32_t irq_input_state; 1096 1098 void **irq_inputs;