jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/intc: Add Loongson LIOINTC support
Loongson-3 has an integrated liointc (Local I/O Interrupt Controller).
It is similar to Goldfish interrupt controller, but more powerful (e.g.,
it can route external interrupt to multi-cores).
Documents about Loongson-3's liointc:
1, https://wiki.godson.ac.cn/ip_block:liointc;
2, The "I/O中断" section of Loongson-3's user mannual, part 1.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1592995531-32600-3-git-send-email-chenhc@lemote.com>
authored by
Huacai Chen
and committed by
Aleksandar Markovic
c012e0b1
719d109b
+246
+3
hw/intc/Kconfig
+3
hw/intc/Kconfig
+1
hw/intc/Makefile.objs
+1
hw/intc/Makefile.objs
+242
hw/intc/loongson_liointc.c
+242
hw/intc/loongson_liointc.c
···
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/*
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* QEMU Loongson Local I/O interrupt controler.
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*
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* Copyright (c) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "qemu/module.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#define D(x)
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#define NUM_IRQS 32
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#define NUM_CORES 4
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#define NUM_IPS 4
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#define NUM_PARENTS (NUM_CORES * NUM_IPS)
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#define PARENT_COREx_IPy(x, y) (NUM_IPS * x + y)
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#define R_MAPPER_START 0x0
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#define R_MAPPER_END 0x20
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#define R_ISR R_MAPPER_END
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#define R_IEN 0x24
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#define R_IEN_SET 0x28
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#define R_IEN_CLR 0x2c
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#define R_PERCORE_ISR(x) (0x40 + 0x8 * x)
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#define R_END 0x64
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#define TYPE_LOONGSON_LIOINTC "loongson.liointc"
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#define LOONGSON_LIOINTC(obj) \
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OBJECT_CHECK(struct loongson_liointc, (obj), TYPE_LOONGSON_LIOINTC)
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struct loongson_liointc {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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qemu_irq parent_irq[NUM_PARENTS];
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uint8_t mapper[NUM_IRQS]; /* 0:3 for core, 4:7 for IP */
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uint32_t isr;
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uint32_t ien;
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uint32_t per_core_isr[NUM_CORES];
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/* state of the interrupt input pins */
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uint32_t pin_state;
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bool parent_state[NUM_PARENTS];
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};
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static void update_irq(struct loongson_liointc *p)
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{
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uint32_t irq, core, ip;
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uint32_t per_ip_isr[NUM_IPS] = {0};
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/* level triggered interrupt */
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p->isr = p->pin_state;
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/* Clear disabled IRQs */
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p->isr &= p->ien;
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/* Clear per_core_isr */
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for (core = 0; core < NUM_CORES; core++) {
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p->per_core_isr[core] = 0;
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}
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/* Update per_core_isr and per_ip_isr */
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for (irq = 0; irq < NUM_IRQS; irq++) {
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if (!(p->isr & (1 << irq))) {
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continue;
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}
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for (core = 0; core < NUM_CORES; core++) {
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if ((p->mapper[irq] & (1 << core))) {
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p->per_core_isr[core] |= (1 << irq);
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}
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}
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for (ip = 0; ip < NUM_IPS; ip++) {
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if ((p->mapper[irq] & (1 << (ip + 4)))) {
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per_ip_isr[ip] |= (1 << irq);
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}
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}
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}
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/* Emit IRQ to parent! */
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for (core = 0; core < NUM_CORES; core++) {
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for (ip = 0; ip < NUM_IPS; ip++) {
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int parent = PARENT_COREx_IPy(core, ip);
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if (p->parent_state[parent] !=
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(!!p->per_core_isr[core] && !!per_ip_isr[ip])) {
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p->parent_state[parent] = !p->parent_state[parent];
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qemu_set_irq(p->parent_irq[parent], p->parent_state[parent]);
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}
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}
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}
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}
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static uint64_t
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liointc_read(void *opaque, hwaddr addr, unsigned int size)
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{
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struct loongson_liointc *p = opaque;
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uint32_t r = 0;
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/* Mapper is 1 byte */
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if (size == 1 && addr < R_MAPPER_END) {
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r = p->mapper[addr];
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goto out;
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}
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/* Rest is 4 byte */
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if (size != 4 || (addr % 4)) {
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goto out;
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}
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if (addr >= R_PERCORE_ISR(0) &&
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addr < R_PERCORE_ISR(NUM_CORES)) {
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int core = (addr - R_PERCORE_ISR(0)) / 4;
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r = p->per_core_isr[core];
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goto out;
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}
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switch (addr) {
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case R_ISR:
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r = p->isr;
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break;
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case R_IEN:
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r = p->ien;
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break;
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default:
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break;
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}
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out:
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D(qemu_log("%s: size=%d addr=%lx val=%x\n", __func__, size, addr, r));
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return r;
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}
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static void
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liointc_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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struct loongson_liointc *p = opaque;
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uint32_t value = val64;
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D(qemu_log("%s: size=%d, addr=%lx val=%x\n", __func__, size, addr, value));
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/* Mapper is 1 byte */
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if (size == 1 && addr < R_MAPPER_END) {
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p->mapper[addr] = value;
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goto out;
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}
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/* Rest is 4 byte */
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if (size != 4 || (addr % 4)) {
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goto out;
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}
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if (addr >= R_PERCORE_ISR(0) &&
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addr < R_PERCORE_ISR(NUM_CORES)) {
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int core = (addr - R_PERCORE_ISR(0)) / 4;
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p->per_core_isr[core] = value;
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goto out;
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}
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switch (addr) {
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case R_IEN_SET:
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p->ien |= value;
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break;
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case R_IEN_CLR:
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p->ien &= ~value;
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break;
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default:
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break;
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}
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out:
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update_irq(p);
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}
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static const MemoryRegionOps pic_ops = {
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.read = liointc_read,
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.write = liointc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4
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}
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};
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static void irq_handler(void *opaque, int irq, int level)
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{
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struct loongson_liointc *p = opaque;
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p->pin_state &= ~(1 << irq);
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p->pin_state |= level << irq;
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update_irq(p);
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}
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static void loongson_liointc_init(Object *obj)
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{
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struct loongson_liointc *p = LOONGSON_LIOINTC(obj);
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int i;
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qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
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for (i = 0; i < NUM_PARENTS; i++) {
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq[i]);
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}
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memory_region_init_io(&p->mmio, obj, &pic_ops, p,
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"loongson.liointc", R_END);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
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}
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static const TypeInfo loongson_liointc_info = {
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.name = TYPE_LOONGSON_LIOINTC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(struct loongson_liointc),
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.instance_init = loongson_liointc_init,
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};
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static void loongson_liointc_register_types(void)
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{
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type_register_static(&loongson_liointc_info);
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}
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type_init(loongson_liointc_register_types)