jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
qdev: use device_class_set_parent_realize/unrealize/reset()
changes generated using the following Coccinelle patch:
@@
type DeviceParentClass;
DeviceParentClass *pc;
DeviceClass *dc;
identifier parent_fn;
identifier child_fn;
@@
(
+device_class_set_parent_realize(dc, child_fn, &pc->parent_fn);
-pc->parent_fn = dc->realize;
...
-dc->realize = child_fn;
|
+device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn);
-pc->parent_fn = dc->unrealize;
...
-dc->unrealize = child_fn;
|
+device_class_set_parent_reset(dc, child_fn, &pc->parent_fn);
-pc->parent_fn = dc->reset;
...
-dc->reset = child_fn;
)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180114020412.26160-4-f4bug@amsat.org>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
authored by
Philippe Mathieu-Daudé
and committed by
Paolo Bonzini
bf853881
46795cf2
+73
-88
+2
-2
hw/i386/kvm/i8254.c
+2
-2
hw/i386/kvm/i8254.c
···
315
315
PITCommonClass *k = PIT_COMMON_CLASS(klass);
316
316
DeviceClass *dc = DEVICE_CLASS(klass);
317
317
318
-
kpc->parent_realize = dc->realize;
319
-
dc->realize = kvm_pit_realizefn;
318
+
device_class_set_parent_realize(dc, kvm_pit_realizefn,
319
+
&kpc->parent_realize);
320
320
k->set_channel_gate = kvm_pit_set_gate;
321
321
k->get_channel_info = kvm_pit_get_channel_info;
322
322
dc->reset = kvm_pit_reset;
+1
-2
hw/i386/kvm/i8259.c
+1
-2
hw/i386/kvm/i8259.c
···
142
142
DeviceClass *dc = DEVICE_CLASS(klass);
143
143
144
144
dc->reset = kvm_pic_reset;
145
-
kpc->parent_realize = dc->realize;
146
-
dc->realize = kvm_pic_realize;
145
+
device_class_set_parent_realize(dc, kvm_pic_realize, &kpc->parent_realize);
147
146
k->pre_save = kvm_pic_get;
148
147
k->post_load = kvm_pic_put;
149
148
}
+2
-2
hw/input/adb-kbd.c
+2
-2
hw/input/adb-kbd.c
···
374
374
ADBDeviceClass *adc = ADB_DEVICE_CLASS(oc);
375
375
ADBKeyboardClass *akc = ADB_KEYBOARD_CLASS(oc);
376
376
377
-
akc->parent_realize = dc->realize;
378
-
dc->realize = adb_kbd_realizefn;
377
+
device_class_set_parent_realize(dc, adb_kbd_realizefn,
378
+
&akc->parent_realize);
379
379
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
380
380
381
381
adc->devreq = adb_kbd_request;
+2
-2
hw/input/adb-mouse.c
+2
-2
hw/input/adb-mouse.c
···
228
228
ADBDeviceClass *adc = ADB_DEVICE_CLASS(oc);
229
229
ADBMouseClass *amc = ADB_MOUSE_CLASS(oc);
230
230
231
-
amc->parent_realize = dc->realize;
232
-
dc->realize = adb_mouse_realizefn;
231
+
device_class_set_parent_realize(dc, adb_mouse_realizefn,
232
+
&amc->parent_realize);
233
233
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
234
234
235
235
adc->devreq = adb_mouse_request;
+1
-2
hw/intc/arm_gic.c
+1
-2
hw/intc/arm_gic.c
···
1461
1461
DeviceClass *dc = DEVICE_CLASS(klass);
1462
1462
ARMGICClass *agc = ARM_GIC_CLASS(klass);
1463
1463
1464
-
agc->parent_realize = dc->realize;
1465
-
dc->realize = arm_gic_realize;
1464
+
device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);
1466
1465
}
1467
1466
1468
1467
static const TypeInfo arm_gic_info = {
+3
-4
hw/intc/arm_gic_kvm.c
+3
-4
hw/intc/arm_gic_kvm.c
···
591
591
592
592
agcc->pre_save = kvm_arm_gic_get;
593
593
agcc->post_load = kvm_arm_gic_put;
594
-
kgc->parent_realize = dc->realize;
595
-
kgc->parent_reset = dc->reset;
596
-
dc->realize = kvm_arm_gic_realize;
597
-
dc->reset = kvm_arm_gic_reset;
594
+
device_class_set_parent_realize(dc, kvm_arm_gic_realize,
595
+
&kgc->parent_realize);
596
+
device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
598
597
}
599
598
600
599
static const TypeInfo kvm_arm_gic_info = {
+1
-2
hw/intc/arm_gicv3.c
+1
-2
hw/intc/arm_gicv3.c
···
385
385
ARMGICv3Class *agc = ARM_GICV3_CLASS(klass);
386
386
387
387
agcc->post_load = arm_gicv3_post_load;
388
-
agc->parent_realize = dc->realize;
389
-
dc->realize = arm_gic_realize;
388
+
device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);
390
389
}
391
390
392
391
static const TypeInfo arm_gicv3_info = {
+1
-2
hw/intc/arm_gicv3_its_kvm.c
+1
-2
hw/intc/arm_gicv3_its_kvm.c
···
245
245
246
246
dc->realize = kvm_arm_its_realize;
247
247
dc->props = kvm_arm_its_props;
248
-
ic->parent_reset = dc->reset;
248
+
device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
249
249
icc->send_msi = kvm_its_send_msi;
250
250
icc->pre_save = kvm_arm_its_pre_save;
251
251
icc->post_load = kvm_arm_its_post_load;
252
-
dc->reset = kvm_arm_its_reset;
253
252
}
254
253
255
254
static const TypeInfo kvm_arm_its_info = {
+3
-4
hw/intc/arm_gicv3_kvm.c
+3
-4
hw/intc/arm_gicv3_kvm.c
···
795
795
796
796
agcc->pre_save = kvm_arm_gicv3_get;
797
797
agcc->post_load = kvm_arm_gicv3_put;
798
-
kgc->parent_realize = dc->realize;
799
-
kgc->parent_reset = dc->reset;
800
-
dc->realize = kvm_arm_gicv3_realize;
801
-
dc->reset = kvm_arm_gicv3_reset;
798
+
device_class_set_parent_realize(dc, kvm_arm_gicv3_realize,
799
+
&kgc->parent_realize);
800
+
device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset);
802
801
}
803
802
804
803
static const TypeInfo kvm_arm_gicv3_info = {
+1
-2
hw/intc/i8259.c
+1
-2
hw/intc/i8259.c
+2
-2
hw/net/vmxnet3.c
+2
-2
hw/net/vmxnet3.c
···
2664
2664
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2665
2665
c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2666
2666
c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2667
-
vc->parent_dc_realize = dc->realize;
2668
-
dc->realize = vmxnet3_realize;
2667
+
device_class_set_parent_realize(dc, vmxnet3_realize,
2668
+
&vc->parent_dc_realize);
2669
2669
dc->desc = "VMWare Paravirtualized Ethernet v3";
2670
2670
dc->reset = vmxnet3_qdev_reset;
2671
2671
dc->vmsd = &vmstate_vmxnet3;
+1
-2
hw/pci-bridge/gen_pcie_root_port.c
+1
-2
hw/pci-bridge/gen_pcie_root_port.c
···
137
137
dc->vmsd = &vmstate_rp_dev;
138
138
dc->props = gen_rp_props;
139
139
140
-
rpc->parent_realize = dc->realize;
141
-
dc->realize = gen_rp_realize;
140
+
device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
142
141
143
142
rpc->aer_vector = gen_rp_aer_vector;
144
143
rpc->interrupts_init = gen_rp_interrupts_init;
+2
-2
hw/scsi/vmw_pvscsi.c
+2
-2
hw/scsi/vmw_pvscsi.c
···
1284
1284
k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1285
1285
k->class_id = PCI_CLASS_STORAGE_SCSI;
1286
1286
k->subsystem_id = 0x1000;
1287
-
pvs_k->parent_dc_realize = dc->realize;
1288
-
dc->realize = pvscsi_realize;
1287
+
device_class_set_parent_realize(dc, pvscsi_realize,
1288
+
&pvs_k->parent_dc_realize);
1289
1289
dc->reset = pvscsi_reset;
1290
1290
dc->vmsd = &vmstate_pvscsi;
1291
1291
dc->props = pvscsi_properties;
+1
-2
hw/timer/i8254.c
+1
-2
hw/timer/i8254.c
···
358
358
PITCommonClass *k = PIT_COMMON_CLASS(klass);
359
359
DeviceClass *dc = DEVICE_CLASS(klass);
360
360
361
-
pc->parent_realize = dc->realize;
362
-
dc->realize = pit_realizefn;
361
+
device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize);
363
362
k->set_channel_gate = pit_set_channel_gate;
364
363
k->get_channel_info = pit_get_channel_info_common;
365
364
k->post_load = pit_post_load;
+2
-2
hw/vfio/amd-xgbe.c
+2
-2
hw/vfio/amd-xgbe.c
···
34
34
DeviceClass *dc = DEVICE_CLASS(klass);
35
35
VFIOAmdXgbeDeviceClass *vcxc =
36
36
VFIO_AMD_XGBE_DEVICE_CLASS(klass);
37
-
vcxc->parent_realize = dc->realize;
38
-
dc->realize = amd_xgbe_realize;
37
+
device_class_set_parent_realize(dc, amd_xgbe_realize,
38
+
&vcxc->parent_realize);
39
39
dc->desc = "VFIO AMD XGBE";
40
40
dc->vmsd = &vfio_platform_amd_xgbe_vmstate;
41
41
/* Supported by TYPE_VIRT_MACHINE */
+2
-2
hw/vfio/calxeda-xgmac.c
+2
-2
hw/vfio/calxeda-xgmac.c
···
34
34
DeviceClass *dc = DEVICE_CLASS(klass);
35
35
VFIOCalxedaXgmacDeviceClass *vcxc =
36
36
VFIO_CALXEDA_XGMAC_DEVICE_CLASS(klass);
37
-
vcxc->parent_realize = dc->realize;
38
-
dc->realize = calxeda_xgmac_realize;
37
+
device_class_set_parent_realize(dc, calxeda_xgmac_realize,
38
+
&vcxc->parent_realize);
39
39
dc->desc = "VFIO Calxeda XGMAC";
40
40
dc->vmsd = &vfio_platform_calxeda_xgmac_vmstate;
41
41
/* Supported by TYPE_VIRT_MACHINE */
+2
-2
hw/virtio/virtio-pci.c
+2
-2
hw/virtio/virtio-pci.c
···
1907
1907
k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
1908
1908
k->revision = VIRTIO_PCI_ABI_VERSION;
1909
1909
k->class_id = PCI_CLASS_OTHERS;
1910
-
vpciklass->parent_dc_realize = dc->realize;
1911
-
dc->realize = virtio_pci_dc_realize;
1910
+
device_class_set_parent_realize(dc, virtio_pci_dc_realize,
1911
+
&vpciklass->parent_dc_realize);
1912
1912
dc->reset = virtio_pci_reset;
1913
1913
}
1914
1914
+2
-2
target/alpha/cpu.c
+2
-2
target/alpha/cpu.c
···
233
233
CPUClass *cc = CPU_CLASS(oc);
234
234
AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
235
235
236
-
acc->parent_realize = dc->realize;
237
-
dc->realize = alpha_cpu_realizefn;
236
+
device_class_set_parent_realize(dc, alpha_cpu_realizefn,
237
+
&acc->parent_realize);
238
238
239
239
cc->class_by_name = alpha_cpu_class_by_name;
240
240
cc->has_work = alpha_cpu_has_work;
+2
-2
target/arm/cpu.c
+2
-2
target/arm/cpu.c
···
1722
1722
CPUClass *cc = CPU_CLASS(acc);
1723
1723
DeviceClass *dc = DEVICE_CLASS(oc);
1724
1724
1725
-
acc->parent_realize = dc->realize;
1726
-
dc->realize = arm_cpu_realizefn;
1725
+
device_class_set_parent_realize(dc, arm_cpu_realizefn,
1726
+
&acc->parent_realize);
1727
1727
dc->props = arm_cpu_properties;
1728
1728
1729
1729
acc->parent_reset = cc->reset;
+2
-2
target/cris/cpu.c
+2
-2
target/cris/cpu.c
···
260
260
CPUClass *cc = CPU_CLASS(oc);
261
261
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
262
262
263
-
ccc->parent_realize = dc->realize;
264
-
dc->realize = cris_cpu_realizefn;
263
+
device_class_set_parent_realize(dc, cris_cpu_realizefn,
264
+
&ccc->parent_realize);
265
265
266
266
ccc->parent_reset = cc->reset;
267
267
cc->reset = cris_cpu_reset;
+2
-2
target/hppa/cpu.c
+2
-2
target/hppa/cpu.c
···
168
168
CPUClass *cc = CPU_CLASS(oc);
169
169
HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
170
170
171
-
acc->parent_realize = dc->realize;
172
-
dc->realize = hppa_cpu_realizefn;
171
+
device_class_set_parent_realize(dc, hppa_cpu_realizefn,
172
+
&acc->parent_realize);
173
173
174
174
cc->class_by_name = hppa_cpu_class_by_name;
175
175
cc->has_work = hppa_cpu_has_work;
+4
-4
target/i386/cpu.c
+4
-4
target/i386/cpu.c
···
4705
4705
CPUClass *cc = CPU_CLASS(oc);
4706
4706
DeviceClass *dc = DEVICE_CLASS(oc);
4707
4707
4708
-
xcc->parent_realize = dc->realize;
4709
-
xcc->parent_unrealize = dc->unrealize;
4710
-
dc->realize = x86_cpu_realizefn;
4711
-
dc->unrealize = x86_cpu_unrealizefn;
4708
+
device_class_set_parent_realize(dc, x86_cpu_realizefn,
4709
+
&xcc->parent_realize);
4710
+
device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
4711
+
&xcc->parent_unrealize);
4712
4712
dc->props = x86_cpu_properties;
4713
4713
4714
4714
xcc->parent_reset = cc->reset;
+2
-3
target/lm32/cpu.c
+2
-3
target/lm32/cpu.c
···
236
236
CPUClass *cc = CPU_CLASS(oc);
237
237
DeviceClass *dc = DEVICE_CLASS(oc);
238
238
239
-
lcc->parent_realize = dc->realize;
240
-
dc->realize = lm32_cpu_realizefn;
241
-
239
+
device_class_set_parent_realize(dc, lm32_cpu_realizefn,
240
+
&lcc->parent_realize);
242
241
lcc->parent_reset = cc->reset;
243
242
cc->reset = lm32_cpu_reset;
244
243
+2
-3
target/m68k/cpu.c
+2
-3
target/m68k/cpu.c
···
255
255
CPUClass *cc = CPU_CLASS(c);
256
256
DeviceClass *dc = DEVICE_CLASS(c);
257
257
258
-
mcc->parent_realize = dc->realize;
259
-
dc->realize = m68k_cpu_realizefn;
260
-
258
+
device_class_set_parent_realize(dc, m68k_cpu_realizefn,
259
+
&mcc->parent_realize);
261
260
mcc->parent_reset = cc->reset;
262
261
cc->reset = m68k_cpu_reset;
263
262
+2
-3
target/microblaze/cpu.c
+2
-3
target/microblaze/cpu.c
···
258
258
CPUClass *cc = CPU_CLASS(oc);
259
259
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
260
260
261
-
mcc->parent_realize = dc->realize;
262
-
dc->realize = mb_cpu_realizefn;
263
-
261
+
device_class_set_parent_realize(dc, mb_cpu_realizefn,
262
+
&mcc->parent_realize);
264
263
mcc->parent_reset = cc->reset;
265
264
cc->reset = mb_cpu_reset;
266
265
+2
-3
target/mips/cpu.c
+2
-3
target/mips/cpu.c
···
174
174
CPUClass *cc = CPU_CLASS(c);
175
175
DeviceClass *dc = DEVICE_CLASS(c);
176
176
177
-
mcc->parent_realize = dc->realize;
178
-
dc->realize = mips_cpu_realizefn;
179
-
177
+
device_class_set_parent_realize(dc, mips_cpu_realizefn,
178
+
&mcc->parent_realize);
180
179
mcc->parent_reset = cc->reset;
181
180
cc->reset = mips_cpu_reset;
182
181
+2
-3
target/moxie/cpu.c
+2
-3
target/moxie/cpu.c
···
102
102
CPUClass *cc = CPU_CLASS(oc);
103
103
MoxieCPUClass *mcc = MOXIE_CPU_CLASS(oc);
104
104
105
-
mcc->parent_realize = dc->realize;
106
-
dc->realize = moxie_cpu_realizefn;
107
-
105
+
device_class_set_parent_realize(dc, moxie_cpu_realizefn,
106
+
&mcc->parent_realize);
108
107
mcc->parent_reset = cc->reset;
109
108
cc->reset = moxie_cpu_reset;
110
109
+2
-2
target/nios2/cpu.c
+2
-2
target/nios2/cpu.c
···
187
187
CPUClass *cc = CPU_CLASS(oc);
188
188
Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
189
189
190
-
ncc->parent_realize = dc->realize;
191
-
dc->realize = nios2_cpu_realizefn;
190
+
device_class_set_parent_realize(dc, nios2_cpu_realizefn,
191
+
&ncc->parent_realize);
192
192
dc->props = nios2_properties;
193
193
ncc->parent_reset = cc->reset;
194
194
cc->reset = nios2_cpu_reset;
+2
-3
target/openrisc/cpu.c
+2
-3
target/openrisc/cpu.c
···
132
132
CPUClass *cc = CPU_CLASS(occ);
133
133
DeviceClass *dc = DEVICE_CLASS(oc);
134
134
135
-
occ->parent_realize = dc->realize;
136
-
dc->realize = openrisc_cpu_realizefn;
137
-
135
+
device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
136
+
&occ->parent_realize);
138
137
occ->parent_reset = cc->reset;
139
138
cc->reset = openrisc_cpu_reset;
140
139
+4
-4
target/ppc/translate_init.c
+4
-4
target/ppc/translate_init.c
···
10556
10556
CPUClass *cc = CPU_CLASS(oc);
10557
10557
DeviceClass *dc = DEVICE_CLASS(oc);
10558
10558
10559
-
pcc->parent_realize = dc->realize;
10560
-
pcc->parent_unrealize = dc->unrealize;
10559
+
device_class_set_parent_realize(dc, ppc_cpu_realizefn,
10560
+
&pcc->parent_realize);
10561
+
device_class_set_parent_unrealize(dc, ppc_cpu_unrealizefn,
10562
+
&pcc->parent_unrealize);
10561
10563
pcc->pvr_match = ppc_pvr_match_default;
10562
10564
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10563
-
dc->realize = ppc_cpu_realizefn;
10564
-
dc->unrealize = ppc_cpu_unrealizefn;
10565
10565
dc->props = ppc_cpu_properties;
10566
10566
10567
10567
pcc->parent_reset = cc->reset;
+2
-2
target/s390x/cpu.c
+2
-2
target/s390x/cpu.c
···
464
464
CPUClass *cc = CPU_CLASS(scc);
465
465
DeviceClass *dc = DEVICE_CLASS(oc);
466
466
467
-
scc->parent_realize = dc->realize;
468
-
dc->realize = s390_cpu_realizefn;
467
+
device_class_set_parent_realize(dc, s390_cpu_realizefn,
468
+
&scc->parent_realize);
469
469
dc->props = s390x_cpu_properties;
470
470
dc->user_creatable = true;
471
471
+2
-2
target/sh4/cpu.c
+2
-2
target/sh4/cpu.c
···
236
236
CPUClass *cc = CPU_CLASS(oc);
237
237
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
238
238
239
-
scc->parent_realize = dc->realize;
240
-
dc->realize = superh_cpu_realizefn;
239
+
device_class_set_parent_realize(dc, superh_cpu_realizefn,
240
+
&scc->parent_realize);
241
241
242
242
scc->parent_reset = cc->reset;
243
243
cc->reset = superh_cpu_reset;
+2
-2
target/sparc/cpu.c
+2
-2
target/sparc/cpu.c
···
858
858
CPUClass *cc = CPU_CLASS(oc);
859
859
DeviceClass *dc = DEVICE_CLASS(oc);
860
860
861
-
scc->parent_realize = dc->realize;
862
-
dc->realize = sparc_cpu_realizefn;
861
+
device_class_set_parent_realize(dc, sparc_cpu_realizefn,
862
+
&scc->parent_realize);
863
863
dc->props = sparc_cpu_properties;
864
864
865
865
scc->parent_reset = cc->reset;
+2
-2
target/tilegx/cpu.c
+2
-2
target/tilegx/cpu.c
···
141
141
CPUClass *cc = CPU_CLASS(oc);
142
142
TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
143
143
144
-
tcc->parent_realize = dc->realize;
145
-
dc->realize = tilegx_cpu_realizefn;
144
+
device_class_set_parent_realize(dc, tilegx_cpu_realizefn,
145
+
&tcc->parent_realize);
146
146
147
147
tcc->parent_reset = cc->reset;
148
148
cc->reset = tilegx_cpu_reset;
+2
-2
target/tricore/cpu.c
+2
-2
target/tricore/cpu.c
···
153
153
CPUClass *cc = CPU_CLASS(c);
154
154
DeviceClass *dc = DEVICE_CLASS(c);
155
155
156
-
mcc->parent_realize = dc->realize;
157
-
dc->realize = tricore_cpu_realizefn;
156
+
device_class_set_parent_realize(dc, tricore_cpu_realizefn,
157
+
&mcc->parent_realize);
158
158
159
159
mcc->parent_reset = cc->reset;
160
160
cc->reset = tricore_cpu_reset;
+2
-2
target/unicore32/cpu.c
+2
-2
target/unicore32/cpu.c
···
132
132
CPUClass *cc = CPU_CLASS(oc);
133
133
UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc);
134
134
135
-
ucc->parent_realize = dc->realize;
136
-
dc->realize = uc32_cpu_realizefn;
135
+
device_class_set_parent_realize(dc, uc32_cpu_realizefn,
136
+
&ucc->parent_realize);
137
137
138
138
cc->class_by_name = uc32_cpu_class_by_name;
139
139
cc->has_work = uc32_cpu_has_work;
+2
-2
target/xtensa/cpu.c
+2
-2
target/xtensa/cpu.c
···
151
151
CPUClass *cc = CPU_CLASS(oc);
152
152
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
153
153
154
-
xcc->parent_realize = dc->realize;
155
-
dc->realize = xtensa_cpu_realizefn;
154
+
device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
155
+
&xcc->parent_realize);
156
156
157
157
xcc->parent_reset = cc->reset;
158
158
cc->reset = xtensa_cpu_reset;