jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
aspeed/smc: Add some tracing
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200206112645.21275-2-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Cédric Le Goater
and committed by
Peter Maydell
bd6ce9a6
563152e0
+27
+1
Makefile.objs
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Makefile.objs
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hw/ssi/aspeed_smc.c
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hw/ssi/aspeed_smc.c
···
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "qemu/units.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
···
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s->ctrl->reg_to_segment(s, new, &seg);
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trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
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/* The start address of CS0 is read-only */
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if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
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qemu_log_mask(LOG_GUEST_ERROR,
···
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__func__, aspeed_smc_flash_mode(fl));
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}
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trace_aspeed_smc_flash_read(fl->id, addr, size, ret,
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aspeed_smc_flash_mode(fl));
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return ret;
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}
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···
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AspeedSMCState *s = fl->controller;
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uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
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trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies,
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(uint8_t) data & 0xff);
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if (s->snoop_index == SNOOP_OFF) {
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return false; /* Do nothing */
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···
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AspeedSMCState *s = fl->controller;
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int i;
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trace_aspeed_smc_flash_write(fl->id, addr, size, data,
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aspeed_smc_flash_mode(fl));
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if (!aspeed_smc_is_writable(fl)) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
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HWADDR_PRIx "\n", __func__, addr);
···
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(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
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(addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
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(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
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trace_aspeed_smc_read(addr, size, s->regs[addr]);
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return s->regs[addr];
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} else {
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qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
···
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__func__, s->regs[R_DMA_FLASH_ADDR]);
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return;
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}
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trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
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/*
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* When the DMA is on-going, the DMA registers are updated
···
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uint32_t value = data;
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addr >>= 2;
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trace_aspeed_smc_write(addr, size, data);
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if (addr == s->r_conf ||
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(addr >= s->r_timings &&
+9
hw/ssi/trace-events
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hw/ssi/trace-events
···
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# aspeed_smc.c
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aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_t end) "CS%d segreg=0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]"
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aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
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aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:0x%x dummies:%d data:0x%x"
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aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t data, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
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aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
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aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
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aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64