+2 -4

hw/arm/boot.c

··· 327 327 328 328 cmdline_size = strlen(info->kernel_cmdline); 329 329 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, 330 330 - (const uint8_t *)info->kernel_cmdline, 331 331 - cmdline_size + 1); 330 330 + info->kernel_cmdline, cmdline_size + 1); 332 331 cmdline_size = (cmdline_size >> 2) + 1; 333 332 WRITE_WORD(p, cmdline_size + 2); 334 333 WRITE_WORD(p, 0x54410009); ··· 420 419 } 421 420 s = info->kernel_cmdline; 422 421 if (s) { 423 423 - address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, 424 424 - (const uint8_t *)s, strlen(s) + 1); 422 422 + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); 425 423 } else { 426 424 WRITE_WORD(p, 0); 427 425 }

+2 -2

hw/dma/rc4030.c

··· 513 513 if (i < s->dma_tl_limit / sizeof(entry)) { 514 514 entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry); 515 515 if (address_space_read(ret.target_as, entry_address, 516 516 - MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry, 517 517 - sizeof(entry)) == MEMTX_OK) { 516 516 + MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry)) 517 517 + == MEMTX_OK) { 518 518 ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1); 519 519 ret.perm = IOMMU_RW; 520 520 }

+1 -1

hw/dma/xlnx-zdma.c

··· 364 364 } else { 365 365 addr = zdma_get_regaddr64(s, basereg); 366 366 addr += sizeof(s->dsc_dst); 367 367 - address_space_rw(s->dma_as, addr, s->attr, (void *) &next, 8, false); 367 367 + address_space_rw(s->dma_as, addr, s->attr, &next, 8, false); 368 368 zdma_put_regaddr64(s, basereg, next); 369 369 } 370 370 return next;

+9 -12

hw/net/cadence_gem.c

··· 871 871 872 872 /* read current descriptor */ 873 873 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 874 874 - (uint8_t *)s->rx_desc[q], 874 874 + s->rx_desc[q], 875 875 sizeof(uint32_t) * gem_get_desc_len(s, true)); 876 876 877 877 /* Descriptor owned by software ? */ ··· 1029 1029 1030 1030 /* Descriptor write-back. */ 1031 1031 desc_addr = gem_get_rx_desc_addr(s, q); 1032 1032 - address_space_write(&s->dma_as, desc_addr, 1033 1033 - MEMTXATTRS_UNSPECIFIED, 1034 1034 - (uint8_t *)s->rx_desc[q], 1032 1032 + address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1033 1033 + s->rx_desc[q], 1035 1034 sizeof(uint32_t) * gem_get_desc_len(s, true)); 1036 1035 1037 1036 /* Next descriptor */ ··· 1137 1136 1138 1137 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1139 1138 address_space_read(&s->dma_as, packet_desc_addr, 1140 1140 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, 1139 1139 + MEMTXATTRS_UNSPECIFIED, desc, 1141 1140 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1142 1141 /* Handle all descriptors owned by hardware */ 1143 1142 while (tx_desc_get_used(desc) == 0) { ··· 1185 1184 * the processor. 1186 1185 */ 1187 1186 address_space_read(&s->dma_as, desc_addr, 1188 1188 - MEMTXATTRS_UNSPECIFIED, 1189 1189 - (uint8_t *)desc_first, 1187 1187 + MEMTXATTRS_UNSPECIFIED, desc_first, 1190 1188 sizeof(desc_first)); 1191 1189 tx_desc_set_used(desc_first); 1192 1190 address_space_write(&s->dma_as, desc_addr, 1193 1193 - MEMTXATTRS_UNSPECIFIED, 1194 1194 - (uint8_t *)desc_first, 1195 1195 - sizeof(desc_first)); 1191 1191 + MEMTXATTRS_UNSPECIFIED, desc_first, 1192 1192 + sizeof(desc_first)); 1196 1193 /* Advance the hardware current descriptor past this packet */ 1197 1194 if (tx_desc_get_wrap(desc)) { 1198 1195 s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; ··· 1246 1243 } 1247 1244 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1248 1245 address_space_read(&s->dma_as, packet_desc_addr, 1249 1249 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, 1250 1250 - sizeof(uint32_t) * gem_get_desc_len(s, false)); 1246 1246 + MEMTXATTRS_UNSPECIFIED, desc, 1247 1247 + sizeof(uint32_t) * gem_get_desc_len(s, false)); 1251 1248 } 1252 1249 1253 1250 if (tx_desc_get_used(desc)) {

+14 -14

hw/net/dp8393x.c

··· 276 276 while (s->regs[SONIC_CDC] & 0x1f) { 277 277 /* Fill current entry */ 278 278 address_space_rw(&s->as, dp8393x_cdp(s), 279 279 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 279 279 + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); 280 280 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 281 281 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 282 282 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; ··· 294 294 295 295 /* Read CAM enable */ 296 296 address_space_rw(&s->as, dp8393x_cdp(s), 297 297 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 297 297 + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); 298 298 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 299 299 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 300 300 ··· 312 312 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 313 313 size = sizeof(uint16_t) * 4 * width; 314 314 address_space_rw(&s->as, dp8393x_rrp(s), 315 315 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 315 315 + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); 316 316 317 317 /* Update SONIC registers */ 318 318 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); ··· 427 427 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 428 428 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); 429 429 address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 430 430 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 430 430 + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); 431 431 tx_len = 0; 432 432 433 433 /* Update registers */ ··· 461 461 size = sizeof(uint16_t) * 3 * width; 462 462 address_space_rw(&s->as, 463 463 dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width, 464 464 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 464 464 + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); 465 465 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 466 466 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 467 467 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); ··· 495 495 s->regs[SONIC_TCR] & 0x0fff); /* status */ 496 496 size = sizeof(uint16_t) * width; 497 497 address_space_rw(&s->as, 498 498 - dp8393x_ttda(s), 499 499 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); 498 498 + dp8393x_ttda(s), 499 499 + MEMTXATTRS_UNSPECIFIED, s->data, size, 1); 500 500 501 501 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 502 502 /* Read footer of packet */ 503 503 size = sizeof(uint16_t) * width; 504 504 address_space_rw(&s->as, 505 505 - dp8393x_ttda(s) + 505 505 + dp8393x_ttda(s) + 506 506 sizeof(uint16_t) * 507 507 (4 + 3 * s->regs[SONIC_TFC]) * width, 508 508 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 508 508 + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); 509 509 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; 510 510 if (dp8393x_get(s, width, 0) & 0x1) { 511 511 /* EOL detected */ ··· 768 768 size = sizeof(uint16_t) * 1 * width; 769 769 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 770 770 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 771 771 - (uint8_t *)s->data, size, 0); 771 771 + s->data, size, 0); 772 772 if (dp8393x_get(s, width, 0) & 0x1) { 773 773 /* Still EOL ; stop reception */ 774 774 return -1; ··· 790 790 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, buf, rx_len); 791 791 address += rx_len; 792 792 address_space_rw(&s->as, address, 793 793 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); 793 793 + MEMTXATTRS_UNSPECIFIED, &checksum, 4, 1); 794 794 rx_len += 4; 795 795 s->regs[SONIC_CRBA1] = address >> 16; 796 796 s->regs[SONIC_CRBA0] = address & 0xffff; ··· 819 819 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 820 820 size = sizeof(uint16_t) * 5 * width; 821 821 address_space_rw(&s->as, dp8393x_crda(s), 822 822 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); 822 822 + MEMTXATTRS_UNSPECIFIED, s->data, size, 1); 823 823 824 824 /* Move to next descriptor */ 825 825 size = sizeof(uint16_t) * width; 826 826 address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 827 827 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); 827 827 + MEMTXATTRS_UNSPECIFIED, s->data, size, 0); 828 828 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 829 829 if (s->regs[SONIC_LLFA] & 0x1) { 830 830 /* EOL detected */ ··· 838 838 } 839 839 s->data[0] = 0; 840 840 address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED, 841 841 - (uint8_t *)s->data, sizeof(uint16_t), 1); 841 841 + s->data, sizeof(uint16_t), 1); 842 842 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 843 843 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 844 844 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);

+2 -2

hw/s390x/css.c

··· 875 875 return -EINVAL; /* channel program check */ 876 876 } 877 877 ret = address_space_rw(&address_space_memory, idaw_addr, 878 878 - MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2, 878 878 + MEMTXATTRS_UNSPECIFIED, &idaw.fmt2, 879 879 sizeof(idaw.fmt2), false); 880 880 cds->cda = be64_to_cpu(idaw.fmt2); 881 881 } else { ··· 884 884 return -EINVAL; /* channel program check */ 885 885 } 886 886 ret = address_space_rw(&address_space_memory, idaw_addr, 887 887 - MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1, 887 887 + MEMTXATTRS_UNSPECIFIED, &idaw.fmt1, 888 888 sizeof(idaw.fmt1), false); 889 889 cds->cda = be64_to_cpu(idaw.fmt1); 890 890 if (cds->cda & 0x80000000) {

+6 -6

qtest.c

··· 435 435 uint16_t data = value; 436 436 tswap16s(&data); 437 437 address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, 438 438 - (uint8_t *) &data, 2, true); 438 438 + &data, 2, true); 439 439 } else if (words[0][5] == 'l') { 440 440 uint32_t data = value; 441 441 tswap32s(&data); 442 442 address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, 443 443 - (uint8_t *) &data, 4, true); 443 443 + &data, 4, true); 444 444 } else if (words[0][5] == 'q') { 445 445 uint64_t data = value; 446 446 tswap64s(&data); 447 447 address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, 448 448 - (uint8_t *) &data, 8, true); 448 448 + &data, 8, true); 449 449 } 450 450 qtest_send_prefix(chr); 451 451 qtest_send(chr, "OK\n"); ··· 469 469 } else if (words[0][4] == 'w') { 470 470 uint16_t data; 471 471 address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, 472 472 - (uint8_t *) &data, 2, false); 472 472 + &data, 2, false); 473 473 value = tswap16(data); 474 474 } else if (words[0][4] == 'l') { 475 475 uint32_t data; 476 476 address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, 477 477 - (uint8_t *) &data, 4, false); 477 477 + &data, 4, false); 478 478 value = tswap32(data); 479 479 } else if (words[0][4] == 'q') { 480 480 address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, 481 481 - (uint8_t *) &value, 8, false); 481 481 + &value, 8, false); 482 482 tswap64s(&value); 483 483 } 484 484 qtest_send_prefix(chr);

+14 -1

scripts/coccinelle/exec_rw_const.cocci

··· 25 25 26 26 // Remove useless cast 27 27 @@ 28 28 - expression E1, E2, E3, E4; 28 28 + expression E1, E2, E3, E4, E5, E6; 29 29 type T; 30 30 @@ 31 31 ( 32 32 + - address_space_rw(E1, E2, E3, (T *)(E4), E5, E6) 33 33 + + address_space_rw(E1, E2, E3, E4, E5, E6) 34 34 + | 35 35 + - address_space_read(E1, E2, E3, (T *)(E4), E5) 36 36 + + address_space_read(E1, E2, E3, E4, E5) 37 37 + | 38 38 + - address_space_write(E1, E2, E3, (T *)(E4), E5) 39 39 + + address_space_write(E1, E2, E3, E4, E5) 40 40 + | 41 41 + - address_space_write_rom(E1, E2, E3, (T *)(E4), E5) 42 42 + + address_space_write_rom(E1, E2, E3, E4, E5) 43 43 + | 44 44 + 32 45 - dma_memory_read(E1, E2, (T *)(E3), E4) 33 46 + dma_memory_read(E1, E2, E3, E4) 34 47 |

+1 -1

target/i386/hvf/vmx.h

··· 128 128 address_space_rw(&address_space_memory, 129 129 rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, 130 130 MEMTXATTRS_UNSPECIFIED, 131 131 - (uint8_t *)pdpte, 32, 0); 131 131 + pdpte, 32, 0); 132 132 /* Only set PDPTE when appropriate. */ 133 133 for (i = 0; i < 4; i++) { 134 134 wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);

+1 -1

target/i386/hvf/x86_mmu.c

··· 89 89 90 90 index = gpt_entry(pt->gva, level, pae); 91 91 address_space_rw(&address_space_memory, gpa + index * pte_size(pae), 92 92 - MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0); 92 92 + MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae), 0); 93 93 94 94 pt->pte[level - 1] = pte; 95 95

+1 -1

target/i386/whpx-all.c

··· 540 540 { 541 541 MemTxAttrs attrs = { 0 }; 542 542 address_space_rw(&address_space_io, IoAccess->Port, attrs, 543 543 - (uint8_t *)&IoAccess->Data, IoAccess->AccessSize, 543 543 + &IoAccess->Data, IoAccess->AccessSize, 544 544 IoAccess->Direction); 545 545 return S_OK; 546 546 }

+1 -1

target/s390x/mmu_helper.c

··· 106 106 * We treat them as absolute addresses and don't wrap them. 107 107 */ 108 108 if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED, 109 109 - (uint8_t *)entry, sizeof(*entry)) != 109 109 + entry, sizeof(*entry)) != 110 110 MEMTX_OK)) { 111 111 return false; 112 112 }