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qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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target/i386: Enable TSX Suspend Load Address Tracking feature

This instruction aims to give a way to choose which memory accesses
do not need to be tracked in the TSX read set, which is defined as
CPUID.(EAX=7,ECX=0):EDX[bit 16].

The release spec link is as follows:
https://software.intel.com/content/dam/develop/public/us/en/documents/\
architecture-instruction-set-extensions-programming-reference.pdf

The associated kvm patch link is as follows:
https://lore.kernel.org/patchwork/patch/1268026/

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Message-Id: <1593991036-12183-3-git-send-email-cathy.zhang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

authored by

Cathy Zhang and committed by
Paolo Bonzini b3c7344e 5dd13f2a

+3 -1
+1 -1
target/i386/cpu.c
··· 987 987 NULL, NULL, NULL, NULL, 988 988 "avx512-vp2intersect", NULL, "md-clear", NULL, 989 989 NULL, NULL, "serialize", NULL, 990 - NULL, NULL, NULL /* pconfig */, NULL, 990 + "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, 991 991 NULL, NULL, NULL, NULL, 992 992 NULL, NULL, "spec-ctrl", "stibp", 993 993 NULL, "arch-capabilities", "core-capability", "ssbd",
+2
target/i386/cpu.h
··· 779 779 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) 780 780 /* SERIALIZE instruction */ 781 781 #define CPUID_7_0_EDX_SERIALIZE (1U << 14) 782 + /* TSX Suspend Load Address Tracking instruction */ 783 + #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) 782 784 /* Speculation Control */ 783 785 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) 784 786 /* Single Thread Indirect Branch Predictors */