-3

.gitmodules

··· 10 10 [submodule "roms/openbios"] 11 11 path = roms/openbios 12 12 url = https://git.qemu.org/git/openbios.git 13 13 - [submodule "roms/openhackware"] 14 14 - path = roms/openhackware 15 15 - url = https://git.qemu.org/git/openhackware.git 16 13 [submodule "roms/qemu-palcode"] 17 14 path = roms/qemu-palcode 18 15 url = https://git.qemu.org/git/qemu-palcode.git

-1

MAINTAINERS

··· 1103 1103 F: hw/rtc/m48t59-isa.c 1104 1104 F: include/hw/isa/pc87312.h 1105 1105 F: include/hw/rtc/m48t59.h 1106 1106 - F: pc-bios/ppc_rom.bin 1107 1106 F: tests/acceptance/ppc_prep_40p.py 1108 1107 1109 1108 sPAPR

+1 -1

Makefile

··· 784 784 BLOBS=bios.bin bios-256k.bin bios-microvm.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \ 785 785 vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin vgabios-virtio.bin \ 786 786 vgabios-ramfb.bin vgabios-bochs-display.bin vgabios-ati.bin \ 787 787 - ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \ 787 787 + openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \ 788 788 pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \ 789 789 pxe-pcnet.rom pxe-rtl8139.rom pxe-virtio.rom \ 790 790 efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \

+1 -2

docs/interop/firmware.json

··· 27 27 # 28 28 # @openfirmware: The interface is defined by the (historical) IEEE 29 29 # 1275-1994 standard. Examples for firmware projects that 30 30 - # provide this interface are: OpenBIOS, OpenHackWare, 31 31 - # SLOF. 30 30 + # provide this interface are: OpenBIOS and SLOF. 32 31 # 33 32 # @uboot: Firmware interface defined by the U-Boot project. 34 33 #

-18

hw/ppc/ppc.c

··· 1490 1490 } 1491 1491 1492 1492 /*****************************************************************************/ 1493 1493 - /* Debug port */ 1494 1494 - void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) 1495 1495 - { 1496 1496 - addr &= 0xF; 1497 1497 - switch (addr) { 1498 1498 - case 0: 1499 1499 - printf("%c", val); 1500 1500 - break; 1501 1501 - case 1: 1502 1502 - printf("\n"); 1503 1503 - fflush(stdout); 1504 1504 - break; 1505 1505 - case 2: 1506 1506 - printf("Set loglevel to %04" PRIx32 "\n", val); 1507 1507 - qemu_set_log(val | 0x100); 1508 1508 - break; 1509 1509 - } 1510 1510 - } 1511 1493 1512 1494 int ppc_cpu_pir(PowerPCCPU *cpu) 1513 1495 {

+1 -383

hw/ppc/prep.c

··· 42 42 #include "hw/loader.h" 43 43 #include "hw/rtc/mc146818rtc.h" 44 44 #include "hw/isa/pc87312.h" 45 45 - #include "hw/net/ne2000-isa.h" 45 45 + #include "hw/qdev-properties.h" 46 46 #include "sysemu/arch_init.h" 47 47 #include "sysemu/kvm.h" 48 48 #include "sysemu/qtest.h" ··· 60 60 61 61 #define CFG_ADDR 0xf0000510 62 62 63 63 - #define BIOS_SIZE (1 * MiB) 64 64 - #define BIOS_FILENAME "ppc_rom.bin" 65 63 #define KERNEL_LOAD_ADDR 0x01000000 66 64 #define INITRD_LOAD_ADDR 0x01800000 67 65 68 68 - /* Constants for devices init */ 69 69 - static const int ide_iobase[2] = { 0x1f0, 0x170 }; 70 70 - static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 71 71 - static const int ide_irq[2] = { 13, 13 }; 72 72 - 73 73 - #define NE2000_NB_MAX 6 74 74 - 75 75 - static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 76 76 - static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 77 77 - 78 78 - /* ISA IO ports bridge */ 79 79 - #define PPC_IO_BASE 0x80000000 80 80 - 81 81 - /* Fake super-io ports for PREP platform (Intel 82378ZB) */ 82 82 - typedef struct sysctrl_t { 83 83 - qemu_irq reset_irq; 84 84 - Nvram *nvram; 85 85 - uint8_t state; 86 86 - uint8_t syscontrol; 87 87 - int contiguous_map; 88 88 - qemu_irq contiguous_map_irq; 89 89 - int endian; 90 90 - } sysctrl_t; 91 91 - 92 92 - enum { 93 93 - STATE_HARDFILE = 0x01, 94 94 - }; 95 95 - 96 96 - static sysctrl_t *sysctrl; 97 97 - 98 98 - static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 99 99 - { 100 100 - sysctrl_t *sysctrl = opaque; 101 101 - 102 102 - trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); 103 103 - switch (addr) { 104 104 - case 0x0092: 105 105 - /* Special port 92 */ 106 106 - /* Check soft reset asked */ 107 107 - if (val & 0x01) { 108 108 - qemu_irq_raise(sysctrl->reset_irq); 109 109 - } else { 110 110 - qemu_irq_lower(sysctrl->reset_irq); 111 111 - } 112 112 - /* Check LE mode */ 113 113 - if (val & 0x02) { 114 114 - sysctrl->endian = 1; 115 115 - } else { 116 116 - sysctrl->endian = 0; 117 117 - } 118 118 - break; 119 119 - case 0x0800: 120 120 - /* Motorola CPU configuration register : read-only */ 121 121 - break; 122 122 - case 0x0802: 123 123 - /* Motorola base module feature register : read-only */ 124 124 - break; 125 125 - case 0x0803: 126 126 - /* Motorola base module status register : read-only */ 127 127 - break; 128 128 - case 0x0808: 129 129 - /* Hardfile light register */ 130 130 - if (val & 1) 131 131 - sysctrl->state |= STATE_HARDFILE; 132 132 - else 133 133 - sysctrl->state &= ~STATE_HARDFILE; 134 134 - break; 135 135 - case 0x0810: 136 136 - /* Password protect 1 register */ 137 137 - if (sysctrl->nvram != NULL) { 138 138 - NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 139 139 - (k->toggle_lock)(sysctrl->nvram, 1); 140 140 - } 141 141 - break; 142 142 - case 0x0812: 143 143 - /* Password protect 2 register */ 144 144 - if (sysctrl->nvram != NULL) { 145 145 - NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 146 146 - (k->toggle_lock)(sysctrl->nvram, 2); 147 147 - } 148 148 - break; 149 149 - case 0x0814: 150 150 - /* L2 invalidate register */ 151 151 - // tlb_flush(first_cpu, 1); 152 152 - break; 153 153 - case 0x081C: 154 154 - /* system control register */ 155 155 - sysctrl->syscontrol = val & 0x0F; 156 156 - break; 157 157 - case 0x0850: 158 158 - /* I/O map type register */ 159 159 - sysctrl->contiguous_map = val & 0x01; 160 160 - qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); 161 161 - break; 162 162 - default: 163 163 - printf("ERROR: unaffected IO port write: %04" PRIx32 164 164 - " => %02" PRIx32"\n", addr, val); 165 165 - break; 166 166 - } 167 167 - } 168 168 - 169 169 - static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 170 170 - { 171 171 - sysctrl_t *sysctrl = opaque; 172 172 - uint32_t retval = 0xFF; 173 173 - 174 174 - switch (addr) { 175 175 - case 0x0092: 176 176 - /* Special port 92 */ 177 177 - retval = sysctrl->endian << 1; 178 178 - break; 179 179 - case 0x0800: 180 180 - /* Motorola CPU configuration register */ 181 181 - retval = 0xEF; /* MPC750 */ 182 182 - break; 183 183 - case 0x0802: 184 184 - /* Motorola Base module feature register */ 185 185 - retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ 186 186 - break; 187 187 - case 0x0803: 188 188 - /* Motorola base module status register */ 189 189 - retval = 0xE0; /* Standard MPC750 */ 190 190 - break; 191 191 - case 0x080C: 192 192 - /* Equipment present register: 193 193 - * no L2 cache 194 194 - * no upgrade processor 195 195 - * no cards in PCI slots 196 196 - * SCSI fuse is bad 197 197 - */ 198 198 - retval = 0x3C; 199 199 - break; 200 200 - case 0x0810: 201 201 - /* Motorola base module extended feature register */ 202 202 - retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ 203 203 - break; 204 204 - case 0x0814: 205 205 - /* L2 invalidate: don't care */ 206 206 - break; 207 207 - case 0x0818: 208 208 - /* Keylock */ 209 209 - retval = 0x00; 210 210 - break; 211 211 - case 0x081C: 212 212 - /* system control register 213 213 - * 7 - 6 / 1 - 0: L2 cache enable 214 214 - */ 215 215 - retval = sysctrl->syscontrol; 216 216 - break; 217 217 - case 0x0823: 218 218 - /* */ 219 219 - retval = 0x03; /* no L2 cache */ 220 220 - break; 221 221 - case 0x0850: 222 222 - /* I/O map type register */ 223 223 - retval = sysctrl->contiguous_map; 224 224 - break; 225 225 - default: 226 226 - printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); 227 227 - break; 228 228 - } 229 229 - trace_prep_io_800_readb(addr - PPC_IO_BASE, retval); 230 230 - 231 231 - return retval; 232 232 - } 233 233 - 234 234 - 235 66 #define NVRAM_SIZE 0x2000 236 67 237 68 static void fw_cfg_boot_set(void *opaque, const char *boot_device, ··· 247 78 cpu_reset(CPU(cpu)); 248 79 } 249 80 250 250 - static const MemoryRegionPortio prep_portio_list[] = { 251 251 - /* System control ports */ 252 252 - { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 253 253 - { 0x0800, 0x52, 1, 254 254 - .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 255 255 - /* Special port to get debug messages from Open-Firmware */ 256 256 - { 0x0F00, 4, 1, .write = PPC_debug_write, }, 257 257 - PORTIO_END_OF_LIST(), 258 258 - }; 259 259 - 260 260 - static PortioList prep_port_list; 261 81 262 82 /*****************************************************************************/ 263 83 /* NVRAM helpers */ ··· 397 217 return 0; 398 218 } 399 219 400 400 - /* PowerPC PREP hardware initialisation */ 401 401 - static void ppc_prep_init(MachineState *machine) 402 402 - { 403 403 - ram_addr_t ram_size = machine->ram_size; 404 404 - const char *kernel_filename = machine->kernel_filename; 405 405 - const char *kernel_cmdline = machine->kernel_cmdline; 406 406 - const char *initrd_filename = machine->initrd_filename; 407 407 - const char *boot_device = machine->boot_order; 408 408 - MemoryRegion *sysmem = get_system_memory(); 409 409 - PowerPCCPU *cpu = NULL; 410 410 - CPUPPCState *env = NULL; 411 411 - Nvram *m48t59; 412 412 - #if 0 413 413 - MemoryRegion *xcsr = g_new(MemoryRegion, 1); 414 414 - #endif 415 415 - int linux_boot, i, nb_nics1; 416 416 - MemoryRegion *ram = g_new(MemoryRegion, 1); 417 417 - uint32_t kernel_base, initrd_base; 418 418 - long kernel_size, initrd_size; 419 419 - DeviceState *dev; 420 420 - PCIHostState *pcihost; 421 421 - PCIBus *pci_bus; 422 422 - PCIDevice *pci; 423 423 - ISABus *isa_bus; 424 424 - ISADevice *isa; 425 425 - int ppc_boot_device; 426 426 - DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 427 427 - 428 428 - sysctrl = g_malloc0(sizeof(sysctrl_t)); 429 429 - 430 430 - linux_boot = (kernel_filename != NULL); 431 431 - 432 432 - /* init CPUs */ 433 433 - for (i = 0; i < machine->smp.cpus; i++) { 434 434 - cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 435 435 - env = &cpu->env; 436 436 - 437 437 - if (env->flags & POWERPC_FLAG_RTC_CLK) { 438 438 - /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 439 439 - cpu_ppc_tb_init(env, 7812500UL); 440 440 - } else { 441 441 - /* Set time-base frequency to 100 Mhz */ 442 442 - cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 443 443 - } 444 444 - qemu_register_reset(ppc_prep_reset, cpu); 445 445 - } 446 446 - 447 447 - /* allocate RAM */ 448 448 - memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size); 449 449 - memory_region_add_subregion(sysmem, 0, ram); 450 450 - 451 451 - if (linux_boot) { 452 452 - kernel_base = KERNEL_LOAD_ADDR; 453 453 - /* now we can load the kernel */ 454 454 - kernel_size = load_image_targphys(kernel_filename, kernel_base, 455 455 - ram_size - kernel_base); 456 456 - if (kernel_size < 0) { 457 457 - error_report("could not load kernel '%s'", kernel_filename); 458 458 - exit(1); 459 459 - } 460 460 - /* load initrd */ 461 461 - if (initrd_filename) { 462 462 - initrd_base = INITRD_LOAD_ADDR; 463 463 - initrd_size = load_image_targphys(initrd_filename, initrd_base, 464 464 - ram_size - initrd_base); 465 465 - if (initrd_size < 0) { 466 466 - error_report("could not load initial ram disk '%s'", 467 467 - initrd_filename); 468 468 - exit(1); 469 469 - } 470 470 - } else { 471 471 - initrd_base = 0; 472 472 - initrd_size = 0; 473 473 - } 474 474 - ppc_boot_device = 'm'; 475 475 - } else { 476 476 - kernel_base = 0; 477 477 - kernel_size = 0; 478 478 - initrd_base = 0; 479 479 - initrd_size = 0; 480 480 - ppc_boot_device = '\0'; 481 481 - /* For now, OHW cannot boot from the network. */ 482 482 - for (i = 0; boot_device[i] != '\0'; i++) { 483 483 - if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 484 484 - ppc_boot_device = boot_device[i]; 485 485 - break; 486 486 - } 487 487 - } 488 488 - if (ppc_boot_device == '\0') { 489 489 - error_report("No valid boot device for Mac99 machine"); 490 490 - exit(1); 491 491 - } 492 492 - } 493 493 - 494 494 - if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 495 495 - error_report("Only 6xx bus is supported on PREP machine"); 496 496 - exit(1); 497 497 - } 498 498 - 499 499 - dev = qdev_create(NULL, "raven-pcihost"); 500 500 - if (bios_name == NULL) { 501 501 - bios_name = BIOS_FILENAME; 502 502 - } 503 503 - qdev_prop_set_string(dev, "bios-name", bios_name); 504 504 - qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 505 505 - qdev_prop_set_bit(dev, "is-legacy-prep", true); 506 506 - pcihost = PCI_HOST_BRIDGE(dev); 507 507 - object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 508 508 - qdev_init_nofail(dev); 509 509 - pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 510 510 - if (pci_bus == NULL) { 511 511 - error_report("Couldn't create PCI host controller"); 512 512 - exit(1); 513 513 - } 514 514 - sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); 515 515 - 516 516 - /* PCI -> ISA bridge */ 517 517 - pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); 518 518 - cpu = POWERPC_CPU(first_cpu); 519 519 - qdev_connect_gpio_out(&pci->qdev, 0, 520 520 - cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 521 521 - sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); 522 522 - sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); 523 523 - sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); 524 524 - sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); 525 525 - isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0")); 526 526 - 527 527 - /* Super I/O (parallel + serial ports) */ 528 528 - isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO); 529 529 - dev = DEVICE(isa); 530 530 - qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ 531 531 - qdev_init_nofail(dev); 532 532 - 533 533 - /* init basic PC hardware */ 534 534 - pci_vga_init(pci_bus); 535 535 - 536 536 - nb_nics1 = nb_nics; 537 537 - if (nb_nics1 > NE2000_NB_MAX) 538 538 - nb_nics1 = NE2000_NB_MAX; 539 539 - for(i = 0; i < nb_nics1; i++) { 540 540 - if (nd_table[i].model == NULL) { 541 541 - nd_table[i].model = g_strdup("ne2k_isa"); 542 542 - } 543 543 - if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { 544 544 - isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], 545 545 - &nd_table[i]); 546 546 - } else { 547 547 - pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 548 548 - } 549 549 - } 550 550 - 551 551 - ide_drive_get(hd, ARRAY_SIZE(hd)); 552 552 - for(i = 0; i < MAX_IDE_BUS; i++) { 553 553 - isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], 554 554 - hd[2 * i], 555 555 - hd[2 * i + 1]); 556 556 - } 557 557 - 558 558 - cpu = POWERPC_CPU(first_cpu); 559 559 - sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 560 560 - 561 561 - portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); 562 562 - portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); 563 563 - 564 564 - /* 565 565 - * PowerPC control and status register group: unimplemented, 566 566 - * would be at address 0xFEFF0000. 567 567 - */ 568 568 - 569 569 - if (machine_usb(machine)) { 570 570 - pci_create_simple(pci_bus, -1, "pci-ohci"); 571 571 - } 572 572 - 573 573 - m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59); 574 574 - if (m48t59 == NULL) 575 575 - return; 576 576 - sysctrl->nvram = m48t59; 577 577 - 578 578 - /* Initialise NVRAM */ 579 579 - PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 580 580 - ppc_boot_device, 581 581 - kernel_base, kernel_size, 582 582 - kernel_cmdline, 583 583 - initrd_base, initrd_size, 584 584 - /* XXX: need an option to load a NVRAM image */ 585 585 - 0, 586 586 - graphic_width, graphic_height, graphic_depth); 587 587 - } 588 588 - 589 589 - static void prep_machine_init(MachineClass *mc) 590 590 - { 591 591 - mc->deprecation_reason = "use 40p machine type instead"; 592 592 - mc->desc = "PowerPC PREP platform"; 593 593 - mc->init = ppc_prep_init; 594 594 - mc->block_default_type = IF_IDE; 595 595 - mc->max_cpus = MAX_CPUS; 596 596 - mc->default_boot_order = "cad"; 597 597 - mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602"); 598 598 - mc->default_display = "std"; 599 599 - } 600 600 - 601 220 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) 602 221 { 603 222 uint16_t checksum = *(uint16_t *)opaque; ··· 821 440 } 822 441 823 442 DEFINE_MACHINE("40p", ibm_40p_machine_init) 824 824 - DEFINE_MACHINE("prep", prep_machine_init)

-1

include/hw/ppc/ppc.h

··· 68 68 void ppc40x_core_reset(PowerPCCPU *cpu); 69 69 void ppc40x_chip_reset(PowerPCCPU *cpu); 70 70 void ppc40x_system_reset(PowerPCCPU *cpu); 71 71 - void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); 72 71 73 72 #if defined(CONFIG_USER_ONLY) 74 73 static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}

-3

pc-bios/README

··· 4 4 - The VGA BIOS and the Cirrus VGA BIOS come from the LGPL VGA bios 5 5 project (http://www.nongnu.org/vgabios/). 6 6 7 7 - - The PowerPC Open Hack'Ware Open Firmware Compatible BIOS is 8 8 - available at https://repo.or.cz/openhackware.git. 9 9 - 10 7 - OpenBIOS (http://www.openbios.org/) is a free (GPL v2) portable 11 8 firmware implementation. The goal is to implement a 100% IEEE 12 9 1275-1994 (referred to as Open Firmware) compliant firmware.

pc-bios/ppc_rom.bin

This is a binary file and will not be displayed.

-6

qemu-deprecated.texi

··· 270 270 These machine types are very old and likely can not be used for live migration 271 271 from old QEMU versions anymore. A newer machine type should be used instead. 272 272 273 273 - @subsection prep (PowerPC) (since 3.1) 274 274 - 275 275 - This machine type uses an unmaintained firmware, broken in lots of ways, 276 276 - and unable to start post-2004 operating systems. 40p machine type should be 277 277 - used instead. 278 278 - 279 273 @subsection spike_v1.9.1 and spike_v1.10 (since 4.1) 280 274 281 275 The version specific Spike machines have been deprecated in favour of the

+5 -10

qemu-doc.texi

··· 1729 1729 @section PowerPC System emulator 1730 1730 @cindex system emulation (PowerPC) 1731 1731 1732 1732 - Use the executable @file{qemu-system-ppc} to simulate a complete PREP 1732 1732 + Use the executable @file{qemu-system-ppc} to simulate a complete 40P (PREP) 1733 1733 or PowerMac PowerPC system. 1734 1734 1735 1735 QEMU emulates the following PowerMac peripherals: ··· 1749 1749 VIA-CUDA with ADB keyboard and mouse. 1750 1750 @end itemize 1751 1751 1752 1752 - QEMU emulates the following PREP peripherals: 1752 1752 + QEMU emulates the following 40P (PREP) peripherals: 1753 1753 1754 1754 @itemize @minus 1755 1755 @item ··· 1761 1761 @item 1762 1762 Floppy disk 1763 1763 @item 1764 1764 - NE2000 network adapters 1764 1764 + PCnet network adapters 1765 1765 @item 1766 1766 Serial port 1767 1767 @item ··· 1770 1770 PC compatible keyboard and mouse. 1771 1771 @end itemize 1772 1772 1773 1773 - QEMU uses the Open Hack'Ware Open Firmware Compatible BIOS available at 1774 1774 - @url{http://perso.magic.fr/l_indien/OpenHackWare/index.htm}. 1775 1775 - 1776 1773 Since version 0.9.1, QEMU uses OpenBIOS @url{https://www.openbios.org/} 1777 1777 - for the g3beige and mac99 PowerMac machines. OpenBIOS is a free (GPL 1778 1778 - v2) portable firmware implementation. The goal is to implement a 100% 1774 1774 + for the g3beige and mac99 PowerMac and the 40p machines. OpenBIOS is a free 1775 1775 + (GPL v2) portable firmware implementation. The goal is to implement a 100% 1779 1776 IEEE 1275-1994 (referred to as Open Firmware) compliant firmware. 1780 1777 1781 1778 @c man begin OPTIONS ··· 1797 1794 -prom-env 'boot-device=hd:2,\yaboot' \ 1798 1795 -prom-env 'boot-args=conf=hd:2,\yaboot.conf' 1799 1796 @end example 1800 1800 - 1801 1801 - These variables are not used by Open Hack'Ware. 1802 1797 1803 1798 @end table 1804 1799

-25

tests/qtest/boot-order-test.c

··· 108 108 test_boot_orders(NULL, read_boot_order_pc, test_cases_pc); 109 109 } 110 110 111 111 - static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t reg) 112 112 - { 113 113 - qtest_writeb(qts, addr, reg & 0xff); 114 114 - qtest_writeb(qts, addr + 1, reg >> 8); 115 115 - return qtest_readb(qts, addr + 3); 116 116 - } 117 117 - 118 118 - static uint64_t read_boot_order_prep(QTestState *qts) 119 119 - { 120 120 - return read_m48t59(qts, 0x80000000 + 0x74, 0x34); 121 121 - } 122 122 - 123 123 - static const boot_order_test test_cases_prep[] = { 124 124 - { "", 'c', 'c' }, 125 125 - { "-boot c", 'c', 'c' }, 126 126 - { "-boot d", 'd', 'd' }, 127 127 - {} 128 128 - }; 129 129 - 130 130 - static void test_prep_boot_order(void) 131 131 - { 132 132 - test_boot_orders("prep", read_boot_order_prep, test_cases_prep); 133 133 - } 134 134 - 135 111 static uint64_t read_boot_order_pmac(QTestState *qts) 136 112 { 137 113 QFWCFG *fw_cfg = mm_fw_cfg_init(qts, 0xf0000510); ··· 190 166 if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { 191 167 qtest_add_func("boot-order/pc", test_pc_boot_order); 192 168 } else if (strcmp(arch, "ppc") == 0 || strcmp(arch, "ppc64") == 0) { 193 193 - qtest_add_func("boot-order/prep", test_prep_boot_order); 194 169 qtest_add_func("boot-order/pmac_oldworld", 195 170 test_pmac_oldworld_boot_order); 196 171 qtest_add_func("boot-order/pmac_newworld",

+1 -1

tests/qtest/cdrom-test.c

··· 189 189 add_s390x_tests(); 190 190 } else if (g_str_equal(arch, "ppc64")) { 191 191 const char *ppcmachines[] = { 192 192 - "pseries", "mac99", "g3beige", "40p", "prep", NULL 192 192 + "pseries", "mac99", "g3beige", "40p", NULL 193 193 }; 194 194 add_cdrom_param_tests(ppcmachines); 195 195 } else if (g_str_equal(arch, "sparc")) {

+1 -1

tests/qtest/endianness-test.c

··· 35 35 { "mips64", "malta", 0x10000000, .bswap = true }, 36 36 { "mips64el", "fulong2e", 0x1fd00000 }, 37 37 { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio = "i82378" }, 38 38 - { "ppc", "prep", 0x80000000, .bswap = true }, 38 38 + { "ppc", "40p", 0x80000000, .bswap = true }, 39 39 { "ppc", "bamboo", 0xe8000000, .bswap = true, .superio = "i82378" }, 40 40 { "ppc64", "mac99", 0xf2000000, .bswap = true, .superio = "i82378" }, 41 41 { "ppc64", "pseries", (1ULL << 45), .bswap = true, .superio = "i82378" },