jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/mips/gt64xxx: Remove dynamic field width from trace events
Since not all trace backends support dynamic field width in
format (dtrace via stap does not), replace by a static field
width instead.
We previously passed to the trace API 'width << 1' as the number
of hex characters to display (the dynamic field width). We don't
need this anymore. Instead, display the size of bytes accessed.
Fixes: ab6bff424f ("gt64xxx_pci: Convert debug printf to trace events")
Reported-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Buglink: https://bugs.launchpad.net/qemu/+bug/1844817
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+10
-10
+8
-8
hw/mips/gt64xxx_pci.c
+8
-8
hw/mips/gt64xxx_pci.c
···
642
642
/* not really implemented */
643
643
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
644
644
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
645
-
trace_gt64120_write("INTRCAUSE", size << 1, val);
645
+
trace_gt64120_write("INTRCAUSE", size, val);
646
646
break;
647
647
case GT_INTRMASK:
648
648
s->regs[saddr] = val & 0x3c3ffffe;
649
-
trace_gt64120_write("INTRMASK", size << 1, val);
649
+
trace_gt64120_write("INTRMASK", size, val);
650
650
break;
651
651
case GT_PCI0_ICMASK:
652
652
s->regs[saddr] = val & 0x03fffffe;
653
-
trace_gt64120_write("ICMASK", size << 1, val);
653
+
trace_gt64120_write("ICMASK", size, val);
654
654
break;
655
655
case GT_PCI0_SERR0MASK:
656
656
s->regs[saddr] = val & 0x0000003f;
657
-
trace_gt64120_write("SERR0MASK", size << 1, val);
657
+
trace_gt64120_write("SERR0MASK", size, val);
658
658
break;
659
659
660
660
/* Reserved when only PCI_0 is configured. */
···
930
930
/* Interrupts */
931
931
case GT_INTRCAUSE:
932
932
val = s->regs[saddr];
933
-
trace_gt64120_read("INTRCAUSE", size << 1, val);
933
+
trace_gt64120_read("INTRCAUSE", size, val);
934
934
break;
935
935
case GT_INTRMASK:
936
936
val = s->regs[saddr];
937
-
trace_gt64120_read("INTRMASK", size << 1, val);
937
+
trace_gt64120_read("INTRMASK", size, val);
938
938
break;
939
939
case GT_PCI0_ICMASK:
940
940
val = s->regs[saddr];
941
-
trace_gt64120_read("ICMASK", size << 1, val);
941
+
trace_gt64120_read("ICMASK", size, val);
942
942
break;
943
943
case GT_PCI0_SERR0MASK:
944
944
val = s->regs[saddr];
945
-
trace_gt64120_read("SERR0MASK", size << 1, val);
945
+
trace_gt64120_read("SERR0MASK", size, val);
946
946
break;
947
947
948
948
/* Reserved when only PCI_0 is configured. */
+2
-2
hw/mips/trace-events
+2
-2
hw/mips/trace-events
···
1
1
# gt64xxx.c
2
-
gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64
3
-
gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64
2
+
gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
3
+
gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
4
4
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64