target/riscv: Expose "priv" register for GDB for reads

qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

This patch enables a debugger to read the current privilege level via a virtual
"priv" register. When compiled with CONFIG_USER_ONLY the register is still
visible but always reports the value zero.

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

authored by

Jonathan Behrens and committed by

Palmer Dabbelt 6 years ago ab9056ff a555ad13

+47 -2

4 changed files

expand all

configure

gdb-xml

riscv-32bit-virtual.xml

riscv-64bit-virtual.xml

target

riscv

gdbstub.c

+2 -2

configure

··· 7526 7526 TARGET_BASE_ARCH=riscv 7527 7527 TARGET_ABI_DIR=riscv 7528 7528 mttcg=yes 7529 - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" 7529 + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" 7530 7530 ;; 7531 7531 riscv64) 7532 7532 TARGET_BASE_ARCH=riscv 7533 7533 TARGET_ABI_DIR=riscv 7534 7534 mttcg=yes 7535 - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml" 7535 + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" 7536 7536 ;; 7537 7537 sh4|sh4eb) 7538 7538 TARGET_ARCH=sh4

+11

gdb-xml/riscv-32bit-virtual.xml

··· 1 + <?xml version="1.0"?> 2 +  7 + 8 + <!DOCTYPE feature SYSTEM "gdb-target.dtd"> 9 + <feature name="org.gnu.gdb.riscv.virtual"> 10 + <reg name="priv" bitsize="32"/> 11 + </feature>

+11

gdb-xml/riscv-64bit-virtual.xml

+23

target/riscv/gdbstub.c

··· 373 373 return 0; 374 374 } 375 375 376 + static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) 377 + { 378 + if (n == 0) { 379 + #ifdef CONFIG_USER_ONLY 380 + return gdb_get_regl(mem_buf, 0); 381 + #else 382 + return gdb_get_regl(mem_buf, cs->priv); 383 + #endif 384 + } 385 + return 0; 386 + } 387 + 388 + static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) 389 + { 390 + return 0; 391 + } 392 + 376 393 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) 377 394 { 378 395 RISCVCPU *cpu = RISCV_CPU(cs); ··· 385 402 386 403 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 387 404 240, "riscv-32bit-csr.xml", 0); 405 + 406 + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 407 + 1, "riscv-32bit-virtual.xml", 0); 388 408 #elif defined(TARGET_RISCV64) 389 409 if (env->misa & RVF) { 390 410 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, ··· 393 413 394 414 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 395 415 240, "riscv-64bit-csr.xml", 0); 416 + 417 + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 418 + 1, "riscv-64bit-virtual.xml", 0); 396 419 #endif 397 420 }