jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
leon3: use qemu_irq framework instead of callback as property
"set_pin_in" property is used to define a callback mechanism where the
device says "call the callback function, passing it an opaque cookie
and a 32-bit value". We already have a generic mechanism for doing
that, which is the qemu_irq. So we should just use that.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
+14
-35
+4
-31
hw/intc/grlib_irqmp.c
+4
-31
hw/intc/grlib_irqmp.c
···
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25
*/
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#include "qemu/osdep.h"
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+
#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "cpu.h"
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···
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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-
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void *set_pil_in;
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void *set_pil_in_opaque;
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IRQMPState *state;
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qemu_irq irq;
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} IRQMP;
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struct IRQMPState {
···
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uint32_t pend = 0;
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uint32_t level0 = 0;
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uint32_t level1 = 0;
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set_pil_in_fn set_pil_in;
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assert(state != NULL);
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assert(state->parent != NULL);
···
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trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
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state->mask[0], level1, level0);
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set_pil_in = (set_pil_in_fn)state->parent->set_pil_in;
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/* Trigger level1 interrupt first and level0 if there is no level1 */
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if (level1 != 0) {
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set_pil_in(state->parent->set_pil_in_opaque, level1);
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} else {
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set_pil_in(state->parent->set_pil_in_opaque, level0);
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}
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qemu_set_irq(state->parent->irq, level1 ?: level0);
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}
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static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask)
···
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IRQMP *irqmp = GRLIB_IRQMP(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1);
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memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp,
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"irqmp", IRQMP_REG_SIZE);
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···
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sysbus_init_mmio(dev, &irqmp->iomem);
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}
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-
static void grlib_irqmp_realize(DeviceState *dev, Error **errp)
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-
{
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IRQMP *irqmp = GRLIB_IRQMP(dev);
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-
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/* Check parameters */
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if (irqmp->set_pil_in == NULL) {
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error_setg(errp, "set_pil_in cannot be NULL.");
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}
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}
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static Property grlib_irqmp_properties[] = {
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DEFINE_PROP_PTR("set_pil_in", IRQMP, set_pil_in),
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DEFINE_PROP_PTR("set_pil_in_opaque", IRQMP, set_pil_in_opaque),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = grlib_irqmp_reset;
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dc->props = grlib_irqmp_properties;
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/* Reason: pointer properties "set_pil_in", "set_pil_in_opaque" */
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dc->user_creatable = false;
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dc->realize = grlib_irqmp_realize;
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}
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static const TypeInfo grlib_irqmp_info = {
+9
-4
hw/sparc/leon3.c
+9
-4
hw/sparc/leon3.c
···
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grlib_irqmp_ack((DeviceState *)irq_manager, intno);
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}
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static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
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/*
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* This device assumes that the incoming 'level' value on the
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* qemu_irq is the interrupt number, not just a simple 0/1 level.
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*/
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static void leon3_set_pil_in(void *opaque, int n, int level)
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{
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CPUSPARCState *env = (CPUSPARCState *)opaque;
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CPUSPARCState *env = opaque;
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uint32_t pil_in = level;
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CPUState *cs;
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assert(env != NULL);
···
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/* Allocate IRQ manager */
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dev = qdev_create(NULL, TYPE_GRLIB_IRQMP);
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qdev_prop_set_ptr(dev, "set_pil_in", leon3_set_pil_in);
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qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
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env->pil_irq = qemu_allocate_irq(leon3_set_pil_in, env, 0);
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qdev_connect_gpio_out_named(dev, "grlib-irq", 0, env->pil_irq);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET);
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env->irq_manager = dev;