jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/arm/armsse: Unify init-svtor and cpuwait handling
At the moment the handling of init-svtor and cpuwait initial
values is split between armsse.c and iotkit-sysctl.c:
the code in armsse.c sets the initial state of the CPU
object by setting the init-svtor and start-powered-off
properties, but the iotkit-sysctl.c code has its own
code setting the reset values of its registers (which are
then used when updating the CPU when the guest makes
runtime changes).
Clean this up by making the armsse.c code set properties on the
iotkit-sysctl object to define the initial values of the
registers, so they always match the initial CPU state,
and update the comments in armsse.c accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-9-peter.maydell@linaro.org
+42
-30
+31
-18
hw/arm/armsse.c
+31
-18
hw/arm/armsse.c
···
11
11
12
12
#include "qemu/osdep.h"
13
13
#include "qemu/log.h"
14
+
#include "qemu/bitops.h"
14
15
#include "qapi/error.h"
15
16
#include "trace.h"
16
17
#include "hw/sysbus.h"
···
29
30
int sram_banks;
30
31
int num_cpus;
31
32
uint32_t sys_version;
33
+
uint32_t cpuwait_rst;
32
34
SysConfigFormat sys_config_format;
33
35
bool has_mhus;
34
36
bool has_ppus;
···
43
45
.sram_banks = 1,
44
46
.num_cpus = 1,
45
47
.sys_version = 0x41743,
48
+
.cpuwait_rst = 0,
46
49
.sys_config_format = IoTKitFormat,
47
50
.has_mhus = false,
48
51
.has_ppus = false,
···
55
58
.sram_banks = 4,
56
59
.num_cpus = 2,
57
60
.sys_version = 0x22041743,
61
+
.cpuwait_rst = 2,
58
62
.sys_config_format = SSE200Format,
59
63
.has_mhus = true,
60
64
.has_ppus = true,
···
495
499
496
500
qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32);
497
501
/*
498
-
* In real hardware the initial Secure VTOR is set from the INITSVTOR0
499
-
* register in the IoT Kit System Control Register block, and the
500
-
* initial value of that is in turn specifiable by the FPGA that
501
-
* instantiates the IoT Kit. In QEMU we don't implement this wrinkle,
502
-
* and simply set the CPU's init-svtor to the IoT Kit default value.
503
-
* In SSE-200 the situation is similar, except that the default value
504
-
* is a reset-time signal input. Typically a board using the SSE-200
505
-
* will have a system control processor whose boot firmware initializes
506
-
* the INITSVTOR* registers before powering up the CPUs in any case,
507
-
* so the hardware's default value doesn't matter. QEMU doesn't emulate
502
+
* In real hardware the initial Secure VTOR is set from the INITSVTOR*
503
+
* registers in the IoT Kit System Control Register block. In QEMU
504
+
* we set the initial value here, and also the reset value of the
505
+
* sysctl register, from this object's QOM init-svtor property.
506
+
* If the guest changes the INITSVTOR* registers at runtime then the
507
+
* code in iotkit-sysctl.c will update the CPU init-svtor property
508
+
* (which will then take effect on the next CPU warm-reset).
509
+
*
510
+
* Note that typically a board using the SSE-200 will have a system
511
+
* control processor whose boot firmware initializes the INITSVTOR*
512
+
* registers before powering up the CPUs. QEMU doesn't emulate
508
513
* the control processor, so instead we behave in the way that the
509
-
* firmware does. The initial value is configurable by the board code
510
-
* to match whatever its firmware does.
514
+
* firmware does: the initial value should be set by the board code
515
+
* (using the init-svtor property on the ARMSSE object) to match
516
+
* whatever its firmware does.
511
517
*/
512
518
qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
513
519
/*
514
-
* Start all CPUs except CPU0 powered down. In real hardware it is
515
-
* a configurable property of the SSE-200 which CPUs start powered up
516
-
* (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all
517
-
* the boards we care about start CPU0 and leave CPU1 powered off,
518
-
* we hard-code that for now. We can add QOM properties for this
520
+
* CPUs start powered down if the corresponding bit in the CPUWAIT
521
+
* register is 1. In real hardware the CPUWAIT register reset value is
522
+
* a configurable property of the SSE-200 (via the CPUWAIT0_RST and
523
+
* CPUWAIT1_RST parameters), but since all the boards we care about
524
+
* start CPU0 and leave CPU1 powered off, we hard-code that in
525
+
* info->cpuwait_rst for now. We can add QOM properties for this
519
526
* later if necessary.
520
527
*/
521
-
if (i > 0) {
528
+
if (extract32(info->cpuwait_rst, i, 1)) {
522
529
object_property_set_bool(cpuobj, true, "start-powered-off", &err);
523
530
if (err) {
524
531
error_propagate(errp, err);
···
999
1006
/* System control registers */
1000
1007
object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
1001
1008
"SYS_VERSION", &err);
1009
+
object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst,
1010
+
"CPUWAIT_RST", &err);
1011
+
object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
1012
+
"INITSVTOR0_RST", &err);
1013
+
object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
1014
+
"INITSVTOR1_RST", &err);
1002
1015
object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
1003
1016
if (err) {
1004
1017
error_propagate(errp, err);
+8
-12
hw/misc/iotkit-sysctl.c
+8
-12
hw/misc/iotkit-sysctl.c
···
404
404
s->reset_syndrome = 1;
405
405
s->reset_mask = 0;
406
406
s->gretreg = 0;
407
-
s->initsvtor0 = 0x10000000;
408
-
s->initsvtor1 = 0x10000000;
409
-
if (s->is_sse200) {
410
-
/*
411
-
* CPU 0 starts on, CPU 1 starts off. In real hardware this is
412
-
* configurable by the SoC integrator as a verilog parameter.
413
-
*/
414
-
s->cpuwait = 2;
415
-
} else {
416
-
/* CPU 0 starts on */
417
-
s->cpuwait = 0;
418
-
}
407
+
s->initsvtor0 = s->initsvtor0_rst;
408
+
s->initsvtor1 = s->initsvtor1_rst;
409
+
s->cpuwait = s->cpuwait_rst;
419
410
s->wicctrl = 0;
420
411
s->scsecctrl = 0;
421
412
s->fclk_div = 0;
···
500
491
501
492
static Property iotkit_sysctl_props[] = {
502
493
DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
494
+
DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0),
495
+
DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst,
496
+
0x10000000),
497
+
DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst,
498
+
0x10000000),
503
499
DEFINE_PROP_END_OF_LIST()
504
500
};
505
501