-1

block/trace-events

··· 57 57 58 58 # file-posix.c 59 59 # file-win32.c 60 60 - file_paio_submit_co(int64_t offset, int count, int type) "offset %"PRId64" count %d type %d" 61 60 file_paio_submit(void *acb, void *opaque, int64_t offset, int count, int type) "acb %p opaque %p offset %"PRId64" count %d type %d" 62 61 file_copy_file_range(void *bs, int src, int64_t src_off, int dst, int64_t dst_off, int64_t bytes, int flags, int64_t ret) "bs %p src_fd %d offset %"PRIu64" dst_fd %d offset %"PRIu64" bytes %"PRIu64" flags %d ret %"PRId64 63 62

-7

hw/arm/trace-events

··· 5 5 6 6 # smmu-common.c 7 7 smmu_add_mr(const char *name) "%s" 8 8 - smmu_page_walk(int stage, uint64_t baseaddr, int first_level, uint64_t start, uint64_t end) "stage=%d, baseaddr=0x%"PRIx64", first level=%d, start=0x%"PRIx64", end=0x%"PRIx64 9 9 - smmu_lookup_table(int level, uint64_t baseaddr, int granule_sz, uint64_t start, uint64_t end, int flags, uint64_t subpage_size) "level=%d baseaddr=0x%"PRIx64" granule=%d, start=0x%"PRIx64" end=0x%"PRIx64" flags=%d subpage_size=0x%"PRIx64 10 8 smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64 11 9 smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64 12 10 smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64 ··· 29 27 smmuv3_cmdq_opcode(const char *opcode) "<--- %s" 30 28 smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d " 31 29 smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) "Error on %s command execution: %d" 32 32 - smmuv3_update(bool is_empty, uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "q empty:%d prod:%d cons:%d p.wrap:%d p.cons:%d" 33 33 - smmuv3_update_check_cmd(int error) "cmdq not enabled or error :0x%x" 34 30 smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" 35 35 - smmuv3_write_mmio_idr(uint64_t addr, uint64_t val) "write to RO/Unimpl reg 0x%"PRIx64" val64:0x%"PRIx64 36 36 - smmuv3_write_mmio_evtq_cons_bef_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "Before clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d" 37 37 - smmuv3_write_mmio_evtq_cons_after_clear(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "after clearing interrupt prod:0x%x cons:0x%x prod.w:%d cons.w:%d" 38 31 smmuv3_record_event(const char *type, uint32_t sid) "%s sid=%d" 39 32 smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "SID:0x%x features:0x%x, sid_split:0x%x" 40 33 smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRIx64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d"

-2

hw/block/trace-events

··· 63 63 nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or not page aligned: 0x%"PRIx64"" 64 64 nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64"" 65 65 nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be transferred" 66 66 - nvme_err_invalid_field(void) "invalid field" 67 66 nvme_err_invalid_prp(void) "invalid PRP" 68 68 - nvme_err_invalid_sgl(void) "invalid SGL" 69 67 nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u not within 1-%u" 70 68 nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" 71 69 nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8""

-1

hw/display/trace-events

··· 131 131 # cirrus_vga.c 132 132 vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" 133 133 vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x" 134 134 - vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x" 135 134 vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x" 136 135 137 136 # sii9022.c

-2

hw/i386/trace-events

··· 106 106 amdvi_ir_intctl(uint8_t val) "int_ctl 0x%"PRIx8 107 107 amdvi_ir_target_abort(const char *str) "%s" 108 108 amdvi_ir_delivery_mode(const char *str) "%s" 109 109 - amdvi_ir_generate_msi_message(uint8_t vector, uint8_t delivery_mode, uint8_t dest_mode, uint8_t dest, uint8_t rh) "vector %d delivery-mode %d dest-mode %d dest-id %d rh %d" 110 110 - amdvi_ir_irte_ga(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" offset 0x%"PRIx64 111 109 amdvi_ir_irte_ga_val(uint64_t hi, uint64_t lo) "hi 0x%"PRIx64" lo 0x%"PRIx64 112 110 113 111 # vmport.c

-1

hw/ide/trace-events

··· 91 91 ahci_populate_sglist_bad_offset(void *s, int port, int off_idx, int64_t off_pos) "ahci(%p)[%d]: Incorrect offset! off_idx: %d, off_pos: %"PRId64 92 92 ncq_finish(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:%d]: NCQ transfer finished" 93 93 execute_ncq_command_read(void *s, int port, uint8_t tag, int count, int64_t lba) "ahci(%p)[%d][tag:%d]: NCQ reading %d sectors from LBA %"PRId64 94 94 - execute_ncq_command_write(void *s, int port, uint8_t tag, int count, int64_t lba) "ahci(%p)[%d][tag:%d]: NCQ writing %d sectors to LBA %"PRId64 95 94 execute_ncq_command_unsup(void *s, int port, uint8_t tag, uint8_t cmd) "ahci(%p)[%d][tag:%d]: error: unsupported NCQ command (0x%02x) received" 96 95 process_ncq_command_mismatch(void *s, int port, uint8_t tag, uint8_t slot) "ahci(%p)[%d][tag:%d]: Warning: NCQ slot (%d) did not match the given tag" 97 96 process_ncq_command_aux(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:%d]: Warn: Attempt to use NCQ auxiliary fields"

-1

hw/intc/trace-events

··· 187 187 nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled" 188 188 nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d derived %d (enabled: %d priority %d)" 189 189 nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)" 190 190 - nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1" 191 190 nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)" 192 191 nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets_secure: %d" 193 192 nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)"

-1

hw/misc/macio/trace-events

··· 19 19 macio_gpio_irq_assert(int gpio) "asserting GPIO %d" 20 20 macio_gpio_irq_deassert(int gpio) "deasserting GPIO %d" 21 21 macio_gpio_write(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64" value: 0x%"PRIx64 22 22 - macio_gpio_read(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64" value: 0x%"PRIx64 23 22 24 23 # pmu.c 25 24 pmu_adb_poll(int olen) "ADB autopoll, olen=%d"

-2

hw/misc/trace-events

··· 96 96 tz_msc_reset(void) "TZ MSC: reset" 97 97 tz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d" 98 98 tz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d" 99 99 - tz_msc_irq_enable(int level) "TZ MSC: int_enable = %d" 100 99 tz_msc_irq_clear(int level) "TZ MSC: int_clear = %d" 101 100 tz_msc_update_irq(int level) "TZ MSC: setting irq line to %d" 102 101 tz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked" ··· 117 116 iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl S regs write: offset 0x%x data 0x%" PRIx64 " size %u" 118 117 iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" 119 118 iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" 120 120 - iotkit_secctl_reset(void) "IoTKit SecCtl: reset" 121 119 122 120 # imx6ul_ccm.c 123 121 ccm_entry(void) "\n"

-8

hw/ppc/trace-events

··· 12 12 # spapr.c 13 13 spapr_cas_failed(unsigned long n) "DT diff buffer is too small: %ld bytes" 14 14 spapr_cas_continue(unsigned long n) "Copy changes to the guest: %ld bytes" 15 15 - spapr_irq_alloc(int irq) "irq %d" 16 16 - spapr_irq_alloc_block(int first, int num, bool lsi, int align) "first irq %d, %d irqs, lsi=%d, alignnum %d" 17 15 spapr_irq_free(int src, int irq, int num) "Source#%d, first irq %d, %d irqs" 18 16 spapr_irq_free_warn(int src, int irq) "Source#%d, irq %d is already free" 19 17 20 18 # spapr_hcall.c 21 21 - spapr_cas_pvr_try(uint32_t pvr) "0x%x" 22 19 spapr_cas_pvr(uint32_t cur_pvr, bool explicit_match, uint32_t new_pvr) "current=0x%x, explicit_match=%u, new=0x%x" 23 20 spapr_h_resize_hpt_prepare(uint64_t flags, uint64_t shift) "flags=0x%"PRIx64", shift=%"PRIu64 24 21 spapr_h_resize_hpt_commit(uint64_t flags, uint64_t shift) "flags=0x%"PRIx64", shift=%"PRIu64 ··· 47 44 # spapr_drc.c 48 45 spapr_drc_set_isolation_state(uint32_t index, int state) "drc: 0x%"PRIx32", state: 0x%"PRIx32 49 46 spapr_drc_set_isolation_state_finalizing(uint32_t index) "drc: 0x%"PRIx32 50 50 - spapr_drc_set_isolation_state_deferring(uint32_t index) "drc: 0x%"PRIx32 51 47 spapr_drc_set_dr_indicator(uint32_t index, int state) "drc: 0x%"PRIx32", state: 0x%x" 52 48 spapr_drc_set_allocation_state(uint32_t index, int state) "drc: 0x%"PRIx32", state: 0x%x" 53 49 spapr_drc_set_allocation_state_finalizing(uint32_t index) "drc: 0x%"PRIx32 54 50 spapr_drc_set_configured(uint32_t index) "drc: 0x%"PRIx32 55 55 - spapr_drc_set_configured_skipping(uint32_t index) "drc: 0x%"PRIx32", isolated device" 56 51 spapr_drc_attach(uint32_t index) "drc: 0x%"PRIx32 57 52 spapr_drc_detach(uint32_t index) "drc: 0x%"PRIx32 58 53 spapr_drc_awaiting_quiesce(uint32_t index) "drc: 0x%"PRIx32 59 59 - spapr_drc_awaiting_allocation(uint32_t index) "drc: 0x%"PRIx32 60 54 spapr_drc_reset(uint32_t index) "drc: 0x%"PRIx32 61 55 spapr_drc_realize(uint32_t index) "drc: 0x%"PRIx32 62 56 spapr_drc_realize_child(uint32_t index, char *childname) "drc: 0x%"PRIx32", child name: %s" ··· 71 65 spapr_rtas_get_sensor_state_not_supported(uint32_t index, uint32_t type) "sensor index: 0x%"PRIx32", type: %"PRIu32 72 66 spapr_rtas_get_sensor_state_invalid(uint32_t index) "sensor index: 0x%"PRIx32 73 67 spapr_rtas_ibm_configure_connector_invalid(uint32_t index) "DRC index: 0x%"PRIx32 74 74 - spapr_rtas_ibm_configure_connector_missing_fdt(uint32_t index) "DRC index: 0x%"PRIx32 75 68 76 69 # spapr_vio.c 77 70 spapr_vio_h_reg_crq(uint64_t reg, uint64_t queue_addr, uint64_t queue_len) "CRQ for dev 0x%" PRIx64 " registered at 0x%" PRIx64 "/0x%" PRIx64 ··· 105 98 ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of size=0x%" PRIx64 " to CPU=0x%" PRIx64 106 99 ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 107 100 ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 108 108 - ppc440_pcix_reg_write(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64

-1

hw/sd/trace-events

··· 35 35 sdcard_response(const char *rspdesc, int rsplen) "%s (sz:%d)" 36 36 sdcard_powerup(void) "" 37 37 sdcard_inquiry_cmd41(void) "" 38 38 - sdcard_set_enable(bool current_state, bool new_state) "%u -> %u" 39 38 sdcard_reset(void) "" 40 39 sdcard_set_blocklen(uint16_t length) "0x%03x" 41 40 sdcard_inserted(bool readonly) "read_only: %u"

-1

hw/vfio/trace-events

··· 16 16 vfio_msix_pba_enable(const char *name) " (%s)" 17 17 vfio_msix_disable(const char *name) " (%s)" 18 18 vfio_msix_fixup(const char *name, int bar, uint64_t start, uint64_t end) " (%s) MSI-X region %d mmap fixup [0x%"PRIx64" - 0x%"PRIx64"]" 19 19 - vfio_msix_relo_cost(const char *name, int bar, uint64_t cost) " (%s) BAR %d cost 0x%"PRIx64"" 20 19 vfio_msix_relo(const char *name, int bar, uint64_t offset) " (%s) BAR %d offset 0x%"PRIx64"" 21 20 vfio_msi_enable(const char *name, int nr_vectors) " (%s) Enabled %d MSI vectors" 22 21 vfio_msi_disable(const char *name) " (%s)"

-2

nbd/trace-events

··· 58 58 nbd_negotiate_options_check_magic(uint64_t magic) "Checking opts magic 0x%" PRIx64 59 59 nbd_negotiate_options_check_option(uint32_t option, const char *name) "Checking option %" PRIu32 " (%s)" 60 60 nbd_negotiate_begin(void) "Beginning negotiation" 61 61 - nbd_negotiate_old_style(uint64_t size, unsigned flags) "advertising size %" PRIu64 " and flags 0x%x" 62 61 nbd_negotiate_new_style_size_flags(uint64_t size, unsigned flags) "advertising size %" PRIu64 " and flags 0x%x" 63 62 nbd_negotiate_success(void) "Negotiation succeeded" 64 63 nbd_receive_request(uint32_t magic, uint16_t flags, uint16_t type, uint64_t from, uint32_t len) "Got request: { magic = 0x%" PRIx32 ", .flags = 0x%" PRIx16 ", .type = 0x%" PRIx16 ", from = %" PRIu64 ", len = %" PRIu32 " }" ··· 72 71 nbd_co_send_structured_error(uint64_t handle, int err, const char *errname, const char *msg) "Send structured error reply: handle = %" PRIu64 ", error = %d (%s), msg = '%s'" 73 72 nbd_co_receive_request_decode_type(uint64_t handle, uint16_t type, const char *name) "Decoding type: handle = %" PRIu64 ", type = %" PRIu16 " (%s)" 74 73 nbd_co_receive_request_payload_received(uint64_t handle, uint32_t len) "Payload received: handle = %" PRIu64 ", len = %" PRIu32 75 75 - nbd_co_receive_request_cmd_write(uint32_t len) "Reading %" PRIu32 " byte(s)" 76 74 nbd_trip(void) "Reading request"

-2

util/trace-events

··· 36 36 qemu_coroutine_terminate(void *co) "self %p" 37 37 38 38 # qemu-coroutine-lock.c 39 39 - qemu_co_queue_run_restart(void *co) "co %p" 40 39 qemu_co_mutex_lock_uncontended(void *mutex, void *self) "mutex %p self %p" 41 40 qemu_co_mutex_lock_entry(void *mutex, void *self) "mutex %p self %p" 42 41 qemu_co_mutex_lock_return(void *mutex, void *self) "mutex %p self %p" ··· 78 77 qemu_vfio_new_mapping(void *s, void *host, size_t size, int index, uint64_t iova) "s %p host %p size %zu index %d iova 0x%"PRIx64 79 78 qemu_vfio_do_mapping(void *s, void *host, size_t size, uint64_t iova) "s %p host %p size %zu iova 0x%"PRIx64 80 79 qemu_vfio_dma_map(void *s, void *host, size_t size, bool temporary, uint64_t *iova) "s %p host %p size %zu temporary %d iova %p" 81 81 - qemu_vfio_dma_map_invalid(void *s, void *mapping_host, size_t mapping_size, void *host, size_t size) "s %p mapping %p %zu requested %p %zu" 82 80 qemu_vfio_dma_unmap(void *s, void *host) "s %p host %p"