jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/riscv: integer scalar move instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-57-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
authored by
LIU Zhiwei
and committed by
Alistair Francis
9fc08be6
90355f39
+67
+1
target/riscv/insn32.decode
+1
target/riscv/insn32.decode
···
564
564
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
565
565
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
566
566
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
567
+
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
567
568
568
569
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
569
570
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
+60
target/riscv/insn_trans/trans_rvv.inc.c
+60
target/riscv/insn_trans/trans_rvv.inc.c
···
2649
2649
tcg_temp_free_i64(tmp);
2650
2650
return true;
2651
2651
}
2652
+
2653
+
/* Integer Scalar Move Instruction */
2654
+
2655
+
static void store_element(TCGv_i64 val, TCGv_ptr base,
2656
+
int ofs, int sew)
2657
+
{
2658
+
switch (sew) {
2659
+
case MO_8:
2660
+
tcg_gen_st8_i64(val, base, ofs);
2661
+
break;
2662
+
case MO_16:
2663
+
tcg_gen_st16_i64(val, base, ofs);
2664
+
break;
2665
+
case MO_32:
2666
+
tcg_gen_st32_i64(val, base, ofs);
2667
+
break;
2668
+
case MO_64:
2669
+
tcg_gen_st_i64(val, base, ofs);
2670
+
break;
2671
+
default:
2672
+
g_assert_not_reached();
2673
+
break;
2674
+
}
2675
+
}
2676
+
2677
+
/*
2678
+
* Store vreg[idx] = val.
2679
+
* The index must be in range of VLMAX.
2680
+
*/
2681
+
static void vec_element_storei(DisasContext *s, int vreg,
2682
+
int idx, TCGv_i64 val)
2683
+
{
2684
+
store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
2685
+
}
2686
+
2687
+
/* vmv.s.x vd, rs1 # vd[0] = rs1 */
2688
+
static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
2689
+
{
2690
+
if (vext_check_isa_ill(s)) {
2691
+
/* This instruction ignores LMUL and vector register groups */
2692
+
int maxsz = s->vlen >> 3;
2693
+
TCGv_i64 t1;
2694
+
TCGLabel *over = gen_new_label();
2695
+
2696
+
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
2697
+
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
2698
+
if (a->rs1 == 0) {
2699
+
goto done;
2700
+
}
2701
+
2702
+
t1 = tcg_temp_new_i64();
2703
+
tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
2704
+
vec_element_storei(s, a->rd, 0, t1);
2705
+
tcg_temp_free_i64(t1);
2706
+
done:
2707
+
gen_set_label(over);
2708
+
return true;
2709
+
}
2710
+
return false;
2711
+
}