jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180111' into staging
target-arm queue:
* add aarch64_be linux-user target
* Virt: ACPI: fix qemu assert due to re-assigned table data address
* imx_fec: various bug fixes and cleanups
* hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask()
* hw/sd/pxa2xx_mmci: add read/write() trace events
* linux-user/arm/nwfpe: Check coprocessor number for FPA emulation
* target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions
* hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI
* hw/intc/arm_gic: reserved register addresses are RAZ/WI
# gpg: Signature made Thu 11 Jan 2018 13:37:25 GMT
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180111: (26 commits)
hw/intc/arm_gic: reserved register addresses are RAZ/WI
hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI
target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions
linux-user/arm/nwfpe: Check coprocessor number for FPA emulation
hw/sd/pxa2xx_mmci: add read/write() trace events
hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask()
imx_fec: Reserve full FSL_IMX25_FEC_SIZE page for the register file
imx_fec: Fix a typo in imx_enet_receive()
imx_fec: Use correct length for packet size
imx_fec: Add support for multiple Tx DMA rings
imx_fec: Emulate SHIFT16 in ENETx_RACC
imx_fec: Use MIN instead of explicit ternary operator
imx_fec: Use ENET_FTRL to determine truncation length
imx_fec: Move Tx frame buffer away from the stack
imx_fec: Change queue flushing heuristics
imx_fec: Refactor imx_eth_enable_rx()
imx_fec: Do not link to netdev
Virt: ACPI: fix qemu assert due to re-assigned table data address
target/arm: Fix stlxp for aarch64_be
linux-user: Activate armeb handler registration
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+356
-119
+3
-2
configure
+3
-2
configure
···
6439
6439
target_bigendian="no"
6440
6440
6441
6441
case "$target_name" in
6442
-
armeb|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
6442
+
armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
6443
6443
target_bigendian=yes
6444
6444
;;
6445
6445
esac
···
6494
6494
mttcg="yes"
6495
6495
gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"
6496
6496
;;
6497
-
aarch64)
6497
+
aarch64|aarch64_be)
6498
+
TARGET_ARCH=aarch64
6498
6499
TARGET_BASE_ARCH=arm
6499
6500
bflt="yes"
6500
6501
mttcg="yes"
+1
default-configs/aarch64_be-linux-user.mak
+1
default-configs/aarch64_be-linux-user.mak
···
1
+
# Default configuration for aarch64_be-linux-user
+1
hw/arm/fsl-imx6.c
+1
hw/arm/fsl-imx6.c
+11
-7
hw/arm/virt-acpi-build.c
+11
-7
hw/arm/virt-acpi-build.c
···
453
453
AcpiSerialPortConsoleRedirection *spcr;
454
454
const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
455
455
int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
456
+
int spcr_start = table_data->len;
456
457
457
458
spcr = acpi_data_push(table_data, sizeof(*spcr));
458
459
···
476
477
spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */
477
478
spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */
478
479
479
-
build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2,
480
-
NULL, NULL);
480
+
build_header(linker, table_data, (void *)(table_data->data + spcr_start),
481
+
"SPCR", table_data->len - spcr_start, 2, NULL, NULL);
481
482
}
482
483
483
484
static void
···
512
513
mem_base += numa_info[i].node_mem;
513
514
}
514
515
515
-
build_header(linker, table_data, (void *)srat, "SRAT",
516
-
table_data->len - srat_start, 3, NULL, NULL);
516
+
build_header(linker, table_data, (void *)(table_data->data + srat_start),
517
+
"SRAT", table_data->len - srat_start, 3, NULL, NULL);
517
518
}
518
519
519
520
static void
···
522
523
AcpiTableMcfg *mcfg;
523
524
const MemMapEntry *memmap = vms->memmap;
524
525
int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
526
+
int mcfg_start = table_data->len;
525
527
526
528
mcfg = acpi_data_push(table_data, len);
527
529
mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
···
532
534
mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
533
535
/ PCIE_MMCFG_SIZE_MIN) - 1;
534
536
535
-
build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL);
537
+
build_header(linker, table_data, (void *)(table_data->data + mcfg_start),
538
+
"MCFG", table_data->len - mcfg_start, 1, NULL, NULL);
536
539
}
537
540
538
541
/* GTDT */
···
651
654
static void build_fadt(GArray *table_data, BIOSLinker *linker,
652
655
VirtMachineState *vms, unsigned dsdt_tbl_offset)
653
656
{
657
+
int fadt_start = table_data->len;
654
658
AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
655
659
unsigned xdsdt_entry_offset = (char *)&fadt->x_dsdt - table_data->data;
656
660
uint16_t bootflags;
···
681
685
ACPI_BUILD_TABLE_FILE, xdsdt_entry_offset, sizeof(fadt->x_dsdt),
682
686
ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
683
687
684
-
build_header(linker, table_data,
685
-
(void *)fadt, "FACP", sizeof(*fadt), 5, NULL, NULL);
688
+
build_header(linker, table_data, (void *)(table_data->data + fadt_start),
689
+
"FACP", table_data->len - fadt_start, 5, NULL, NULL);
686
690
}
687
691
688
692
/* DSDT */
+3
-2
hw/intc/arm_gic.c
+3
-2
hw/intc/arm_gic.c
···
1261
1261
default:
1262
1262
qemu_log_mask(LOG_GUEST_ERROR,
1263
1263
"gic_cpu_read: Bad offset %x\n", (int)offset);
1264
-
return MEMTX_ERROR;
1264
+
*data = 0;
1265
+
break;
1265
1266
}
1266
1267
return MEMTX_OK;
1267
1268
}
···
1329
1330
default:
1330
1331
qemu_log_mask(LOG_GUEST_ERROR,
1331
1332
"gic_cpu_write: Bad offset %x\n", (int)offset);
1332
-
return MEMTX_ERROR;
1333
+
return MEMTX_OK;
1333
1334
}
1334
1335
gic_update(s);
1335
1336
return MEMTX_OK;
+13
hw/intc/arm_gicv3_dist.c
+13
hw/intc/arm_gicv3_dist.c
···
817
817
"%s: invalid guest read at offset " TARGET_FMT_plx
818
818
"size %u\n", __func__, offset, size);
819
819
trace_gicv3_dist_badread(offset, size, attrs.secure);
820
+
/* The spec requires that reserved registers are RAZ/WI;
821
+
* so use MEMTX_ERROR returns from leaf functions as a way to
822
+
* trigger the guest-error logging but don't return it to
823
+
* the caller, or we'll cause a spurious guest data abort.
824
+
*/
825
+
r = MEMTX_OK;
826
+
*data = 0;
820
827
} else {
821
828
trace_gicv3_dist_read(offset, *data, size, attrs.secure);
822
829
}
···
852
859
"%s: invalid guest write at offset " TARGET_FMT_plx
853
860
"size %u\n", __func__, offset, size);
854
861
trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
862
+
/* The spec requires that reserved registers are RAZ/WI;
863
+
* so use MEMTX_ERROR returns from leaf functions as a way to
864
+
* trigger the guest-error logging but don't return it to
865
+
* the caller, or we'll cause a spurious guest data abort.
866
+
*/
867
+
r = MEMTX_OK;
855
868
} else {
856
869
trace_gicv3_dist_write(offset, data, size, attrs.secure);
857
870
}
+3
-5
hw/intc/arm_gicv3_its_common.c
+3
-5
hw/intc/arm_gicv3_its_common.c
···
67
67
MemTxAttrs attrs)
68
68
{
69
69
qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
70
-
return MEMTX_ERROR;
70
+
*data = 0;
71
+
return MEMTX_OK;
71
72
}
72
73
73
74
static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
···
82
83
if (ret <= 0) {
83
84
qemu_log_mask(LOG_GUEST_ERROR,
84
85
"ITS: Error sending MSI: %s\n", strerror(-ret));
85
-
return MEMTX_DECODE_ERROR;
86
86
}
87
-
88
-
return MEMTX_OK;
89
87
} else {
90
88
qemu_log_mask(LOG_GUEST_ERROR,
91
89
"ITS write at bad offset 0x%"PRIx64"\n", offset);
92
-
return MEMTX_DECODE_ERROR;
93
90
}
91
+
return MEMTX_OK;
94
92
}
95
93
96
94
static const MemoryRegionOps gicv3_its_trans_ops = {
+13
hw/intc/arm_gicv3_redist.c
+13
hw/intc/arm_gicv3_redist.c
···
455
455
"size %u\n", __func__, offset, size);
456
456
trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
457
457
size, attrs.secure);
458
+
/* The spec requires that reserved registers are RAZ/WI;
459
+
* so use MEMTX_ERROR returns from leaf functions as a way to
460
+
* trigger the guest-error logging but don't return it to
461
+
* the caller, or we'll cause a spurious guest data abort.
462
+
*/
463
+
r = MEMTX_OK;
464
+
*data = 0;
458
465
} else {
459
466
trace_gicv3_redist_read(gicv3_redist_affid(cs), offset, *data,
460
467
size, attrs.secure);
···
505
512
"size %u\n", __func__, offset, size);
506
513
trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
507
514
size, attrs.secure);
515
+
/* The spec requires that reserved registers are RAZ/WI;
516
+
* so use MEMTX_ERROR returns from leaf functions as a way to
517
+
* trigger the guest-error logging but don't return it to
518
+
* the caller, or we'll cause a spurious guest data abort.
519
+
*/
520
+
r = MEMTX_OK;
508
521
} else {
509
522
trace_gicv3_redist_write(gicv3_redist_affid(cs), offset, data,
510
523
size, attrs.secure);
+163
-47
hw/net/imx_fec.c
+163
-47
hw/net/imx_fec.c
···
196
196
}
197
197
}
198
198
199
+
/*
200
+
* Versions of this device with more than one TX descriptor save the
201
+
* 2nd and 3rd descriptors in a subsection, to maintain migration
202
+
* compatibility with previous versions of the device that only
203
+
* supported a single descriptor.
204
+
*/
205
+
static bool imx_eth_is_multi_tx_ring(void *opaque)
206
+
{
207
+
IMXFECState *s = IMX_FEC(opaque);
208
+
209
+
return s->tx_ring_num > 1;
210
+
}
211
+
212
+
static const VMStateDescription vmstate_imx_eth_txdescs = {
213
+
.name = "imx.fec/txdescs",
214
+
.version_id = 1,
215
+
.minimum_version_id = 1,
216
+
.needed = imx_eth_is_multi_tx_ring,
217
+
.fields = (VMStateField[]) {
218
+
VMSTATE_UINT32(tx_descriptor[1], IMXFECState),
219
+
VMSTATE_UINT32(tx_descriptor[2], IMXFECState),
220
+
VMSTATE_END_OF_LIST()
221
+
}
222
+
};
223
+
199
224
static const VMStateDescription vmstate_imx_eth = {
200
225
.name = TYPE_IMX_FEC,
201
226
.version_id = 2,
···
203
228
.fields = (VMStateField[]) {
204
229
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
205
230
VMSTATE_UINT32(rx_descriptor, IMXFECState),
206
-
VMSTATE_UINT32(tx_descriptor, IMXFECState),
207
-
231
+
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
208
232
VMSTATE_UINT32(phy_status, IMXFECState),
209
233
VMSTATE_UINT32(phy_control, IMXFECState),
210
234
VMSTATE_UINT32(phy_advertise, IMXFECState),
211
235
VMSTATE_UINT32(phy_int, IMXFECState),
212
236
VMSTATE_UINT32(phy_int_mask, IMXFECState),
213
237
VMSTATE_END_OF_LIST()
214
-
}
238
+
},
239
+
.subsections = (const VMStateDescription * []) {
240
+
&vmstate_imx_eth_txdescs,
241
+
NULL
242
+
},
215
243
};
216
244
217
245
#define PHY_INT_ENERGYON (1 << 7)
···
405
433
static void imx_fec_do_tx(IMXFECState *s)
406
434
{
407
435
int frame_size = 0, descnt = 0;
408
-
uint8_t frame[ENET_MAX_FRAME_SIZE];
409
-
uint8_t *ptr = frame;
410
-
uint32_t addr = s->tx_descriptor;
436
+
uint8_t *ptr = s->frame;
437
+
uint32_t addr = s->tx_descriptor[0];
411
438
412
439
while (descnt++ < IMX_MAX_DESC) {
413
440
IMXFECBufDesc bd;
···
431
458
frame_size += len;
432
459
if (bd.flags & ENET_BD_L) {
433
460
/* Last buffer in frame. */
434
-
qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size);
435
-
ptr = frame;
461
+
qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);
462
+
ptr = s->frame;
436
463
frame_size = 0;
437
464
s->regs[ENET_EIR] |= ENET_INT_TXF;
438
465
}
···
448
475
}
449
476
}
450
477
451
-
s->tx_descriptor = addr;
478
+
s->tx_descriptor[0] = addr;
452
479
453
480
imx_eth_update(s);
454
481
}
455
482
456
-
static void imx_enet_do_tx(IMXFECState *s)
483
+
static void imx_enet_do_tx(IMXFECState *s, uint32_t index)
457
484
{
458
485
int frame_size = 0, descnt = 0;
459
-
uint8_t frame[ENET_MAX_FRAME_SIZE];
460
-
uint8_t *ptr = frame;
461
-
uint32_t addr = s->tx_descriptor;
486
+
487
+
uint8_t *ptr = s->frame;
488
+
uint32_t addr, int_txb, int_txf, tdsr;
489
+
size_t ring;
490
+
491
+
switch (index) {
492
+
case ENET_TDAR:
493
+
ring = 0;
494
+
int_txb = ENET_INT_TXB;
495
+
int_txf = ENET_INT_TXF;
496
+
tdsr = ENET_TDSR;
497
+
break;
498
+
case ENET_TDAR1:
499
+
ring = 1;
500
+
int_txb = ENET_INT_TXB1;
501
+
int_txf = ENET_INT_TXF1;
502
+
tdsr = ENET_TDSR1;
503
+
break;
504
+
case ENET_TDAR2:
505
+
ring = 2;
506
+
int_txb = ENET_INT_TXB2;
507
+
int_txf = ENET_INT_TXF2;
508
+
tdsr = ENET_TDSR2;
509
+
break;
510
+
default:
511
+
qemu_log_mask(LOG_GUEST_ERROR,
512
+
"%s: bogus value for index %x\n",
513
+
__func__, index);
514
+
abort();
515
+
break;
516
+
}
517
+
518
+
addr = s->tx_descriptor[ring];
462
519
463
520
while (descnt++ < IMX_MAX_DESC) {
464
521
IMXENETBufDesc bd;
···
482
539
frame_size += len;
483
540
if (bd.flags & ENET_BD_L) {
484
541
if (bd.option & ENET_BD_PINS) {
485
-
struct ip_header *ip_hd = PKT_GET_IP_HDR(frame);
542
+
struct ip_header *ip_hd = PKT_GET_IP_HDR(s->frame);
486
543
if (IP_HEADER_VERSION(ip_hd) == 4) {
487
-
net_checksum_calculate(frame, frame_size);
544
+
net_checksum_calculate(s->frame, frame_size);
488
545
}
489
546
}
490
547
if (bd.option & ENET_BD_IINS) {
491
-
struct ip_header *ip_hd = PKT_GET_IP_HDR(frame);
548
+
struct ip_header *ip_hd = PKT_GET_IP_HDR(s->frame);
492
549
/* We compute checksum only for IPv4 frames */
493
550
if (IP_HEADER_VERSION(ip_hd) == 4) {
494
551
uint16_t csum;
···
498
555
}
499
556
}
500
557
/* Last buffer in frame. */
501
-
qemu_send_packet(qemu_get_queue(s->nic), frame, len);
502
-
ptr = frame;
558
+
559
+
qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);
560
+
ptr = s->frame;
561
+
503
562
frame_size = 0;
504
563
if (bd.option & ENET_BD_TX_INT) {
505
-
s->regs[ENET_EIR] |= ENET_INT_TXF;
564
+
s->regs[ENET_EIR] |= int_txf;
506
565
}
507
566
}
508
567
if (bd.option & ENET_BD_TX_INT) {
509
-
s->regs[ENET_EIR] |= ENET_INT_TXB;
568
+
s->regs[ENET_EIR] |= int_txb;
510
569
}
511
570
bd.flags &= ~ENET_BD_R;
512
571
/* Write back the modified descriptor. */
513
572
imx_enet_write_bd(&bd, addr);
514
573
/* Advance to the next descriptor. */
515
574
if ((bd.flags & ENET_BD_W) != 0) {
516
-
addr = s->regs[ENET_TDSR];
575
+
addr = s->regs[tdsr];
517
576
} else {
518
577
addr += sizeof(bd);
519
578
}
520
579
}
521
580
522
-
s->tx_descriptor = addr;
581
+
s->tx_descriptor[ring] = addr;
523
582
524
583
imx_eth_update(s);
525
584
}
526
585
527
-
static void imx_eth_do_tx(IMXFECState *s)
586
+
static void imx_eth_do_tx(IMXFECState *s, uint32_t index)
528
587
{
529
588
if (!s->is_fec && (s->regs[ENET_ECR] & ENET_ECR_EN1588)) {
530
-
imx_enet_do_tx(s);
589
+
imx_enet_do_tx(s, index);
531
590
} else {
532
591
imx_fec_do_tx(s);
533
592
}
534
593
}
535
594
536
-
static void imx_eth_enable_rx(IMXFECState *s)
595
+
static void imx_eth_enable_rx(IMXFECState *s, bool flush)
537
596
{
538
597
IMXFECBufDesc bd;
539
-
bool tmp;
598
+
bool rx_ring_full;
540
599
541
600
imx_fec_read_bd(&bd, s->rx_descriptor);
542
601
543
-
tmp = ((bd.flags & ENET_BD_E) != 0);
602
+
rx_ring_full = !(bd.flags & ENET_BD_E);
544
603
545
-
if (!tmp) {
604
+
if (rx_ring_full) {
546
605
FEC_PRINTF("RX buffer full\n");
547
-
} else if (!s->regs[ENET_RDAR]) {
606
+
} else if (flush) {
548
607
qemu_flush_queued_packets(qemu_get_queue(s->nic));
549
608
}
550
609
551
-
s->regs[ENET_RDAR] = tmp ? ENET_RDAR_RDAR : 0;
610
+
s->regs[ENET_RDAR] = rx_ring_full ? 0 : ENET_RDAR_RDAR;
552
611
}
553
612
554
613
static void imx_eth_reset(DeviceState *d)
···
585
644
}
586
645
587
646
s->rx_descriptor = 0;
588
-
s->tx_descriptor = 0;
647
+
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
589
648
590
649
/* We also reset the PHY */
591
650
phy_reset(s);
···
791
850
unsigned size)
792
851
{
793
852
IMXFECState *s = IMX_FEC(opaque);
853
+
const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s);
794
854
uint32_t index = offset >> 2;
795
855
796
856
FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_eth_reg_name(s, index),
···
807
867
if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) {
808
868
if (!s->regs[index]) {
809
869
s->regs[index] = ENET_RDAR_RDAR;
810
-
imx_eth_enable_rx(s);
870
+
imx_eth_enable_rx(s, true);
811
871
}
812
872
} else {
813
873
s->regs[index] = 0;
814
874
}
815
875
break;
816
-
case ENET_TDAR:
876
+
case ENET_TDAR1: /* FALLTHROUGH */
877
+
case ENET_TDAR2: /* FALLTHROUGH */
878
+
if (unlikely(single_tx_ring)) {
879
+
qemu_log_mask(LOG_GUEST_ERROR,
880
+
"[%s]%s: trying to access TDAR2 or TDAR1\n",
881
+
TYPE_IMX_FEC, __func__);
882
+
return;
883
+
}
884
+
case ENET_TDAR: /* FALLTHROUGH */
817
885
if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) {
818
886
s->regs[index] = ENET_TDAR_TDAR;
819
-
imx_eth_do_tx(s);
887
+
imx_eth_do_tx(s, index);
820
888
}
821
889
s->regs[index] = 0;
822
890
break;
···
828
896
if ((s->regs[index] & ENET_ECR_ETHEREN) == 0) {
829
897
s->regs[ENET_RDAR] = 0;
830
898
s->rx_descriptor = s->regs[ENET_RDSR];
831
-
s->regs[ENET_TDAR] = 0;
832
-
s->tx_descriptor = s->regs[ENET_TDSR];
899
+
s->regs[ENET_TDAR] = 0;
900
+
s->regs[ENET_TDAR1] = 0;
901
+
s->regs[ENET_TDAR2] = 0;
902
+
s->tx_descriptor[0] = s->regs[ENET_TDSR];
903
+
s->tx_descriptor[1] = s->regs[ENET_TDSR1];
904
+
s->tx_descriptor[2] = s->regs[ENET_TDSR2];
833
905
}
834
906
break;
835
907
case ENET_MMFR:
···
907
979
} else {
908
980
s->regs[index] = value & ~7;
909
981
}
910
-
s->tx_descriptor = s->regs[index];
982
+
s->tx_descriptor[0] = s->regs[index];
983
+
break;
984
+
case ENET_TDSR1:
985
+
if (unlikely(single_tx_ring)) {
986
+
qemu_log_mask(LOG_GUEST_ERROR,
987
+
"[%s]%s: trying to access TDSR1\n",
988
+
TYPE_IMX_FEC, __func__);
989
+
return;
990
+
}
991
+
992
+
s->regs[index] = value & ~7;
993
+
s->tx_descriptor[1] = s->regs[index];
994
+
break;
995
+
case ENET_TDSR2:
996
+
if (unlikely(single_tx_ring)) {
997
+
qemu_log_mask(LOG_GUEST_ERROR,
998
+
"[%s]%s: trying to access TDSR2\n",
999
+
TYPE_IMX_FEC, __func__);
1000
+
return;
1001
+
}
1002
+
1003
+
s->regs[index] = value & ~7;
1004
+
s->tx_descriptor[2] = s->regs[index];
911
1005
break;
912
1006
case ENET_MRBR:
913
1007
s->regs[index] = value & 0x00003ff0;
···
930
1024
931
1025
FEC_PRINTF("\n");
932
1026
933
-
return s->regs[ENET_RDAR] ? 1 : 0;
1027
+
return !!s->regs[ENET_RDAR];
934
1028
}
935
1029
936
1030
static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
···
1020
1114
}
1021
1115
}
1022
1116
s->rx_descriptor = addr;
1023
-
imx_eth_enable_rx(s);
1117
+
imx_eth_enable_rx(s, false);
1024
1118
imx_eth_update(s);
1025
1119
return len;
1026
1120
}
···
1037
1131
uint8_t *crc_ptr;
1038
1132
unsigned int buf_len;
1039
1133
size_t size = len;
1134
+
bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16;
1040
1135
1041
1136
FEC_PRINTF("len %d\n", (int)size);
1042
1137
···
1051
1146
crc = cpu_to_be32(crc32(~0, buf, size));
1052
1147
crc_ptr = (uint8_t *) &crc;
1053
1148
1054
-
/* Huge frames are truncted. */
1055
-
if (size > ENET_MAX_FRAME_SIZE) {
1056
-
size = ENET_MAX_FRAME_SIZE;
1149
+
if (shift16) {
1150
+
size += 2;
1151
+
}
1152
+
1153
+
/* Huge frames are truncated. */
1154
+
if (size > s->regs[ENET_FTRL]) {
1155
+
size = s->regs[ENET_FTRL];
1057
1156
flags |= ENET_BD_TR | ENET_BD_LG;
1058
1157
}
1059
1158
···
1076
1175
TYPE_IMX_FEC, __func__);
1077
1176
break;
1078
1177
}
1079
-
buf_len = (size <= s->regs[ENET_MRBR]) ? size : s->regs[ENET_MRBR];
1178
+
buf_len = MIN(size, s->regs[ENET_MRBR]);
1080
1179
bd.length = buf_len;
1081
1180
size -= buf_len;
1082
1181
···
1087
1186
buf_len += size - 4;
1088
1187
}
1089
1188
buf_addr = bd.data;
1189
+
1190
+
if (shift16) {
1191
+
/*
1192
+
* If SHIFT16 bit of ENETx_RACC register is set we need to
1193
+
* align the payload to 4-byte boundary.
1194
+
*/
1195
+
const uint8_t zeros[2] = { 0 };
1196
+
1197
+
dma_memory_write(&address_space_memory, buf_addr,
1198
+
zeros, sizeof(zeros));
1199
+
1200
+
buf_addr += sizeof(zeros);
1201
+
buf_len -= sizeof(zeros);
1202
+
1203
+
/* We only do this once per Ethernet frame */
1204
+
shift16 = false;
1205
+
}
1206
+
1090
1207
dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
1091
1208
buf += buf_len;
1092
1209
if (size < 4) {
···
1116
1233
}
1117
1234
}
1118
1235
s->rx_descriptor = addr;
1119
-
imx_eth_enable_rx(s);
1236
+
imx_eth_enable_rx(s, false);
1120
1237
imx_eth_update(s);
1121
1238
return len;
1122
1239
}
···
1164
1281
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1165
1282
1166
1283
memory_region_init_io(&s->iomem, OBJECT(dev), &imx_eth_ops, s,
1167
-
TYPE_IMX_FEC, 0x400);
1284
+
TYPE_IMX_FEC, FSL_IMX25_FEC_SIZE);
1168
1285
sysbus_init_mmio(sbd, &s->iomem);
1169
1286
sysbus_init_irq(sbd, &s->irq[0]);
1170
1287
sysbus_init_irq(sbd, &s->irq[1]);
1171
1288
1172
1289
qemu_macaddr_default_if_unset(&s->conf.macaddr);
1173
-
1174
-
s->conf.peers.ncs[0] = nd_table[0].netdev;
1175
1290
1176
1291
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
1177
1292
object_get_typename(OBJECT(dev)),
···
1182
1297
1183
1298
static Property imx_eth_properties[] = {
1184
1299
DEFINE_NIC_PROPERTIES(IMXFECState, conf),
1300
+
DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
1185
1301
DEFINE_PROP_END_OF_LIST(),
1186
1302
};
1187
1303
+50
-28
hw/sd/pxa2xx_mmci.c
+50
-28
hw/sd/pxa2xx_mmci.c
···
19
19
#include "hw/qdev.h"
20
20
#include "hw/qdev-properties.h"
21
21
#include "qemu/error-report.h"
22
+
#include "qemu/log.h"
23
+
#include "trace.h"
22
24
23
25
#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
24
26
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
···
278
280
static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
279
281
{
280
282
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
281
-
uint32_t ret;
283
+
uint32_t ret = 0;
282
284
283
285
switch (offset) {
284
286
case MMC_STRPCL:
285
-
return 0;
287
+
break;
286
288
case MMC_STAT:
287
-
return s->status;
289
+
ret = s->status;
290
+
break;
288
291
case MMC_CLKRT:
289
-
return s->clkrt;
292
+
ret = s->clkrt;
293
+
break;
290
294
case MMC_SPI:
291
-
return s->spi;
295
+
ret = s->spi;
296
+
break;
292
297
case MMC_CMDAT:
293
-
return s->cmdat;
298
+
ret = s->cmdat;
299
+
break;
294
300
case MMC_RESTO:
295
-
return s->resp_tout;
301
+
ret = s->resp_tout;
302
+
break;
296
303
case MMC_RDTO:
297
-
return s->read_tout;
304
+
ret = s->read_tout;
305
+
break;
298
306
case MMC_BLKLEN:
299
-
return s->blklen;
307
+
ret = s->blklen;
308
+
break;
300
309
case MMC_NUMBLK:
301
-
return s->numblk;
310
+
ret = s->numblk;
311
+
break;
302
312
case MMC_PRTBUF:
303
-
return 0;
313
+
break;
304
314
case MMC_I_MASK:
305
-
return s->intmask;
315
+
ret = s->intmask;
316
+
break;
306
317
case MMC_I_REG:
307
-
return s->intreq;
318
+
ret = s->intreq;
319
+
break;
308
320
case MMC_CMD:
309
-
return s->cmd | 0x40;
321
+
ret = s->cmd | 0x40;
322
+
break;
310
323
case MMC_ARGH:
311
-
return s->arg >> 16;
324
+
ret = s->arg >> 16;
325
+
break;
312
326
case MMC_ARGL:
313
-
return s->arg & 0xffff;
327
+
ret = s->arg & 0xffff;
328
+
break;
314
329
case MMC_RES:
315
-
if (s->resp_len < 9)
316
-
return s->resp_fifo[s->resp_len ++];
317
-
return 0;
330
+
ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
331
+
break;
318
332
case MMC_RXFIFO:
319
-
ret = 0;
320
333
while (size-- && s->rx_len) {
321
334
ret |= s->rx_fifo[s->rx_start++] << (size << 3);
322
335
s->rx_start &= 0x1f;
···
324
337
}
325
338
s->intreq &= ~INT_RXFIFO_REQ;
326
339
pxa2xx_mmci_fifo_update(s);
327
-
return ret;
340
+
break;
328
341
case MMC_RDWAIT:
329
-
return 0;
342
+
break;
330
343
case MMC_BLKS_REM:
331
-
return s->numblk;
344
+
ret = s->numblk;
345
+
break;
332
346
default:
333
-
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
347
+
qemu_log_mask(LOG_GUEST_ERROR,
348
+
"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
349
+
__func__, offset);
334
350
}
351
+
trace_pxa2xx_mmci_read(size, offset, ret);
335
352
336
-
return 0;
353
+
return ret;
337
354
}
338
355
339
356
static void pxa2xx_mmci_write(void *opaque,
···
341
358
{
342
359
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
343
360
361
+
trace_pxa2xx_mmci_write(size, offset, value);
344
362
switch (offset) {
345
363
case MMC_STRPCL:
346
364
if (value & STRPCL_STRT_CLK) {
···
368
386
369
387
case MMC_SPI:
370
388
s->spi = value & 0xf;
371
-
if (value & SPI_SPI_MODE)
372
-
printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
389
+
if (value & SPI_SPI_MODE) {
390
+
qemu_log_mask(LOG_GUEST_ERROR,
391
+
"%s: attempted to use card in SPI mode\n", __func__);
392
+
}
373
393
break;
374
394
375
395
case MMC_CMDAT:
···
442
462
break;
443
463
444
464
default:
445
-
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
465
+
qemu_log_mask(LOG_GUEST_ERROR,
466
+
"%s: incorrect reg 0x%02" HWADDR_PRIx " "
467
+
"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
446
468
}
447
469
}
448
470
+4
hw/sd/trace-events
+4
hw/sd/trace-events
···
3
3
# hw/sd/milkymist-memcard.c
4
4
milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
5
5
milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
6
+
7
+
# hw/sd/pxa2xx_mmci.c
8
+
pxa2xx_mmci_read(uint8_t size, uint32_t addr, uint32_t value) "size %d addr 0x%02x value 0x%08x"
9
+
pxa2xx_mmci_write(uint8_t size, uint32_t addr, uint32_t value) "size %d addr 0x%02x value 0x%08x"
+15
-2
hw/timer/pxa2xx_timer.c
+15
-2
hw/timer/pxa2xx_timer.c
···
13
13
#include "sysemu/sysemu.h"
14
14
#include "hw/arm/pxa.h"
15
15
#include "hw/sysbus.h"
16
+
#include "qemu/log.h"
16
17
17
18
#define OSMR0 0x00
18
19
#define OSMR1 0x04
···
252
253
case OSNR:
253
254
return s->snapshot;
254
255
default:
256
+
qemu_log_mask(LOG_UNIMP,
257
+
"%s: unknown register 0x%02" HWADDR_PRIx "\n",
258
+
__func__, offset);
259
+
break;
255
260
badreg:
256
-
hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
261
+
qemu_log_mask(LOG_GUEST_ERROR,
262
+
"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
263
+
__func__, offset);
257
264
}
258
265
259
266
return 0;
···
377
384
}
378
385
break;
379
386
default:
387
+
qemu_log_mask(LOG_UNIMP,
388
+
"%s: unknown register 0x%02" HWADDR_PRIx " "
389
+
"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
390
+
break;
380
391
badreg:
381
-
hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
392
+
qemu_log_mask(LOG_GUEST_ERROR,
393
+
"%s: incorrect register 0x%02" HWADDR_PRIx " "
394
+
"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
382
395
}
383
396
}
384
397
-1
include/hw/arm/fsl-imx25.h
-1
include/hw/arm/fsl-imx25.h
···
192
192
#define FSL_IMX25_UART5_ADDR 0x5002C000
193
193
#define FSL_IMX25_UART5_SIZE 0x4000
194
194
#define FSL_IMX25_FEC_ADDR 0x50038000
195
-
#define FSL_IMX25_FEC_SIZE 0x4000
196
195
#define FSL_IMX25_CCM_ADDR 0x53F80000
197
196
#define FSL_IMX25_CCM_SIZE 0x4000
198
197
#define FSL_IMX25_GPT4_ADDR 0x53F84000
+24
-3
include/hw/net/imx_fec.h
+24
-3
include/hw/net/imx_fec.h
···
52
52
#define ENET_TFWR 81
53
53
#define ENET_FRBR 83
54
54
#define ENET_FRSR 84
55
+
#define ENET_TDSR1 89
56
+
#define ENET_TDSR2 92
55
57
#define ENET_RDSR 96
56
58
#define ENET_TDSR 97
57
59
#define ENET_MRBR 98
···
66
68
#define ENET_FTRL 108
67
69
#define ENET_TACC 112
68
70
#define ENET_RACC 113
71
+
#define ENET_TDAR1 121
72
+
#define ENET_TDAR2 123
69
73
#define ENET_MIIGSK_CFGR 192
70
74
#define ENET_MIIGSK_ENR 194
71
75
#define ENET_ATCR 256
···
86
90
#define ENET_TCCR3 393
87
91
#define ENET_MAX 400
88
92
89
-
#define ENET_MAX_FRAME_SIZE 2032
90
93
91
94
/* EIR and EIMR */
92
95
#define ENET_INT_HB (1 << 31)
···
106
109
#define ENET_INT_WAKEUP (1 << 17)
107
110
#define ENET_INT_TS_AVAIL (1 << 16)
108
111
#define ENET_INT_TS_TIMER (1 << 15)
112
+
#define ENET_INT_TXF2 (1 << 7)
113
+
#define ENET_INT_TXB2 (1 << 6)
114
+
#define ENET_INT_TXF1 (1 << 3)
115
+
#define ENET_INT_TXB1 (1 << 2)
109
116
110
117
#define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \
111
118
ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \
112
119
ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \
113
120
ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \
114
121
ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \
115
-
ENET_INT_TS_AVAIL)
122
+
ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \
123
+
ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2)
116
124
117
125
/* RDAR */
118
126
#define ENET_RDAR_RDAR (1 << 24)
···
154
162
#define ENET_RCR_MAX_FL_LENGTH (14)
155
163
#define ENET_RCR_NLC (1 << 30)
156
164
#define ENET_RCR_GRS (1 << 31)
165
+
166
+
#define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH)
157
167
158
168
/* TCR */
159
169
#define ENET_TCR_GTS (1 << 0)
···
169
179
#define ENET_TWFR_TFWR_LENGTH (6)
170
180
#define ENET_TWFR_STRFWD (1 << 8)
171
181
182
+
#define ENET_RACC_SHIFT16 BIT(7)
183
+
172
184
/* Buffer Descriptor. */
173
185
typedef struct {
174
186
uint16_t length;
···
231
243
232
244
#define ENET_BD_BDU (1 << 31)
233
245
246
+
#define ENET_TX_RING_NUM 3
247
+
248
+
#define FSL_IMX25_FEC_SIZE 0x4000
249
+
234
250
typedef struct IMXFECState {
235
251
/*< private >*/
236
252
SysBusDevice parent_obj;
···
243
259
244
260
uint32_t regs[ENET_MAX];
245
261
uint32_t rx_descriptor;
246
-
uint32_t tx_descriptor;
262
+
263
+
uint32_t tx_descriptor[ENET_TX_RING_NUM];
264
+
uint32_t tx_ring_num;
247
265
248
266
uint32_t phy_status;
249
267
uint32_t phy_control;
···
252
270
uint32_t phy_int_mask;
253
271
254
272
bool is_fec;
273
+
274
+
/* Buffer used to assemble a Tx frame */
275
+
uint8_t frame[ENET_MAX_FRAME_SIZE];
255
276
} IMXFECState;
256
277
257
278
#endif
+4
linux-user/aarch64/target_syscall.h
+4
linux-user/aarch64/target_syscall.h
+9
linux-user/arm/nwfpe/fpa11.c
+9
linux-user/arm/nwfpe/fpa11.c
···
137
137
unsigned int nRc = 0;
138
138
// unsigned long flags;
139
139
FPA11 *fpa11;
140
+
unsigned int cp;
140
141
// save_flags(flags); sti();
142
+
143
+
/* Check that this is really an FPA11 instruction: the coprocessor
144
+
* field in bits [11:8] must be 1 or 2.
145
+
*/
146
+
cp = (opcode >> 8) & 0xf;
147
+
if (cp != 1 && cp != 2) {
148
+
return 0;
149
+
}
141
150
142
151
qemufpa=qfpa;
143
152
user_registers=qregs;
+6
linux-user/main.c
+6
linux-user/main.c
···
4629
4629
}
4630
4630
env->pc = regs->pc;
4631
4631
env->xregs[31] = regs->sp;
4632
+
#ifdef TARGET_WORDS_BIGENDIAN
4633
+
env->cp15.sctlr_el[1] |= SCTLR_E0E;
4634
+
for (i = 1; i < 4; ++i) {
4635
+
env->cp15.sctlr_el[i] |= SCTLR_EE;
4636
+
}
4637
+
#endif
4632
4638
}
4633
4639
#elif defined(TARGET_ARM)
4634
4640
{
+7
-3
linux-user/signal.c
+7
-3
linux-user/signal.c
···
1599
1599
if (ka->sa_flags & TARGET_SA_RESTORER) {
1600
1600
return_addr = ka->sa_restorer;
1601
1601
} else {
1602
-
/* mov x8,#__NR_rt_sigreturn; svc #0 */
1603
-
__put_user(0xd2801168, &frame->tramp[0]);
1604
-
__put_user(0xd4000001, &frame->tramp[1]);
1602
+
/*
1603
+
* mov x8,#__NR_rt_sigreturn; svc #0
1604
+
* Since these are instructions they need to be put as little-endian
1605
+
* regardless of target default or current CPU endianness.
1606
+
*/
1607
+
__put_user_e(0xd2801168, &frame->tramp[0], le);
1608
+
__put_user_e(0xd4000001, &frame->tramp[1], le);
1605
1609
return_addr = frame_addr + offsetof(struct target_rt_sigframe, tramp);
1606
1610
}
1607
1611
env->xregs[0] = usig;
+11
-4
scripts/qemu-binfmt-conf.sh
+11
-4
scripts/qemu-binfmt-conf.sh
···
2
2
# enable automatic i386/ARM/M68K/MIPS/SPARC/PPC/s390/HPPA
3
3
# program execution by the kernel
4
4
5
-
qemu_target_list="i386 i486 alpha arm sparc32plus ppc ppc64 ppc64le m68k \
5
+
qemu_target_list="i386 i486 alpha arm armeb sparc32plus ppc ppc64 ppc64le m68k \
6
6
mips mipsel mipsn32 mipsn32el mips64 mips64el \
7
-
sh4 sh4eb s390x aarch64 hppa"
7
+
sh4 sh4eb s390x aarch64 aarch64_be hppa"
8
8
9
9
i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00'
10
10
i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
···
24
24
25
25
armeb_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x28'
26
26
armeb_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff'
27
-
armeb_family=arm
27
+
armeb_family=armeb
28
28
29
29
sparc_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x02'
30
30
sparc_mask='\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff'
···
92
92
aarch64_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
93
93
aarch64_family=arm
94
94
95
+
aarch64_be_magic='\x7fELF\x02\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xb7'
96
+
aarch64_be_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff'
97
+
aarch64_be_family=armeb
98
+
95
99
hppa_magic='\x7f\x45\x4c\x46\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x0f'
96
100
hppa_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff'
97
101
hppa_family=hppa
···
111
115
ppc64el|ppc64le)
112
116
echo "ppcle"
113
117
;;
114
-
arm|armel|armhf|arm64|armv[4-9]*)
118
+
arm|armel|armhf|arm64|armv[4-9]*l|aarch64)
115
119
echo "arm"
120
+
;;
121
+
armeb|armv[4-9]*b|aarch64_be)
122
+
echo "armeb"
116
123
;;
117
124
sparc*)
118
125
echo "sparc"
+5
-2
target/arm/helper-a64.c
+5
-2
target/arm/helper-a64.c
···
506
506
Int128 oldv, cmpv, newv;
507
507
bool success;
508
508
509
-
cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
510
-
newv = int128_make128(new_lo, new_hi);
509
+
/* high and low need to be switched here because this is not actually a
510
+
* 128bit store but two doublewords stored consecutively
511
+
*/
512
+
cmpv = int128_make128(env->exclusive_high, env->exclusive_val);
513
+
newv = int128_make128(new_hi, new_lo);
511
514
512
515
if (parallel) {
513
516
#ifndef CONFIG_ATOMIC128
+10
-13
target/arm/translate.c
+10
-13
target/arm/translate.c
···
9775
9775
return 0;
9776
9776
}
9777
9777
9778
-
/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
9779
-
is not legal. */
9780
-
static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
9778
+
/* Translate a 32-bit thumb instruction. */
9779
+
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
9781
9780
{
9782
9781
uint32_t imm, shift, offset;
9783
9782
uint32_t rd, rn, rm, rs;
···
11016
11015
/* UNPREDICTABLE, unallocated hint or
11017
11016
* PLD/PLDW/PLI (literal)
11018
11017
*/
11019
-
return 0;
11018
+
return;
11020
11019
}
11021
11020
if (op1 & 1) {
11022
-
return 0; /* PLD/PLDW/PLI or unallocated hint */
11021
+
return; /* PLD/PLDW/PLI or unallocated hint */
11023
11022
}
11024
11023
if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
11025
-
return 0; /* PLD/PLDW/PLI or unallocated hint */
11024
+
return; /* PLD/PLDW/PLI or unallocated hint */
11026
11025
}
11027
11026
/* UNDEF space, or an UNPREDICTABLE */
11028
-
return 1;
11027
+
goto illegal_op;
11029
11028
}
11030
11029
}
11031
11030
memidx = get_mem_index(s);
···
11151
11150
default:
11152
11151
goto illegal_op;
11153
11152
}
11154
-
return 0;
11153
+
return;
11155
11154
illegal_op:
11156
-
return 1;
11155
+
gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
11156
+
default_exception_el(s));
11157
11157
}
11158
11158
11159
11159
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
···
12275
12275
if (is_16bit) {
12276
12276
disas_thumb_insn(dc, insn);
12277
12277
} else {
12278
-
if (disas_thumb2_insn(dc, insn)) {
12279
-
gen_exception_insn(dc, 4, EXCP_UDEF, syn_uncategorized(),
12280
-
default_exception_el(dc));
12281
-
}
12278
+
disas_thumb2_insn(dc, insn);
12282
12279
}
12283
12280
12284
12281
/* Advance the Thumb condexec condition. */