+9

HACKING

··· 118 118 is no need to test for failure (as you would have to with malloc). 119 119 Calling g_malloc with a zero size is valid and will return NULL. 120 120 121 121 + Prefer g_new(T, n) instead of g_malloc(sizeof(T) * n) for the following 122 122 + reasons: 123 123 + 124 124 + a. It catches multiplication overflowing size_t; 125 125 + b. It returns T * instead of void *, letting compiler catch more type 126 126 + errors. 127 127 + 128 128 + Declarations like T *v = g_malloc(sizeof(*v)) are acceptable, though. 129 129 + 121 130 Memory allocated by qemu_memalign or qemu_blockalign must be freed with 122 131 qemu_vfree, since breaking this will cause problems on Win32. 123 132

+1 -4

accel/tcg/translate-all.c

··· 644 644 static inline void *alloc_code_gen_buffer(void) 645 645 { 646 646 size_t size = tcg_ctx->code_gen_buffer_size; 647 647 - void *buf; 648 648 - 649 649 - buf = VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, 647 647 + return VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, 650 648 PAGE_EXECUTE_READWRITE); 651 651 - return buf; 652 649 } 653 650 #else 654 651 static inline void *alloc_code_gen_buffer(void)

+2 -4

block/quorum.c

··· 613 613 static int read_quorum_children(QuorumAIOCB *acb) 614 614 { 615 615 BDRVQuorumState *s = acb->bs->opaque; 616 616 - int i, ret; 616 616 + int i; 617 617 618 618 acb->children_read = s->num_children; 619 619 for (i = 0; i < s->num_children; i++) { ··· 648 648 qemu_coroutine_yield(); 649 649 } 650 650 651 651 - ret = acb->vote_ret; 652 652 - 653 653 - return ret; 651 651 + return acb->vote_ret; 654 652 } 655 653 656 654 static int read_fifo_child(QuorumAIOCB *acb)

+14 -10

gdbstub.c

··· 1814 1814 put_packet(s, buf); 1815 1815 } 1816 1816 1817 1817 - static void gdb_accept(void) 1817 1817 + static bool gdb_accept(void) 1818 1818 { 1819 1819 GDBState *s; 1820 1820 struct sockaddr_in sockaddr; ··· 1826 1826 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len); 1827 1827 if (fd < 0 && errno != EINTR) { 1828 1828 perror("accept"); 1829 1829 - return; 1829 1829 + return false; 1830 1830 } else if (fd >= 0) { 1831 1831 - #ifndef _WIN32 1832 1832 - fcntl(fd, F_SETFD, FD_CLOEXEC); 1833 1833 - #endif 1831 1831 + qemu_set_cloexec(fd); 1834 1832 break; 1835 1833 } 1836 1834 } 1837 1835 1838 1836 /* set short latency */ 1839 1839 - socket_set_nodelay(fd); 1837 1837 + if (socket_set_nodelay(fd)) { 1838 1838 + perror("setsockopt"); 1839 1839 + return false; 1840 1840 + } 1840 1841 1841 1842 s = g_malloc0(sizeof(GDBState)); 1842 1843 s->c_cpu = first_cpu; ··· 1845 1846 gdb_has_xml = false; 1846 1847 1847 1848 gdbserver_state = s; 1849 1849 + return true; 1848 1850 } 1849 1851 1850 1852 static int gdbserver_open(int port) ··· 1857 1859 perror("socket"); 1858 1860 return -1; 1859 1861 } 1860 1860 - #ifndef _WIN32 1861 1861 - fcntl(fd, F_SETFD, FD_CLOEXEC); 1862 1862 - #endif 1862 1862 + qemu_set_cloexec(fd); 1863 1863 1864 1864 socket_set_fast_reuse(fd); 1865 1865 ··· 1887 1887 if (gdbserver_fd < 0) 1888 1888 return -1; 1889 1889 /* accept connections */ 1890 1890 - gdb_accept(); 1890 1890 + if (!gdb_accept()) { 1891 1891 + close(gdbserver_fd); 1892 1892 + gdbserver_fd = -1; 1893 1893 + return -1; 1894 1894 + } 1891 1895 return 0; 1892 1896 } 1893 1897

+1 -1

hw/acpi/aml-build.c

··· 627 627 return var; 628 628 } 629 629 630 630 - /* helper to call method with 1 argument */ 630 630 + /* helper to call method without argument */ 631 631 Aml *aml_call0(const char *method) 632 632 { 633 633 Aml *var = aml_alloc();

+1 -5

hw/arm/exynos4210.c

··· 156 156 157 157 static uint64_t exynos4210_calc_affinity(int cpu) 158 158 { 159 159 - uint64_t mp_affinity; 160 160 - 161 159 /* Exynos4210 has 0x9 as cluster ID */ 162 162 - mp_affinity = (0x9 << ARM_AFF1_SHIFT) | cpu; 163 163 - 164 164 - return mp_affinity; 160 160 + return (0x9 << ARM_AFF1_SHIFT) | cpu; 165 161 } 166 162 167 163 Exynos4210State *exynos4210_init(MemoryRegion *system_mem)

+1 -4

hw/block/vhost-user-blk.c

··· 196 196 Error **errp) 197 197 { 198 198 VHostUserBlk *s = VHOST_USER_BLK(vdev); 199 199 - uint64_t get_features; 200 199 201 200 /* Turn on pre-defined features */ 202 201 virtio_add_feature(&features, VIRTIO_BLK_F_SEG_MAX); ··· 215 214 virtio_add_feature(&features, VIRTIO_BLK_F_MQ); 216 215 } 217 216 218 218 - get_features = vhost_get_features(&s->dev, user_feature_bits, features); 219 219 - 220 220 - return get_features; 217 217 + return vhost_get_features(&s->dev, user_feature_bits, features); 221 218 } 222 219 223 220 static void vhost_user_blk_handle_output(VirtIODevice *vdev, VirtQueue *vq)

+1 -4

hw/hppa/dino.c

··· 403 403 static int dino_pci_map_irq(PCIDevice *d, int irq_num) 404 404 { 405 405 int slot = d->devfn >> 3; 406 406 - int local_irq; 407 406 408 407 assert(irq_num >= 0 && irq_num <= 3); 409 408 410 410 - local_irq = slot & 0x03; 411 411 - 412 412 - return local_irq; 409 409 + return slot & 0x03; 413 410 } 414 411 415 412 static void dino_set_timer_irq(void *opaque, int irq, int level)

+3

hw/ide/ahci-allwinner.c

··· 24 24 25 25 #include "trace.h" 26 26 27 27 + #define ALLWINNER_AHCI(obj) \ 28 28 + OBJECT_CHECK(AllwinnerAHCIState, (obj), TYPE_ALLWINNER_AHCI) 29 29 + 27 30 #define ALLWINNER_AHCI_BISTAFR ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4) 28 31 #define ALLWINNER_AHCI_BISTCR ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4) 29 32 #define ALLWINNER_AHCI_BISTFCTR ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4)

-3

hw/ide/ahci_internal.h

··· 375 375 376 376 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI) 377 377 378 378 - #define ALLWINNER_AHCI(obj) OBJECT_CHECK(AllwinnerAHCIState, (obj), \ 379 379 - TYPE_ALLWINNER_AHCI) 380 380 - 381 378 #endif /* HW_IDE_AHCI_H */

+2 -2

hw/ide/trace-events

··· 108 108 ahci_dma_rw_buf(void *s, int port, int l) "ahci(%p)[%d] len=0x%x" 109 109 ahci_cmd_done(void *s, int port) "ahci(%p)[%d]: cmd done" 110 110 ahci_reset(void *s) "ahci(%p): HBA reset" 111 111 - allwinner_ahci_mem_read(void *s, void *a, uint64_t addr, uint64_t val, unsigned size) "ahci(%p): read a=%p addr=0x%"HWADDR_PRIx" val=0x%"PRIx64", size=%d" 112 112 - allwinner_ahci_mem_write(void *s, void *a, uint64_t addr, uint64_t val, unsigned size) "ahci(%p): write a=%p addr=0x%"HWADDR_PRIx" val=0x%"PRIx64", size=%d" 111 111 + allwinner_ahci_mem_read(void *s, void *a, uint64_t addr, uint64_t val, unsigned size) "ahci(%p): read a=%p addr=0x%"PRIx64" val=0x%"PRIx64", size=%d" 112 112 + allwinner_ahci_mem_write(void *s, void *a, uint64_t addr, uint64_t val, unsigned size) "ahci(%p): write a=%p addr=0x%"PRIx64" val=0x%"PRIx64", size=%d" 113 113 114 114 # Warning: Verbose 115 115 handle_reg_h2d_fis_dump(void *s, int port, const char *fis) "ahci(%p)[%d]: %s"

+2 -6

hw/misc/mos6522.c

··· 176 176 177 177 static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti) 178 178 { 179 179 - uint64_t d; 180 180 - 181 181 - d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 182 182 - ti->frequency, NANOSECONDS_PER_SECOND); 183 183 - 184 184 - return d; 179 179 + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, 180 180 + ti->frequency, NANOSECONDS_PER_SECOND); 185 181 } 186 182 187 183 static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti)

+4 -4

hw/misc/trace-events

··· 69 69 mps2_fpgaio_leds(char led1, char led0) "MPS2 FPGAIO LEDs: %c%c" 70 70 71 71 # hw/misc/msf2-sysreg.c 72 72 - msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32 73 73 - msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32 72 72 + msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" PRIx64 " data 0x%" PRIx32 " prev 0x%" PRIx32 73 73 + msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" PRIx64 " data 0x%08" PRIx32 74 74 msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register" 75 75 76 76 #hw/misc/imx7_gpr.c 77 77 - imx7_gpr_read(uint64_t offset) "addr 0x%08" HWADDR_PRIx 78 78 - imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" HWADDR_PRIx "value 0x%08" HWADDR_PRIx 77 77 + imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 78 78 + imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64 79 79 80 80 # hw/misc/mos6522.c 81 81 mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d"

+1 -4

hw/net/ftgmac100.c

··· 511 511 512 512 uint32_t cnt = 1024 * FTGMAC100_APTC_RXPOLL_CNT(s->aptcr); 513 513 uint32_t speed = (s->maccr & FTGMAC100_MACCR_FAST_MODE) ? 1 : 0; 514 514 - uint32_t period; 515 514 516 515 if (s->aptcr & FTGMAC100_APTC_RXPOLL_TIME_SEL) { 517 516 cnt <<= 4; ··· 521 520 speed = 2; 522 521 } 523 522 524 524 - period = cnt / div[speed]; 525 525 - 526 526 - return period; 523 523 + return cnt / div[speed]; 527 524 } 528 525 529 526 static void ftgmac100_reset(DeviceState *d)

+4 -12

hw/ppc/pnv_lpc.c

··· 125 125 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 126 126 int sz) 127 127 { 128 128 - bool success; 129 129 - 130 128 /* XXX Handle access size limits and FW read caching here */ 131 131 - success = !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 132 132 - data, sz, false); 133 133 - 134 134 - return success; 129 129 + return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 130 130 + data, sz, false); 135 131 } 136 132 137 133 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 138 134 int sz) 139 135 { 140 140 - bool success; 141 141 - 142 136 /* XXX Handle access size limits here */ 143 143 - success = !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 144 144 - data, sz, true); 145 145 - 146 146 - return success; 137 137 + return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 138 138 + data, sz, true); 147 139 } 148 140 149 141 #define ECCB_CTL_READ PPC_BIT(15)

+3 -6

hw/timer/m48t59-internal.h

··· 25 25 #ifndef HW_M48T59_INTERNAL_H 26 26 #define HW_M48T59_INTERNAL_H 1 27 27 28 28 - //#define DEBUG_NVRAM 28 28 + #define M48T59_DEBUG 0 29 29 30 30 - #if defined(DEBUG_NVRAM) 31 31 - #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) 32 32 - #else 33 33 - #define NVRAM_PRINTF(fmt, ...) do { } while (0) 34 34 - #endif 30 30 + #define NVRAM_PRINTF(fmt, ...) do { \ 31 31 + if (M48T59_DEBUG) { printf(fmt , ## __VA_ARGS__); } } while (0) 35 32 36 33 /* 37 34 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has

+2 -2

hw/timer/m48t59.c

··· 456 456 { 457 457 M48t59State *NVRAM = opaque; 458 458 459 459 - NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); 459 459 + NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" => 0x%"PRIx64"\n", __func__, addr, val); 460 460 switch (addr) { 461 461 case 0: 462 462 NVRAM->addr &= ~0x00FF; ··· 488 488 retval = -1; 489 489 break; 490 490 } 491 491 - NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); 491 491 + NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" <= 0x%08x\n", __func__, addr, retval); 492 492 493 493 return retval; 494 494 }

-2

include/hw/ppc/ppc4xx.h

··· 25 25 #ifndef PPC4XX_H 26 26 #define PPC4XX_H 27 27 28 28 - #include "hw/pci/pci.h" 29 29 - 30 28 /* PowerPC 4xx core initialization */ 31 29 PowerPCCPU *ppc4xx_init(const char *cpu_model, 32 30 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,

-1

include/hw/virtio/virtio-balloon.h

··· 17 17 18 18 #include "standard-headers/linux/virtio_balloon.h" 19 19 #include "hw/virtio/virtio.h" 20 20 - #include "hw/pci/pci.h" 21 20 22 21 #define TYPE_VIRTIO_BALLOON "virtio-balloon-device" 23 22 #define VIRTIO_BALLOON(obj) \

-1

include/hw/virtio/virtio-gpu.h

··· 18 18 #include "ui/qemu-pixman.h" 19 19 #include "ui/console.h" 20 20 #include "hw/virtio/virtio.h" 21 21 - #include "hw/pci/pci.h" 22 21 #include "qemu/log.h" 23 22 24 23 #include "standard-headers/linux/virtio_gpu.h"

-1

include/qemu/typedefs.h

··· 62 62 typedef struct NetFilterState NetFilterState; 63 63 typedef struct NICInfo NICInfo; 64 64 typedef struct NumaNodeMem NumaNodeMem; 65 65 - typedef struct PcGuestInfo PcGuestInfo; 66 65 typedef struct PCIBridge PCIBridge; 67 66 typedef struct PCIBus PCIBus; 68 67 typedef struct PCIDevice PCIDevice;

+1 -5

io/net-listener.c

··· 25 25 26 26 QIONetListener *qio_net_listener_new(void) 27 27 { 28 28 - QIONetListener *ret; 29 29 - 30 30 - ret = QIO_NET_LISTENER(object_new(TYPE_QIO_NET_LISTENER)); 31 31 - 32 32 - return ret; 28 28 + return QIO_NET_LISTENER(object_new(TYPE_QIO_NET_LISTENER)); 33 29 } 34 30 35 31 void qio_net_listener_set_name(QIONetListener *listener,

+2 -2

qapi/net.json

··· 450 450 # 451 451 # Since: 2.7 452 452 # 453 453 - # 'dump' - removed with 2.12 453 453 + # 'dump': dropped in 2.12 454 454 ## 455 455 { 'enum': 'NetClientDriver', 456 456 'data': [ 'none', 'nic', 'user', 'tap', 'l2tpv3', 'socket', 'vde', ··· 498 498 # 499 499 # Since: 1.2 500 500 # 501 501 - # 'vlan' - removed with 2.12 501 501 + # 'vlan': dropped in 2.13 502 502 ## 503 503 { 'struct': 'NetLegacy', 504 504 'data': {

+8 -5

qemu-img-cmds.hx

··· 6 6 HXCOMM command structures and help message. 7 7 HXCOMM HXCOMM can be used for comments, discarded from both texi and C 8 8 9 9 + HXCOMM When amending the TEXI sections, please remember to copy the usage 10 10 + HXCOMM over to the per-command sections in qemu-img.texi. 11 11 + 9 12 STEXI 10 13 @table @option 11 14 ETEXI ··· 23 26 ETEXI 24 27 25 28 DEF("check", img_check, 26 26 - "check [-q] [--object objectdef] [--image-opts] [-f fmt] [--output=ofmt] [-r [leaks | all]] [-T src_cache] [-U] filename") 29 29 + "check [--object objectdef] [--image-opts] [-q] [-f fmt] [--output=ofmt] [-r [leaks | all]] [-T src_cache] [-U] filename") 27 30 STEXI 28 31 @item check [--object @var{objectdef}] [--image-opts] [-q] [-f @var{fmt}] [--output=@var{ofmt}] [-r [leaks | all]] [-T @var{src_cache}] [-U] @var{filename} 29 32 ETEXI 30 33 31 34 DEF("commit", img_commit, 32 32 - "commit [-q] [--object objectdef] [--image-opts] [-f fmt] [-t cache] [-b base] [-d] [-p] filename") 35 35 + "commit [--object objectdef] [--image-opts] [-q] [-f fmt] [-t cache] [-b base] [-d] [-p] filename") 33 36 STEXI 34 37 @item commit [--object @var{objectdef}] [--image-opts] [-q] [-f @var{fmt}] [-t @var{cache}] [-b @var{base}] [-d] [-p] @var{filename} 35 38 ETEXI ··· 47 50 ETEXI 48 51 49 52 DEF("create", img_create, 50 50 - "create [-q] [--object objectdef] [-f fmt] [-b backing_file] [-F backing_fmt] [-u] [-o options] filename [size]") 53 53 + "create [--object objectdef] [-q] [-f fmt] [-b backing_file] [-F backing_fmt] [-u] [-o options] filename [size]") 51 54 STEXI 52 55 @item create [--object @var{objectdef}] [-q] [-f @var{fmt}] [-b @var{backing_file}] [-F @var{backing_fmt}] [-u] [-o @var{options}] @var{filename} [@var{size}] 53 56 ETEXI ··· 89 92 ETEXI 90 93 91 94 DEF("resize", img_resize, 92 92 - "resize [--object objectdef] [--image-opts] [-q] [--shrink] filename [+ | -]size") 95 95 + "resize [--object objectdef] [--image-opts] [-f fmt] [--preallocation=prealloc] [-q] [--shrink] filename [+ | -]size") 93 96 STEXI 94 94 - @item resize [--object @var{objectdef}] [--image-opts] [-q] [--shrink] @var{filename} [+ | -]@var{size} 97 97 + @item resize [--object @var{objectdef}] [--image-opts] [-f @var{fmt}] [--preallocation=@var{prealloc}] [-q] [--shrink] @var{filename} [+ | -]@var{size} 95 98 ETEXI 96 99 97 100 STEXI

-2

qemu-img.c

··· 123 123 " " arg_string "\n" 124 124 #include "qemu-img-cmds.h" 125 125 #undef DEF 126 126 - #undef GEN_DOCS 127 126 "\n" 128 127 "Command parameters:\n" 129 128 " 'filename' is a disk image filename\n" ··· 4716 4715 { option, callback }, 4717 4716 #include "qemu-img-cmds.h" 4718 4717 #undef DEF 4719 4719 - #undef GEN_DOCS 4720 4718 { NULL, NULL, }, 4721 4719 }; 4722 4720

+40 -38

qemu-img.texi

··· 193 193 Command description: 194 194 195 195 @table @option 196 196 - @item bench [-c @var{count}] [-d @var{depth}] [-f @var{fmt}] [--flush-interval=@var{flush_interval}] [-n] [--no-drain] [-o @var{offset}] [--pattern=@var{pattern}] [-q] [-s @var{buffer_size}] [-S @var{step_size}] [-t @var{cache}] [-w] @var{filename} 196 196 + 197 197 + @item amend [--object @var{objectdef}] [--image-opts] [-p] [-p] [-f @var{fmt}] [-t @var{cache}] -o @var{options} @var{filename} 198 198 + 199 199 + Amends the image format specific @var{options} for the image file 200 200 + @var{filename}. Not all file formats support this operation. 201 201 + 202 202 + @item bench [-c @var{count}] [-d @var{depth}] [-f @var{fmt}] [--flush-interval=@var{flush_interval}] [-n] [--no-drain] [-o @var{offset}] [--pattern=@var{pattern}] [-q] [-s @var{buffer_size}] [-S @var{step_size}] [-t @var{cache}] [-w] [-U] @var{filename} 197 203 198 204 Run a simple sequential I/O benchmark on the specified image. If @code{-w} is 199 205 specified, a write test is performed, otherwise a read test is performed. ··· 217 223 For write tests, by default a buffer filled with zeros is written. This can be 218 224 overridden with a pattern byte specified by @var{pattern}. 219 225 220 220 - @item check [-f @var{fmt}] [--output=@var{ofmt}] [-r [leaks | all]] [-T @var{src_cache}] @var{filename} 226 226 + @item check [--object @var{objectdef}] [--image-opts] [-q] [-f @var{fmt}] [--output=@var{ofmt}] [-r [leaks | all]] [-T @var{src_cache}] [-U] @var{filename} 221 227 222 228 Perform a consistency check on the disk image @var{filename}. The command can 223 229 output in the format @var{ofmt} which is either @code{human} or @code{json}. ··· 253 259 state after (the attempt at) repairing it. That is, a successful @code{-r all} 254 260 will yield the exit code 0, independently of the image state before. 255 261 256 256 - @item create [-f @var{fmt}] [-b @var{backing_file}] [-F @var{backing_fmt}] [-u] [-o @var{options}] @var{filename} [@var{size}] 257 257 - 258 258 - Create the new disk image @var{filename} of size @var{size} and format 259 259 - @var{fmt}. Depending on the file format, you can add one or more @var{options} 260 260 - that enable additional features of this format. 261 261 - 262 262 - If the option @var{backing_file} is specified, then the image will record 263 263 - only the differences from @var{backing_file}. No size needs to be specified in 264 264 - this case. @var{backing_file} will never be modified unless you use the 265 265 - @code{commit} monitor command (or qemu-img commit). 266 266 - 267 267 - If a relative path name is given, the backing file is looked up relative to 268 268 - the directory containing @var{filename}. 269 269 - 270 270 - Note that a given backing file will be opened to check that it is valid. Use 271 271 - the @code{-u} option to enable unsafe backing file mode, which means that the 272 272 - image will be created even if the associated backing file cannot be opened. A 273 273 - matching backing file must be created or additional options be used to make the 274 274 - backing file specification valid when you want to use an image created this 275 275 - way. 276 276 - 277 277 - The size can also be specified using the @var{size} option with @code{-o}, 278 278 - it doesn't need to be specified separately in this case. 279 279 - 280 280 - @item commit [-q] [-f @var{fmt}] [-t @var{cache}] [-b @var{base}] [-d] [-p] @var{filename} 262 262 + @item commit [--object @var{objectdef}] [--image-opts] [-q] [-f @var{fmt}] [-t @var{cache}] [-b @var{base}] [-d] [-p] @var{filename} 281 263 282 264 Commit the changes recorded in @var{filename} in its base image or backing file. 283 265 If the backing file is smaller than the snapshot, then the backing file will be ··· 299 281 garbage data when read. For this reason, @code{-b} implies @code{-d} (so that 300 282 the top image stays valid). 301 283 302 302 - @item compare [-f @var{fmt}] [-F @var{fmt}] [-T @var{src_cache}] [-p] [-s] [-q] @var{filename1} @var{filename2} 284 284 + @item compare [--object @var{objectdef}] [--image-opts] [-f @var{fmt}] [-F @var{fmt}] [-T @var{src_cache}] [-p] [-q] [-s] [-U] @var{filename1} @var{filename2} 303 285 304 286 Check if two images have the same content. You can compare images with 305 287 different format or settings. ··· 340 322 341 323 @end table 342 324 343 343 - @item convert [-c] [-p] [-n] [-f @var{fmt}] [-t @var{cache}] [-T @var{src_cache}] [-O @var{output_fmt}] [-B @var{backing_file}] [-o @var{options}] [-s @var{snapshot_id_or_name}] [-l @var{snapshot_param}] [-m @var{num_coroutines}] [-W] [-S @var{sparse_size}] @var{filename} [@var{filename2} [...]] @var{output_filename} 325 325 + @item convert [--object @var{objectdef}] [--image-opts] [--target-image-opts] [-U] [-c] [-p] [-q] [-n] [-f @var{fmt}] [-t @var{cache}] [-T @var{src_cache}] [-O @var{output_fmt}] [-B @var{backing_file}] [-o @var{options}] [-s @var{snapshot_id_or_name}] [-l @var{snapshot_param}] [-S @var{sparse_size}] [-m @var{num_coroutines}] [-W] @var{filename} [@var{filename2} [...]] @var{output_filename} 344 326 345 327 Convert the disk image @var{filename} or a snapshot @var{snapshot_param}(@var{snapshot_id_or_name} is deprecated) 346 328 to disk image @var{output_filename} using format @var{output_fmt}. It can be optionally compressed (@code{-c} ··· 381 363 @var{num_coroutines} specifies how many coroutines work in parallel during 382 364 the convert process (defaults to 8). 383 365 384 384 - @item dd [-f @var{fmt}] [-O @var{output_fmt}] [bs=@var{block_size}] [count=@var{blocks}] [skip=@var{blocks}] if=@var{input} of=@var{output} 366 366 + @item create [--object @var{objectdef}] [-q] [-f @var{fmt}] [-b @var{backing_file}] [-F @var{backing_fmt}] [-u] [-o @var{options}] @var{filename} [@var{size}] 367 367 + 368 368 + Create the new disk image @var{filename} of size @var{size} and format 369 369 + @var{fmt}. Depending on the file format, you can add one or more @var{options} 370 370 + that enable additional features of this format. 371 371 + 372 372 + If the option @var{backing_file} is specified, then the image will record 373 373 + only the differences from @var{backing_file}. No size needs to be specified in 374 374 + this case. @var{backing_file} will never be modified unless you use the 375 375 + @code{commit} monitor command (or qemu-img commit). 376 376 + 377 377 + If a relative path name is given, the backing file is looked up relative to 378 378 + the directory containing @var{filename}. 379 379 + 380 380 + Note that a given backing file will be opened to check that it is valid. Use 381 381 + the @code{-u} option to enable unsafe backing file mode, which means that the 382 382 + image will be created even if the associated backing file cannot be opened. A 383 383 + matching backing file must be created or additional options be used to make the 384 384 + backing file specification valid when you want to use an image created this 385 385 + way. 386 386 + 387 387 + The size can also be specified using the @var{size} option with @code{-o}, 388 388 + it doesn't need to be specified separately in this case. 389 389 + 390 390 + @item dd [--image-opts] [-U] [-f @var{fmt}] [-O @var{output_fmt}] [bs=@var{block_size}] [count=@var{blocks}] [skip=@var{blocks}] if=@var{input} of=@var{output} 385 391 386 392 Dd copies from @var{input} file to @var{output} file converting it from 387 393 @var{fmt} format to @var{output_fmt} format. ··· 392 398 393 399 The size syntax is similar to dd(1)'s size syntax. 394 400 395 395 - @item info [-f @var{fmt}] [--output=@var{ofmt}] [--backing-chain] @var{filename} 401 401 + @item info [--object @var{objectdef}] [--image-opts] [-f @var{fmt}] [--output=@var{ofmt}] [--backing-chain] [-U] @var{filename} 396 402 397 403 Give information about the disk image @var{filename}. Use it in 398 404 particular to know the size reserved on disk which can be different ··· 500 506 occupy with the exception of internal snapshots, dirty bitmaps, vmstate data, 501 507 and other advanced image format features. 502 508 503 503 - @item snapshot [-l | -a @var{snapshot} | -c @var{snapshot} | -d @var{snapshot} ] @var{filename} 509 509 + @item snapshot [--object @var{objectdef}] [--image-opts] [-U] [-q] [-l | -a @var{snapshot} | -c @var{snapshot} | -d @var{snapshot}] @var{filename} 504 510 505 511 List, apply, create or delete snapshots in image @var{filename}. 506 512 507 507 - @item rebase [-f @var{fmt}] [-t @var{cache}] [-T @var{src_cache}] [-p] [-u] -b @var{backing_file} [-F @var{backing_fmt}] @var{filename} 513 513 + @item rebase [--object @var{objectdef}] [--image-opts] [-U] [-q] [-f @var{fmt}] [-t @var{cache}] [-T @var{src_cache}] [-p] [-u] -b @var{backing_file} [-F @var{backing_fmt}] @var{filename} 508 514 509 515 Changes the backing file of an image. Only the formats @code{qcow2} and 510 516 @code{qed} support changing the backing file. ··· 564 570 At this point, @code{modified.img} can be discarded, since 565 571 @code{base.img + diff.qcow2} contains the same information. 566 572 567 567 - @item resize [--shrink] [--preallocation=@var{prealloc}] @var{filename} [+ | -]@var{size} 573 573 + @item resize [--object @var{objectdef}] [--image-opts] [-f @var{fmt}] [--preallocation=@var{prealloc}] [-q] [--shrink] @var{filename} [+ | -]@var{size} 568 574 569 575 Change the disk image as if it had been created with @var{size}. 570 576 ··· 585 591 description in the @code{NOTES} section which values are allowed. Using this 586 592 option may result in slightly more data being allocated than necessary. 587 593 588 588 - @item amend [-p] [-f @var{fmt}] [-t @var{cache}] -o @var{options} @var{filename} 589 589 - 590 590 - Amends the image format specific @var{options} for the image file 591 591 - @var{filename}. Not all file formats support this operation. 592 594 @end table 593 595 @c man end 594 596

+2 -3

qemu-option-trace.texi

··· 2 2 3 3 @table @option 4 4 @item [enable=]@var{pattern} 5 5 - Immediately enable events matching @var{pattern}. 6 6 - The file must contain one event name (as listed in the @file{trace-events-all} 7 7 - file) per line; globbing patterns are accepted too. This option is only 5 5 + Immediately enable events matching @var{pattern} 6 6 + (either event name or a globbing pattern). This option is only 8 7 available if QEMU has been compiled with the @var{simple}, @var{log} 9 8 or @var{ftrace} tracing backend. To specify multiple events or patterns, 10 9 specify the @option{-trace} option multiple times.

-1

qemu-options-wrapper.h

··· 34 34 #undef DEF 35 35 #undef DEFHEADING 36 36 #undef ARCHHEADING 37 37 - #undef GEN_DOCS 38 37 39 38 #undef QEMU_OPTIONS_GENERATE_ENUM 40 39 #undef QEMU_OPTIONS_GENERATE_HELP

+2 -2

slirp/arp_table.c

··· 33 33 int i; 34 34 35 35 DEBUG_CALL("arp_table_add"); 36 36 - DEBUG_ARG("ip = 0x%x", ip_addr); 36 36 + DEBUG_ARG("ip = %s", inet_ntoa(*(struct in_addr *)&ip_addr)); 37 37 DEBUG_ARGS((dfd, " hw addr = %02x:%02x:%02x:%02x:%02x:%02x\n", 38 38 ethaddr[0], ethaddr[1], ethaddr[2], 39 39 ethaddr[3], ethaddr[4], ethaddr[5])); ··· 67 67 int i; 68 68 69 69 DEBUG_CALL("arp_table_search"); 70 70 - DEBUG_ARG("ip = 0x%x", ip_addr); 70 70 + DEBUG_ARG("ip = %s", inet_ntoa(*(struct in_addr *)&ip_addr)); 71 71 72 72 /* If broadcast address */ 73 73 if (ip_addr == 0xffffffff || ip_addr == broadcast_addr) {

+4 -4

slirp/socket.c

··· 701 701 memset(&addr, 0, addrlen); 702 702 703 703 DEBUG_CALL("tcp_listen"); 704 704 - DEBUG_ARG("haddr = %x", haddr); 705 705 - DEBUG_ARG("hport = %d", hport); 706 706 - DEBUG_ARG("laddr = %x", laddr); 707 707 - DEBUG_ARG("lport = %d", lport); 704 704 + DEBUG_ARG("haddr = %s", inet_ntoa(*(struct in_addr *)&haddr)); 705 705 + DEBUG_ARG("hport = %d", ntohs(hport)); 706 706 + DEBUG_ARG("laddr = %s", inet_ntoa(*(struct in_addr *)&laddr)); 707 707 + DEBUG_ARG("lport = %d", ntohs(lport)); 708 708 DEBUG_ARG("flags = %x", flags); 709 709 710 710 so = socreate(slirp);

+2 -2

slirp/udp.c

··· 241 241 DEBUG_CALL("udp_output"); 242 242 DEBUG_ARG("so = %p", so); 243 243 DEBUG_ARG("m = %p", m); 244 244 - DEBUG_ARG("saddr = %lx", (long)saddr->sin_addr.s_addr); 245 245 - DEBUG_ARG("daddr = %lx", (long)daddr->sin_addr.s_addr); 244 244 + DEBUG_ARG("saddr = %s", inet_ntoa(saddr->sin_addr)); 245 245 + DEBUG_ARG("daddr = %s", inet_ntoa(daddr->sin_addr)); 246 246 247 247 /* 248 248 * Adjust for header

+3 -7

target/i386/hax-darwin.c

··· 257 257 258 258 int hax_vcpu_run(struct hax_vcpu_state *vcpu) 259 259 { 260 260 - int ret; 261 261 - 262 262 - ret = ioctl(vcpu->fd, HAX_VCPU_IOCTL_RUN, NULL); 263 263 - return ret; 260 260 + return ioctl(vcpu->fd, HAX_VCPU_IOCTL_RUN, NULL); 264 261 } 265 262 266 263 int hax_sync_fpu(CPUArchState *env, struct fx_layout *fl, int set) ··· 315 312 316 313 int hax_inject_interrupt(CPUArchState *env, int vector) 317 314 { 318 318 - int ret, fd; 315 315 + int fd; 319 316 320 317 fd = hax_vcpu_get_fd(env); 321 318 if (fd <= 0) { 322 319 return -1; 323 320 } 324 321 325 325 - ret = ioctl(fd, HAX_VCPU_IOCTL_INTERRUPT, &vector); 326 326 - return ret; 322 322 + return ioctl(fd, HAX_VCPU_IOCTL_INTERRUPT, &vector); 327 323 }

+1 -1

target/i386/translate.c

··· 113 113 int rex_x, rex_b; 114 114 #endif 115 115 int vex_l; /* vex vector length */ 116 116 - int vex_v; /* vex vvvv register, without 1's compliment. */ 116 116 + int vex_v; /* vex vvvv register, without 1's complement. */ 117 117 int ss32; /* 32 bit stack segment */ 118 118 CCOp cc_op; /* current CC operation */ 119 119 bool cc_op_dirty;

+1 -1

target/m68k/translate.c

··· 4002 4002 TCGv shift; 4003 4003 4004 4004 /* In general, we're going to rotate the field so that it's at the 4005 4005 - top of the word and then right-shift by the compliment of the 4005 4005 + top of the word and then right-shift by the complement of the 4006 4006 width to extend the field. */ 4007 4007 if (ext & 0x20) { 4008 4008 /* Variable width. */

+3 -12

target/mips/dsp_helper.c

··· 3274 3274 CPUMIPSState *env) 3275 3275 { 3276 3276 uint64_t temp[3]; 3277 3277 - target_ulong result; 3278 3277 3279 3278 shift = shift & 0x3F; 3280 3279 3281 3280 mipsdsp_rndrashift_acc(temp, ac, shift, env); 3282 3282 - result = (temp[1] << 63) | (temp[0] >> 1); 3283 3283 - 3284 3284 - return result; 3281 3281 + return (temp[1] << 63) | (temp[0] >> 1); 3285 3282 } 3286 3283 3287 3284 target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift, ··· 3289 3286 { 3290 3287 uint64_t temp[3]; 3291 3288 uint32_t temp128; 3292 3292 - target_ulong result; 3293 3289 3294 3290 shift = shift & 0x3F; 3295 3291 mipsdsp_rndrashift_acc(temp, ac, shift, env); ··· 3309 3305 set_DSPControl_overflow_flag(1, 23, env); 3310 3306 } 3311 3307 3312 3312 - result = (temp[1] << 63) | (temp[0] >> 1); 3313 3313 - 3314 3314 - return result; 3308 3308 + return (temp[1] << 63) | (temp[0] >> 1); 3315 3309 } 3316 3310 3317 3311 target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift, ··· 3319 3313 { 3320 3314 uint64_t temp[3]; 3321 3315 uint32_t temp128; 3322 3322 - target_ulong result; 3323 3316 3324 3317 shift = shift & 0x3F; 3325 3318 mipsdsp_rndrashift_acc(temp, ac, shift, env); ··· 3345 3338 } 3346 3339 set_DSPControl_overflow_flag(1, 23, env); 3347 3340 } 3348 3348 - result = (temp[1] << 63) | (temp[0] >> 1); 3349 3349 - 3350 3350 - return result; 3341 3341 + return (temp[1] << 63) | (temp[0] >> 1); 3351 3342 } 3352 3343 #endif 3353 3344

+14 -42

target/xtensa/core-dc232b/xtensa-modules.inc.c

··· 1736 1736 static int 1737 1737 Operand_arr_encode (uint32 *valp) 1738 1738 { 1739 1739 - int error; 1740 1740 - error = (*valp & ~0xf) != 0; 1741 1741 - return error; 1739 1739 + return (*valp & ~0xf) != 0; 1742 1740 } 1743 1741 1744 1742 static int ··· 1750 1748 static int 1751 1749 Operand_ars_encode (uint32 *valp) 1752 1750 { 1753 1753 - int error; 1754 1754 - error = (*valp & ~0xf) != 0; 1755 1755 - return error; 1751 1751 + return (*valp & ~0xf) != 0; 1756 1752 } 1757 1753 1758 1754 static int ··· 1764 1760 static int 1765 1761 Operand_art_encode (uint32 *valp) 1766 1762 { 1767 1767 - int error; 1768 1768 - error = (*valp & ~0xf) != 0; 1769 1769 - return error; 1763 1763 + return (*valp & ~0xf) != 0; 1770 1764 } 1771 1765 1772 1766 static int ··· 1778 1772 static int 1779 1773 Operand_ar0_encode (uint32 *valp) 1780 1774 { 1781 1781 - int error; 1782 1782 - error = (*valp & ~0x1f) != 0; 1783 1783 - return error; 1775 1775 + return (*valp & ~0x1f) != 0; 1784 1776 } 1785 1777 1786 1778 static int ··· 1792 1784 static int 1793 1785 Operand_ar4_encode (uint32 *valp) 1794 1786 { 1795 1795 - int error; 1796 1796 - error = (*valp & ~0x1f) != 0; 1797 1797 - return error; 1787 1787 + return (*valp & ~0x1f) != 0; 1798 1788 } 1799 1789 1800 1790 static int ··· 1806 1796 static int 1807 1797 Operand_ar8_encode (uint32 *valp) 1808 1798 { 1809 1809 - int error; 1810 1810 - error = (*valp & ~0x1f) != 0; 1811 1811 - return error; 1799 1799 + return (*valp & ~0x1f) != 0; 1812 1800 } 1813 1801 1814 1802 static int ··· 1820 1808 static int 1821 1809 Operand_ar12_encode (uint32 *valp) 1822 1810 { 1823 1823 - int error; 1824 1824 - error = (*valp & ~0x1f) != 0; 1825 1825 - return error; 1811 1811 + return (*valp & ~0x1f) != 0; 1826 1812 } 1827 1813 1828 1814 static int ··· 1834 1820 static int 1835 1821 Operand_ars_entry_encode (uint32 *valp) 1836 1822 { 1837 1837 - int error; 1838 1838 - error = (*valp & ~0x1f) != 0; 1839 1839 - return error; 1823 1823 + return (*valp & ~0x1f) != 0; 1840 1824 } 1841 1825 1842 1826 static int ··· 2406 2390 static int 2407 2391 Operand_mx_encode (uint32 *valp) 2408 2392 { 2409 2409 - int error; 2410 2410 - error = (*valp & ~0x3) != 0; 2411 2411 - return error; 2393 2393 + return (*valp & ~0x3) != 0; 2412 2394 } 2413 2395 2414 2396 static int ··· 2436 2418 static int 2437 2419 Operand_mw_encode (uint32 *valp) 2438 2420 { 2439 2439 - int error; 2440 2440 - error = (*valp & ~0x3) != 0; 2441 2441 - return error; 2421 2421 + return (*valp & ~0x3) != 0; 2442 2422 } 2443 2423 2444 2424 static int ··· 2450 2430 static int 2451 2431 Operand_mr0_encode (uint32 *valp) 2452 2432 { 2453 2453 - int error; 2454 2454 - error = (*valp & ~0x3) != 0; 2455 2455 - return error; 2433 2433 + return (*valp & ~0x3) != 0; 2456 2434 } 2457 2435 2458 2436 static int ··· 2464 2442 static int 2465 2443 Operand_mr1_encode (uint32 *valp) 2466 2444 { 2467 2467 - int error; 2468 2468 - error = (*valp & ~0x3) != 0; 2469 2469 - return error; 2445 2445 + return (*valp & ~0x3) != 0; 2470 2446 } 2471 2447 2472 2448 static int ··· 2478 2454 static int 2479 2455 Operand_mr2_encode (uint32 *valp) 2480 2456 { 2481 2481 - int error; 2482 2482 - error = (*valp & ~0x3) != 0; 2483 2483 - return error; 2457 2457 + return (*valp & ~0x3) != 0; 2484 2458 } 2485 2459 2486 2460 static int ··· 2492 2466 static int 2493 2467 Operand_mr3_encode (uint32 *valp) 2494 2468 { 2495 2495 - int error; 2496 2496 - error = (*valp & ~0x3) != 0; 2497 2497 - return error; 2469 2469 + return (*valp & ~0x3) != 0; 2498 2470 } 2499 2471 2500 2472 static int

+14 -42

target/xtensa/core-dc233c/xtensa-modules.inc.c

··· 1817 1817 static int 1818 1818 Operand_arr_encode (uint32 *valp) 1819 1819 { 1820 1820 - int error; 1821 1821 - error = (*valp & ~0xf) != 0; 1822 1822 - return error; 1820 1820 + return (*valp & ~0xf) != 0; 1823 1821 } 1824 1822 1825 1823 static int ··· 1831 1829 static int 1832 1830 Operand_ars_encode (uint32 *valp) 1833 1831 { 1834 1834 - int error; 1835 1835 - error = (*valp & ~0xf) != 0; 1836 1836 - return error; 1832 1832 + return (*valp & ~0xf) != 0; 1837 1833 } 1838 1834 1839 1835 static int ··· 1845 1841 static int 1846 1842 Operand_art_encode (uint32 *valp) 1847 1843 { 1848 1848 - int error; 1849 1849 - error = (*valp & ~0xf) != 0; 1850 1850 - return error; 1844 1844 + return (*valp & ~0xf) != 0; 1851 1845 } 1852 1846 1853 1847 static int ··· 1859 1853 static int 1860 1854 Operand_ar0_encode (uint32 *valp) 1861 1855 { 1862 1862 - int error; 1863 1863 - error = (*valp & ~0x1f) != 0; 1864 1864 - return error; 1856 1856 + return (*valp & ~0x1f) != 0; 1865 1857 } 1866 1858 1867 1859 static int ··· 1873 1865 static int 1874 1866 Operand_ar4_encode (uint32 *valp) 1875 1867 { 1876 1876 - int error; 1877 1877 - error = (*valp & ~0x1f) != 0; 1878 1878 - return error; 1868 1868 + return (*valp & ~0x1f) != 0; 1879 1869 } 1880 1870 1881 1871 static int ··· 1887 1877 static int 1888 1878 Operand_ar8_encode (uint32 *valp) 1889 1879 { 1890 1890 - int error; 1891 1891 - error = (*valp & ~0x1f) != 0; 1892 1892 - return error; 1880 1880 + return (*valp & ~0x1f) != 0; 1893 1881 } 1894 1882 1895 1883 static int ··· 1901 1889 static int 1902 1890 Operand_ar12_encode (uint32 *valp) 1903 1891 { 1904 1904 - int error; 1905 1905 - error = (*valp & ~0x1f) != 0; 1906 1906 - return error; 1892 1892 + return (*valp & ~0x1f) != 0; 1907 1893 } 1908 1894 1909 1895 static int ··· 1915 1901 static int 1916 1902 Operand_ars_entry_encode (uint32 *valp) 1917 1903 { 1918 1918 - int error; 1919 1919 - error = (*valp & ~0x1f) != 0; 1920 1920 - return error; 1904 1904 + return (*valp & ~0x1f) != 0; 1921 1905 } 1922 1906 1923 1907 static int ··· 2487 2471 static int 2488 2472 Operand_mx_encode (uint32 *valp) 2489 2473 { 2490 2490 - int error; 2491 2491 - error = (*valp & ~0x3) != 0; 2492 2492 - return error; 2474 2474 + return (*valp & ~0x3) != 0; 2493 2475 } 2494 2476 2495 2477 static int ··· 2517 2499 static int 2518 2500 Operand_mw_encode (uint32 *valp) 2519 2501 { 2520 2520 - int error; 2521 2521 - error = (*valp & ~0x3) != 0; 2522 2522 - return error; 2502 2502 + return (*valp & ~0x3) != 0; 2523 2503 } 2524 2504 2525 2505 static int ··· 2531 2511 static int 2532 2512 Operand_mr0_encode (uint32 *valp) 2533 2513 { 2534 2534 - int error; 2535 2535 - error = (*valp & ~0x3) != 0; 2536 2536 - return error; 2514 2514 + return (*valp & ~0x3) != 0; 2537 2515 } 2538 2516 2539 2517 static int ··· 2545 2523 static int 2546 2524 Operand_mr1_encode (uint32 *valp) 2547 2525 { 2548 2548 - int error; 2549 2549 - error = (*valp & ~0x3) != 0; 2550 2550 - return error; 2526 2526 + return (*valp & ~0x3) != 0; 2551 2527 } 2552 2528 2553 2529 static int ··· 2559 2535 static int 2560 2536 Operand_mr2_encode (uint32 *valp) 2561 2537 { 2562 2562 - int error; 2563 2563 - error = (*valp & ~0x3) != 0; 2564 2564 - return error; 2538 2538 + return (*valp & ~0x3) != 0; 2565 2539 } 2566 2540 2567 2541 static int ··· 2573 2547 static int 2574 2548 Operand_mr3_encode (uint32 *valp) 2575 2549 { 2576 2576 - int error; 2577 2577 - error = (*valp & ~0x3) != 0; 2578 2578 - return error; 2550 2550 + return (*valp & ~0x3) != 0; 2579 2551 } 2580 2552 2581 2553 static int

+12 -36

target/xtensa/core-de212/xtensa-modules.inc.c

··· 1798 1798 static int 1799 1799 OperandSem_opnd_sem_AR_encode (uint32 *valp) 1800 1800 { 1801 1801 - int error; 1802 1802 - error = (*valp >= 32); 1803 1803 - return error; 1801 1801 + return (*valp >= 32); 1804 1802 } 1805 1803 1806 1804 static int ··· 1812 1810 static int 1813 1811 OperandSem_opnd_sem_AR_0_encode (uint32 *valp) 1814 1812 { 1815 1815 - int error; 1816 1816 - error = (*valp >= 32); 1817 1817 - return error; 1813 1813 + return (*valp >= 32); 1818 1814 } 1819 1815 1820 1816 static int ··· 1826 1822 static int 1827 1823 OperandSem_opnd_sem_AR_1_encode (uint32 *valp) 1828 1824 { 1829 1829 - int error; 1830 1830 - error = (*valp >= 32); 1831 1831 - return error; 1825 1825 + return (*valp >= 32); 1832 1826 } 1833 1827 1834 1828 static int ··· 1840 1834 static int 1841 1835 OperandSem_opnd_sem_AR_2_encode (uint32 *valp) 1842 1836 { 1843 1843 - int error; 1844 1844 - error = (*valp >= 32); 1845 1845 - return error; 1837 1837 + return (*valp >= 32); 1846 1838 } 1847 1839 1848 1840 static int ··· 1854 1846 static int 1855 1847 OperandSem_opnd_sem_AR_3_encode (uint32 *valp) 1856 1848 { 1857 1857 - int error; 1858 1858 - error = (*valp >= 32); 1859 1859 - return error; 1849 1849 + return (*valp >= 32); 1860 1850 } 1861 1851 1862 1852 static int ··· 1868 1858 static int 1869 1859 OperandSem_opnd_sem_AR_4_encode (uint32 *valp) 1870 1860 { 1871 1871 - int error; 1872 1872 - error = (*valp >= 32); 1873 1873 - return error; 1861 1861 + return (*valp >= 32); 1874 1862 } 1875 1863 1876 1864 static int ··· 2464 2452 static int 2465 2453 OperandSem_opnd_sem_MR_encode (uint32 *valp) 2466 2454 { 2467 2467 - int error; 2468 2468 - error = (*valp >= 4); 2469 2469 - return error; 2455 2455 + return (*valp >= 4); 2470 2456 } 2471 2457 2472 2458 static int ··· 2478 2464 static int 2479 2465 OperandSem_opnd_sem_MR_1_encode (uint32 *valp) 2480 2466 { 2481 2481 - int error; 2482 2482 - error = (*valp >= 4); 2483 2483 - return error; 2467 2467 + return (*valp >= 4); 2484 2468 } 2485 2469 2486 2470 static int ··· 2492 2476 static int 2493 2477 OperandSem_opnd_sem_MR_2_encode (uint32 *valp) 2494 2478 { 2495 2495 - int error; 2496 2496 - error = (*valp >= 4); 2497 2497 - return error; 2479 2479 + return (*valp >= 4); 2498 2480 } 2499 2481 2500 2482 static int ··· 2506 2488 static int 2507 2489 OperandSem_opnd_sem_MR_3_encode (uint32 *valp) 2508 2490 { 2509 2509 - int error; 2510 2510 - error = (*valp >= 4); 2511 2511 - return error; 2491 2491 + return (*valp >= 4); 2512 2492 } 2513 2493 2514 2494 static int ··· 2520 2500 static int 2521 2501 OperandSem_opnd_sem_MR_4_encode (uint32 *valp) 2522 2502 { 2523 2523 - int error; 2524 2524 - error = (*valp >= 4); 2525 2525 - return error; 2503 2503 + return (*valp >= 4); 2526 2504 } 2527 2505 2528 2506 static int ··· 2534 2512 static int 2535 2513 OperandSem_opnd_sem_MR_5_encode (uint32 *valp) 2536 2514 { 2537 2537 - int error; 2538 2538 - error = (*valp >= 4); 2539 2539 - return error; 2515 2515 + return (*valp >= 4); 2540 2516 } 2541 2517 2542 2518 static int

+8 -24

target/xtensa/core-fsf/xtensa-modules.inc.c

··· 1379 1379 static int 1380 1380 Operand_arr_encode (uint32 *valp) 1381 1381 { 1382 1382 - int error; 1383 1383 - error = (*valp & ~0xf) != 0; 1384 1384 - return error; 1382 1382 + return (*valp & ~0xf) != 0; 1385 1383 } 1386 1384 1387 1385 static int ··· 1393 1391 static int 1394 1392 Operand_ars_encode (uint32 *valp) 1395 1393 { 1396 1396 - int error; 1397 1397 - error = (*valp & ~0xf) != 0; 1398 1398 - return error; 1394 1394 + return (*valp & ~0xf) != 0; 1399 1395 } 1400 1396 1401 1397 static int ··· 1407 1403 static int 1408 1404 Operand_art_encode (uint32 *valp) 1409 1405 { 1410 1410 - int error; 1411 1411 - error = (*valp & ~0xf) != 0; 1412 1412 - return error; 1406 1406 + return (*valp & ~0xf) != 0; 1413 1407 } 1414 1408 1415 1409 static int ··· 1421 1415 static int 1422 1416 Operand_ar0_encode (uint32 *valp) 1423 1417 { 1424 1424 - int error; 1425 1425 - error = (*valp & ~0x3f) != 0; 1426 1426 - return error; 1418 1418 + return (*valp & ~0x3f) != 0; 1427 1419 } 1428 1420 1429 1421 static int ··· 1435 1427 static int 1436 1428 Operand_ar4_encode (uint32 *valp) 1437 1429 { 1438 1438 - int error; 1439 1439 - error = (*valp & ~0x3f) != 0; 1440 1440 - return error; 1430 1430 + return (*valp & ~0x3f) != 0; 1441 1431 } 1442 1432 1443 1433 static int ··· 1449 1439 static int 1450 1440 Operand_ar8_encode (uint32 *valp) 1451 1441 { 1452 1452 - int error; 1453 1453 - error = (*valp & ~0x3f) != 0; 1454 1454 - return error; 1442 1442 + return (*valp & ~0x3f) != 0; 1455 1443 } 1456 1444 1457 1445 static int ··· 1463 1451 static int 1464 1452 Operand_ar12_encode (uint32 *valp) 1465 1453 { 1466 1466 - int error; 1467 1467 - error = (*valp & ~0x3f) != 0; 1468 1468 - return error; 1454 1454 + return (*valp & ~0x3f) != 0; 1469 1455 } 1470 1456 1471 1457 static int ··· 1477 1463 static int 1478 1464 Operand_ars_entry_encode (uint32 *valp) 1479 1465 { 1480 1480 - int error; 1481 1481 - error = (*valp & ~0x3f) != 0; 1482 1482 - return error; 1466 1466 + return (*valp & ~0x3f) != 0; 1483 1467 } 1484 1468 1485 1469 static int

+6 -18

target/xtensa/core-sample_controller/xtensa-modules.inc.c

··· 1570 1570 static int 1571 1571 OperandSem_opnd_sem_AR_encode (uint32 *valp) 1572 1572 { 1573 1573 - int error; 1574 1574 - error = (*valp >= 32); 1575 1575 - return error; 1573 1573 + return (*valp >= 32); 1576 1574 } 1577 1575 1578 1576 static int ··· 1584 1582 static int 1585 1583 OperandSem_opnd_sem_AR_0_encode (uint32 *valp) 1586 1584 { 1587 1587 - int error; 1588 1588 - error = (*valp >= 32); 1589 1589 - return error; 1585 1585 + return (*valp >= 32); 1590 1586 } 1591 1587 1592 1588 static int ··· 1598 1594 static int 1599 1595 OperandSem_opnd_sem_AR_1_encode (uint32 *valp) 1600 1596 { 1601 1601 - int error; 1602 1602 - error = (*valp >= 32); 1603 1603 - return error; 1597 1597 + return (*valp >= 32); 1604 1598 } 1605 1599 1606 1600 static int ··· 1612 1606 static int 1613 1607 OperandSem_opnd_sem_AR_2_encode (uint32 *valp) 1614 1608 { 1615 1615 - int error; 1616 1616 - error = (*valp >= 32); 1617 1617 - return error; 1609 1609 + return (*valp >= 32); 1618 1610 } 1619 1611 1620 1612 static int ··· 1626 1618 static int 1627 1619 OperandSem_opnd_sem_AR_3_encode (uint32 *valp) 1628 1620 { 1629 1629 - int error; 1630 1630 - error = (*valp >= 32); 1631 1631 - return error; 1621 1621 + return (*valp >= 32); 1632 1622 } 1633 1623 1634 1624 static int ··· 1640 1630 static int 1641 1631 OperandSem_opnd_sem_AR_4_encode (uint32 *valp) 1642 1632 { 1643 1643 - int error; 1644 1644 - error = (*valp >= 32); 1645 1645 - return error; 1633 1633 + return (*valp >= 32); 1646 1634 } 1647 1635 1648 1636 static int

+2 -5

target/xtensa/translate.c

··· 1272 1272 xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, 1273 1273 const char *name) 1274 1274 { 1275 1275 - XtensaOpcodeOps *ops; 1276 1276 - 1277 1277 - ops = bsearch(name, t->opcode, t->num_opcodes, 1278 1278 - sizeof(XtensaOpcodeOps), compare_opcode_ops); 1279 1279 - return ops; 1275 1275 + return bsearch(name, t->opcode, t->num_opcodes, 1276 1276 + sizeof(XtensaOpcodeOps), compare_opcode_ops); 1280 1277 } 1281 1278 1282 1279 static void translate_abs(DisasContext *dc, const uint32_t arg[],

+1 -1

tcg/README

··· 561 561 * orc_vec v0, v1, v2 562 562 * not_vec v0, v1 563 563 564 564 - Similarly, logical operations with and without compliment. 564 564 + Similarly, logical operations with and without complement. 565 565 Note that VECE is unused. 566 566 567 567 * shli_vec v0, v1, i2

+1 -5

tests/m48t59-test.c

··· 256 256 257 257 int main(int argc, char **argv) 258 258 { 259 259 - int ret; 260 260 - 261 259 base_setup(); 262 260 263 261 g_test_init(&argc, &argv, NULL); ··· 267 265 qtest_add_func("/rtc/bcd-check-time", bcd_check_time); 268 266 } 269 267 qtest_add_func("/rtc/fuzz-registers", fuzz_registers); 270 270 - ret = g_test_run(); 271 271 - 272 272 - return ret; 268 268 + return g_test_run(); 273 269 }

+1 -5

tests/test-thread-pool.c

··· 224 224 225 225 int main(int argc, char **argv) 226 226 { 227 227 - int ret; 228 228 - 229 227 qemu_init_main_loop(&error_abort); 230 228 ctx = qemu_get_current_aio_context(); 231 229 pool = aio_get_thread_pool(ctx); ··· 238 236 g_test_add_func("/thread-pool/cancel", test_cancel); 239 237 g_test_add_func("/thread-pool/cancel-async", test_cancel_async); 240 238 241 241 - ret = g_test_run(); 242 242 - 243 243 - return ret; 239 239 + return g_test_run(); 244 240 }

+1 -1

tests/tpm-emu.c

··· 125 125 case CMD_SHUTDOWN: { 126 126 ptm_res res = 0; 127 127 qio_channel_write(ioc, (char *)&res, sizeof(res), &error_abort); 128 128 - qio_channel_close(s->tpm_ioc, &error_abort); 128 128 + /* the tpm data thread is expected to finish now */ 129 129 g_thread_join(s->emu_tpm_thread); 130 130 break; 131 131 }

+1 -4

util/uri.c

··· 1065 1065 */ 1066 1066 URI *uri_new(void) 1067 1067 { 1068 1068 - URI *ret; 1069 1069 - 1070 1070 - ret = g_new0(URI, 1); 1071 1071 - return ret; 1068 1068 + return g_new0(URI, 1); 1072 1069 } 1073 1070 1074 1071 /**

+2 -4

util/vfio-helpers.c

··· 522 522 523 523 assert(index >= 0); 524 524 s->nr_mappings++; 525 525 - s->mappings = g_realloc_n(s->mappings, sizeof(s->mappings[0]), 526 526 - s->nr_mappings); 525 525 + s->mappings = g_renew(IOVAMapping, s->mappings, s->nr_mappings); 527 526 insert = &s->mappings[index]; 528 527 shift = s->nr_mappings - index - 1; 529 528 if (shift) { ··· 577 576 memmove(mapping, &s->mappings[index + 1], 578 577 sizeof(s->mappings[0]) * (s->nr_mappings - index - 1)); 579 578 s->nr_mappings--; 580 580 - s->mappings = g_realloc_n(s->mappings, sizeof(s->mappings[0]), 581 581 - s->nr_mappings); 579 579 + s->mappings = g_renew(IOVAMapping, s->mappings, s->nr_mappings); 582 580 } 583 581 584 582 /* Check if the mapping list is (ascending) ordered. */

+4

vl.c

··· 4011 4011 exit(1); 4012 4012 } 4013 4013 break; 4014 4014 + case QEMU_OPTION_nodefconfig: 4015 4015 + case QEMU_OPTION_nouserconfig: 4016 4016 + /* Nothing to be parsed here. Especially, do not error out below. */ 4017 4017 + break; 4014 4018 default: 4015 4019 if (os_parse_cmd_args(popt->index, optarg)) { 4016 4020 error_report("Option not supported in this build");