+2

Makefile.target

··· 272 272 obj-microblaze-y += xilinx_timer.o 273 273 obj-microblaze-y += xilinx_uartlite.o 274 274 obj-microblaze-y += xilinx_ethlite.o 275 275 + obj-microblaze-y += xilinx_axidma.o 276 276 + obj-microblaze-y += xilinx_axienet.o 275 277 276 278 obj-microblaze-$(CONFIG_FDT) += device_tree.o 277 279

+509

hw/xilinx_axidma.c

··· 1 1 + /* 2 2 + * QEMU model of Xilinx AXI-DMA block. 3 3 + * 4 4 + * Copyright (c) 2011 Edgar E. Iglesias. 5 5 + * 6 6 + * Permission is hereby granted, free of charge, to any person obtaining a copy 7 7 + * of this software and associated documentation files (the "Software"), to deal 8 8 + * in the Software without restriction, including without limitation the rights 9 9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 10 + * copies of the Software, and to permit persons to whom the Software is 11 11 + * furnished to do so, subject to the following conditions: 12 12 + * 13 13 + * The above copyright notice and this permission notice shall be included in 14 14 + * all copies or substantial portions of the Software. 15 15 + * 16 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 22 + * THE SOFTWARE. 23 23 + */ 24 24 + 25 25 + #include "sysbus.h" 26 26 + #include "qemu-char.h" 27 27 + #include "qemu-timer.h" 28 28 + #include "qemu-log.h" 29 29 + #include "qdev-addr.h" 30 30 + 31 31 + #include "xilinx_axidma.h" 32 32 + 33 33 + #define D(x) 34 34 + 35 35 + #define R_DMACR (0x00 / 4) 36 36 + #define R_DMASR (0x04 / 4) 37 37 + #define R_CURDESC (0x08 / 4) 38 38 + #define R_TAILDESC (0x10 / 4) 39 39 + #define R_MAX (0x30 / 4) 40 40 + 41 41 + enum { 42 42 + DMACR_RUNSTOP = 1, 43 43 + DMACR_TAILPTR_MODE = 2, 44 44 + DMACR_RESET = 4 45 45 + }; 46 46 + 47 47 + enum { 48 48 + DMASR_HALTED = 1, 49 49 + DMASR_IDLE = 2, 50 50 + DMASR_IOC_IRQ = 1 << 12, 51 51 + DMASR_DLY_IRQ = 1 << 13, 52 52 + 53 53 + DMASR_IRQ_MASK = 7 << 12 54 54 + }; 55 55 + 56 56 + struct SDesc { 57 57 + uint64_t nxtdesc; 58 58 + uint64_t buffer_address; 59 59 + uint64_t reserved; 60 60 + uint32_t control; 61 61 + uint32_t status; 62 62 + uint32_t app[6]; 63 63 + }; 64 64 + 65 65 + enum { 66 66 + SDESC_CTRL_EOF = (1 << 26), 67 67 + SDESC_CTRL_SOF = (1 << 27), 68 68 + 69 69 + SDESC_CTRL_LEN_MASK = (1 << 23) - 1 70 70 + }; 71 71 + 72 72 + enum { 73 73 + SDESC_STATUS_EOF = (1 << 26), 74 74 + SDESC_STATUS_SOF_BIT = 27, 75 75 + SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT), 76 76 + SDESC_STATUS_COMPLETE = (1 << 31) 77 77 + }; 78 78 + 79 79 + struct AXIStream { 80 80 + QEMUBH *bh; 81 81 + ptimer_state *ptimer; 82 82 + qemu_irq irq; 83 83 + 84 84 + int nr; 85 85 + 86 86 + struct SDesc desc; 87 87 + int pos; 88 88 + unsigned int complete_cnt; 89 89 + uint32_t regs[R_MAX]; 90 90 + }; 91 91 + 92 92 + struct XilinxAXIDMA { 93 93 + SysBusDevice busdev; 94 94 + uint32_t freqhz; 95 95 + void *dmach; 96 96 + 97 97 + struct AXIStream streams[2]; 98 98 + }; 99 99 + 100 100 + /* 101 101 + * Helper calls to extract info from desriptors and other trivial 102 102 + * state from regs. 103 103 + */ 104 104 + static inline int stream_desc_sof(struct SDesc *d) 105 105 + { 106 106 + return d->control & SDESC_CTRL_SOF; 107 107 + } 108 108 + 109 109 + static inline int stream_desc_eof(struct SDesc *d) 110 110 + { 111 111 + return d->control & SDESC_CTRL_EOF; 112 112 + } 113 113 + 114 114 + static inline int stream_resetting(struct AXIStream *s) 115 115 + { 116 116 + return !!(s->regs[R_DMACR] & DMACR_RESET); 117 117 + } 118 118 + 119 119 + static inline int stream_running(struct AXIStream *s) 120 120 + { 121 121 + return s->regs[R_DMACR] & DMACR_RUNSTOP; 122 122 + } 123 123 + 124 124 + static inline int stream_halted(struct AXIStream *s) 125 125 + { 126 126 + return s->regs[R_DMASR] & DMASR_HALTED; 127 127 + } 128 128 + 129 129 + static inline int stream_idle(struct AXIStream *s) 130 130 + { 131 131 + return !!(s->regs[R_DMASR] & DMASR_IDLE); 132 132 + } 133 133 + 134 134 + static void stream_reset(struct AXIStream *s) 135 135 + { 136 136 + s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */ 137 137 + s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshhold. */ 138 138 + } 139 139 + 140 140 + /* Mapp an offset addr into a channel index. */ 141 141 + static inline int streamid_from_addr(target_phys_addr_t addr) 142 142 + { 143 143 + int sid; 144 144 + 145 145 + sid = addr / (0x30); 146 146 + sid &= 1; 147 147 + return sid; 148 148 + } 149 149 + 150 150 + #ifdef DEBUG_ENET 151 151 + static void stream_desc_show(struct SDesc *d) 152 152 + { 153 153 + qemu_log("buffer_addr = " PRIx64 "\n", d->buffer_address); 154 154 + qemu_log("nxtdesc = " PRIx64 "\n", d->nxtdesc); 155 155 + qemu_log("control = %x\n", d->control); 156 156 + qemu_log("status = %x\n", d->status); 157 157 + } 158 158 + #endif 159 159 + 160 160 + static void stream_desc_load(struct AXIStream *s, target_phys_addr_t addr) 161 161 + { 162 162 + struct SDesc *d = &s->desc; 163 163 + int i; 164 164 + 165 165 + cpu_physical_memory_read(addr, (void *) d, sizeof *d); 166 166 + 167 167 + /* Convert from LE into host endianness. */ 168 168 + d->buffer_address = le64_to_cpu(d->buffer_address); 169 169 + d->nxtdesc = le64_to_cpu(d->nxtdesc); 170 170 + d->control = le32_to_cpu(d->control); 171 171 + d->status = le32_to_cpu(d->status); 172 172 + for (i = 0; i < ARRAY_SIZE(d->app); i++) { 173 173 + d->app[i] = le32_to_cpu(d->app[i]); 174 174 + } 175 175 + } 176 176 + 177 177 + static void stream_desc_store(struct AXIStream *s, target_phys_addr_t addr) 178 178 + { 179 179 + struct SDesc *d = &s->desc; 180 180 + int i; 181 181 + 182 182 + /* Convert from host endianness into LE. */ 183 183 + d->buffer_address = cpu_to_le64(d->buffer_address); 184 184 + d->nxtdesc = cpu_to_le64(d->nxtdesc); 185 185 + d->control = cpu_to_le32(d->control); 186 186 + d->status = cpu_to_le32(d->status); 187 187 + for (i = 0; i < ARRAY_SIZE(d->app); i++) { 188 188 + d->app[i] = cpu_to_le32(d->app[i]); 189 189 + } 190 190 + cpu_physical_memory_write(addr, (void *) d, sizeof *d); 191 191 + } 192 192 + 193 193 + static void stream_update_irq(struct AXIStream *s) 194 194 + { 195 195 + unsigned int pending, mask, irq; 196 196 + 197 197 + pending = s->regs[R_DMASR] & DMASR_IRQ_MASK; 198 198 + mask = s->regs[R_DMACR] & DMASR_IRQ_MASK; 199 199 + 200 200 + irq = pending & mask; 201 201 + 202 202 + qemu_set_irq(s->irq, !!irq); 203 203 + } 204 204 + 205 205 + static void stream_reload_complete_cnt(struct AXIStream *s) 206 206 + { 207 207 + unsigned int comp_th; 208 208 + comp_th = (s->regs[R_DMACR] >> 16) & 0xff; 209 209 + s->complete_cnt = comp_th; 210 210 + } 211 211 + 212 212 + static void timer_hit(void *opaque) 213 213 + { 214 214 + struct AXIStream *s = opaque; 215 215 + 216 216 + stream_reload_complete_cnt(s); 217 217 + s->regs[R_DMASR] |= DMASR_DLY_IRQ; 218 218 + stream_update_irq(s); 219 219 + } 220 220 + 221 221 + static void stream_complete(struct AXIStream *s) 222 222 + { 223 223 + unsigned int comp_delay; 224 224 + 225 225 + /* Start the delayed timer. */ 226 226 + comp_delay = s->regs[R_DMACR] >> 24; 227 227 + if (comp_delay) { 228 228 + ptimer_stop(s->ptimer); 229 229 + ptimer_set_count(s->ptimer, comp_delay); 230 230 + ptimer_run(s->ptimer, 1); 231 231 + } 232 232 + 233 233 + s->complete_cnt--; 234 234 + if (s->complete_cnt == 0) { 235 235 + /* Raise the IOC irq. */ 236 236 + s->regs[R_DMASR] |= DMASR_IOC_IRQ; 237 237 + stream_reload_complete_cnt(s); 238 238 + } 239 239 + } 240 240 + 241 241 + static void stream_process_mem2s(struct AXIStream *s, 242 242 + struct XilinxDMAConnection *dmach) 243 243 + { 244 244 + uint32_t prev_d; 245 245 + unsigned char txbuf[16 * 1024]; 246 246 + unsigned int txlen; 247 247 + uint32_t app[6]; 248 248 + 249 249 + if (!stream_running(s) || stream_idle(s)) { 250 250 + return; 251 251 + } 252 252 + 253 253 + while (1) { 254 254 + stream_desc_load(s, s->regs[R_CURDESC]); 255 255 + 256 256 + if (s->desc.status & SDESC_STATUS_COMPLETE) { 257 257 + s->regs[R_DMASR] |= DMASR_IDLE; 258 258 + break; 259 259 + } 260 260 + 261 261 + if (stream_desc_sof(&s->desc)) { 262 262 + s->pos = 0; 263 263 + memcpy(app, s->desc.app, sizeof app); 264 264 + } 265 265 + 266 266 + txlen = s->desc.control & SDESC_CTRL_LEN_MASK; 267 267 + if ((txlen + s->pos) > sizeof txbuf) { 268 268 + hw_error("%s: too small internal txbuf! %d\n", __func__, 269 269 + txlen + s->pos); 270 270 + } 271 271 + 272 272 + cpu_physical_memory_read(s->desc.buffer_address, 273 273 + txbuf + s->pos, txlen); 274 274 + s->pos += txlen; 275 275 + 276 276 + if (stream_desc_eof(&s->desc)) { 277 277 + xlx_dma_push_to_client(dmach, txbuf, s->pos, app); 278 278 + s->pos = 0; 279 279 + stream_complete(s); 280 280 + } 281 281 + 282 282 + /* Update the descriptor. */ 283 283 + s->desc.status = txlen | SDESC_STATUS_COMPLETE; 284 284 + stream_desc_store(s, s->regs[R_CURDESC]); 285 285 + 286 286 + /* Advance. */ 287 287 + prev_d = s->regs[R_CURDESC]; 288 288 + s->regs[R_CURDESC] = s->desc.nxtdesc; 289 289 + if (prev_d == s->regs[R_TAILDESC]) { 290 290 + s->regs[R_DMASR] |= DMASR_IDLE; 291 291 + break; 292 292 + } 293 293 + } 294 294 + } 295 295 + 296 296 + static void stream_process_s2mem(struct AXIStream *s, 297 297 + unsigned char *buf, size_t len, uint32_t *app) 298 298 + { 299 299 + uint32_t prev_d; 300 300 + unsigned int rxlen; 301 301 + int pos = 0; 302 302 + int sof = 1; 303 303 + 304 304 + if (!stream_running(s) || stream_idle(s)) { 305 305 + return; 306 306 + } 307 307 + 308 308 + while (len) { 309 309 + stream_desc_load(s, s->regs[R_CURDESC]); 310 310 + 311 311 + if (s->desc.status & SDESC_STATUS_COMPLETE) { 312 312 + s->regs[R_DMASR] |= DMASR_IDLE; 313 313 + break; 314 314 + } 315 315 + 316 316 + rxlen = s->desc.control & SDESC_CTRL_LEN_MASK; 317 317 + if (rxlen > len) { 318 318 + /* It fits. */ 319 319 + rxlen = len; 320 320 + } 321 321 + 322 322 + cpu_physical_memory_write(s->desc.buffer_address, buf + pos, rxlen); 323 323 + len -= rxlen; 324 324 + pos += rxlen; 325 325 + 326 326 + /* Update the descriptor. */ 327 327 + if (!len) { 328 328 + int i; 329 329 + 330 330 + stream_complete(s); 331 331 + for (i = 0; i < 5; i++) { 332 332 + s->desc.app[i] = app[i]; 333 333 + } 334 334 + s->desc.status |= SDESC_STATUS_EOF; 335 335 + } 336 336 + 337 337 + s->desc.status |= sof << SDESC_STATUS_SOF_BIT; 338 338 + s->desc.status |= SDESC_STATUS_COMPLETE; 339 339 + stream_desc_store(s, s->regs[R_CURDESC]); 340 340 + sof = 0; 341 341 + 342 342 + /* Advance. */ 343 343 + prev_d = s->regs[R_CURDESC]; 344 344 + s->regs[R_CURDESC] = s->desc.nxtdesc; 345 345 + if (prev_d == s->regs[R_TAILDESC]) { 346 346 + s->regs[R_DMASR] |= DMASR_IDLE; 347 347 + break; 348 348 + } 349 349 + } 350 350 + } 351 351 + 352 352 + static 353 353 + void axidma_push(void *opaque, unsigned char *buf, size_t len, uint32_t *app) 354 354 + { 355 355 + struct XilinxAXIDMA *d = opaque; 356 356 + struct AXIStream *s = &d->streams[1]; 357 357 + 358 358 + if (!app) { 359 359 + hw_error("No stream app data!\n"); 360 360 + } 361 361 + stream_process_s2mem(s, buf, len, app); 362 362 + stream_update_irq(s); 363 363 + } 364 364 + 365 365 + static uint32_t axidma_readl(void *opaque, target_phys_addr_t addr) 366 366 + { 367 367 + struct XilinxAXIDMA *d = opaque; 368 368 + struct AXIStream *s; 369 369 + uint32_t r = 0; 370 370 + int sid; 371 371 + 372 372 + sid = streamid_from_addr(addr); 373 373 + s = &d->streams[sid]; 374 374 + 375 375 + addr = addr % 0x30; 376 376 + addr >>= 2; 377 377 + switch (addr) { 378 378 + case R_DMACR: 379 379 + /* Simulate one cycles reset delay. */ 380 380 + s->regs[addr] &= ~DMACR_RESET; 381 381 + r = s->regs[addr]; 382 382 + break; 383 383 + case R_DMASR: 384 384 + s->regs[addr] &= 0xffff; 385 385 + s->regs[addr] |= (s->complete_cnt & 0xff) << 16; 386 386 + s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24; 387 387 + r = s->regs[addr]; 388 388 + break; 389 389 + default: 390 390 + r = s->regs[addr]; 391 391 + D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n", 392 392 + __func__, sid, addr * 4, r)); 393 393 + break; 394 394 + } 395 395 + return r; 396 396 + 397 397 + } 398 398 + 399 399 + static void 400 400 + axidma_writel(void *opaque, target_phys_addr_t addr, uint32_t value) 401 401 + { 402 402 + struct XilinxAXIDMA *d = opaque; 403 403 + struct AXIStream *s; 404 404 + int sid; 405 405 + 406 406 + sid = streamid_from_addr(addr); 407 407 + s = &d->streams[sid]; 408 408 + 409 409 + addr = addr % 0x30; 410 410 + addr >>= 2; 411 411 + switch (addr) { 412 412 + case R_DMACR: 413 413 + /* Tailptr mode is always on. */ 414 414 + value |= DMACR_TAILPTR_MODE; 415 415 + /* Remember our previous reset state. */ 416 416 + value |= (s->regs[addr] & DMACR_RESET); 417 417 + s->regs[addr] = value; 418 418 + 419 419 + if (value & DMACR_RESET) { 420 420 + stream_reset(s); 421 421 + } 422 422 + 423 423 + if ((value & 1) && !stream_resetting(s)) { 424 424 + /* Start processing. */ 425 425 + s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE); 426 426 + } 427 427 + stream_reload_complete_cnt(s); 428 428 + break; 429 429 + 430 430 + case R_DMASR: 431 431 + /* Mask away write to clear irq lines. */ 432 432 + value &= ~(value & DMASR_IRQ_MASK); 433 433 + s->regs[addr] = value; 434 434 + break; 435 435 + 436 436 + case R_TAILDESC: 437 437 + s->regs[addr] = value; 438 438 + s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle. */ 439 439 + if (!sid) { 440 440 + stream_process_mem2s(s, d->dmach); 441 441 + } 442 442 + break; 443 443 + default: 444 444 + D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n", 445 445 + __func__, sid, addr * 4, value)); 446 446 + s->regs[addr] = value; 447 447 + break; 448 448 + } 449 449 + stream_update_irq(s); 450 450 + } 451 451 + 452 452 + static CPUReadMemoryFunc * const axidma_read[] = { 453 453 + &axidma_readl, 454 454 + &axidma_readl, 455 455 + &axidma_readl, 456 456 + }; 457 457 + 458 458 + static CPUWriteMemoryFunc * const axidma_write[] = { 459 459 + &axidma_writel, 460 460 + &axidma_writel, 461 461 + &axidma_writel, 462 462 + }; 463 463 + 464 464 + static int xilinx_axidma_init(SysBusDevice *dev) 465 465 + { 466 466 + struct XilinxAXIDMA *s = FROM_SYSBUS(typeof(*s), dev); 467 467 + int axidma_regs; 468 468 + int i; 469 469 + 470 470 + sysbus_init_irq(dev, &s->streams[1].irq); 471 471 + sysbus_init_irq(dev, &s->streams[0].irq); 472 472 + 473 473 + if (!s->dmach) { 474 474 + hw_error("Unconnected DMA channel.\n"); 475 475 + } 476 476 + 477 477 + xlx_dma_connect_dma(s->dmach, s, axidma_push); 478 478 + 479 479 + axidma_regs = cpu_register_io_memory(axidma_read, axidma_write, s, 480 480 + DEVICE_NATIVE_ENDIAN); 481 481 + sysbus_init_mmio(dev, R_MAX * 4 * 2, axidma_regs); 482 482 + 483 483 + for (i = 0; i < 2; i++) { 484 484 + stream_reset(&s->streams[i]); 485 485 + s->streams[i].nr = i; 486 486 + s->streams[i].bh = qemu_bh_new(timer_hit, &s->streams[i]); 487 487 + s->streams[i].ptimer = ptimer_init(s->streams[i].bh); 488 488 + ptimer_set_freq(s->streams[i].ptimer, s->freqhz); 489 489 + } 490 490 + return 0; 491 491 + } 492 492 + 493 493 + static SysBusDeviceInfo axidma_info = { 494 494 + .init = xilinx_axidma_init, 495 495 + .qdev.name = "xilinx,axidma", 496 496 + .qdev.size = sizeof(struct XilinxAXIDMA), 497 497 + .qdev.props = (Property[]) { 498 498 + DEFINE_PROP_UINT32("freqhz", struct XilinxAXIDMA, freqhz, 50000000), 499 499 + DEFINE_PROP_PTR("dmach", struct XilinxAXIDMA, dmach), 500 500 + DEFINE_PROP_END_OF_LIST(), 501 501 + } 502 502 + }; 503 503 + 504 504 + static void xilinx_axidma_register(void) 505 505 + { 506 506 + sysbus_register_withprop(&axidma_info); 507 507 + } 508 508 + 509 509 + device_init(xilinx_axidma_register)

+39

hw/xilinx_axidma.h

··· 1 1 + /* AXI DMA connection. Used until qdev provides a generic way. */ 2 2 + typedef void (*DMAPushFn)(void *opaque, 3 3 + unsigned char *buf, size_t len, uint32_t *app); 4 4 + 5 5 + struct XilinxDMAConnection { 6 6 + void *dma; 7 7 + void *client; 8 8 + 9 9 + DMAPushFn to_dma; 10 10 + DMAPushFn to_client; 11 11 + }; 12 12 + 13 13 + static inline void xlx_dma_connect_client(struct XilinxDMAConnection *dmach, 14 14 + void *c, DMAPushFn f) 15 15 + { 16 16 + dmach->client = c; 17 17 + dmach->to_client = f; 18 18 + } 19 19 + 20 20 + static inline void xlx_dma_connect_dma(struct XilinxDMAConnection *dmach, 21 21 + void *d, DMAPushFn f) 22 22 + { 23 23 + dmach->dma = d; 24 24 + dmach->to_dma = f; 25 25 + } 26 26 + 27 27 + static inline 28 28 + void xlx_dma_push_to_dma(struct XilinxDMAConnection *dmach, 29 29 + uint8_t *buf, size_t len, uint32_t *app) 30 30 + { 31 31 + dmach->to_dma(dmach->dma, buf, len, app); 32 32 + } 33 33 + static inline 34 34 + void xlx_dma_push_to_client(struct XilinxDMAConnection *dmach, 35 35 + uint8_t *buf, size_t len, uint32_t *app) 36 36 + { 37 37 + dmach->to_client(dmach->client, buf, len, app); 38 38 + } 39 39 +

+898

hw/xilinx_axienet.c

··· 1 1 + /* 2 2 + * QEMU model of Xilinx AXI-Ethernet. 3 3 + * 4 4 + * Copyright (c) 2011 Edgar E. Iglesias. 5 5 + * 6 6 + * Permission is hereby granted, free of charge, to any person obtaining a copy 7 7 + * of this software and associated documentation files (the "Software"), to deal 8 8 + * in the Software without restriction, including without limitation the rights 9 9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 10 + * copies of the Software, and to permit persons to whom the Software is 11 11 + * furnished to do so, subject to the following conditions: 12 12 + * 13 13 + * The above copyright notice and this permission notice shall be included in 14 14 + * all copies or substantial portions of the Software. 15 15 + * 16 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 22 + * THE SOFTWARE. 23 23 + */ 24 24 + 25 25 + #include "sysbus.h" 26 26 + #include "qemu-char.h" 27 27 + #include "qemu-log.h" 28 28 + #include "net.h" 29 29 + #include "net/checksum.h" 30 30 + 31 31 + #include "xilinx_axidma.h" 32 32 + 33 33 + #define DPHY(x) 34 34 + 35 35 + /* Advertisement control register. */ 36 36 + #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 37 37 + #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 38 38 + #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 39 39 + #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 40 40 + 41 41 + struct PHY { 42 42 + uint32_t regs[32]; 43 43 + 44 44 + int link; 45 45 + 46 46 + unsigned int (*read)(struct PHY *phy, unsigned int req); 47 47 + void (*write)(struct PHY *phy, unsigned int req, 48 48 + unsigned int data); 49 49 + }; 50 50 + 51 51 + static unsigned int tdk_read(struct PHY *phy, unsigned int req) 52 52 + { 53 53 + int regnum; 54 54 + unsigned r = 0; 55 55 + 56 56 + regnum = req & 0x1f; 57 57 + 58 58 + switch (regnum) { 59 59 + case 1: 60 60 + if (!phy->link) { 61 61 + break; 62 62 + } 63 63 + /* MR1. */ 64 64 + /* Speeds and modes. */ 65 65 + r |= (1 << 13) | (1 << 14); 66 66 + r |= (1 << 11) | (1 << 12); 67 67 + r |= (1 << 5); /* Autoneg complete. */ 68 68 + r |= (1 << 3); /* Autoneg able. */ 69 69 + r |= (1 << 2); /* link. */ 70 70 + r |= (1 << 1); /* link. */ 71 71 + break; 72 72 + case 5: 73 73 + /* Link partner ability. 74 74 + We are kind; always agree with whatever best mode 75 75 + the guest advertises. */ 76 76 + r = 1 << 14; /* Success. */ 77 77 + /* Copy advertised modes. */ 78 78 + r |= phy->regs[4] & (15 << 5); 79 79 + /* Autoneg support. */ 80 80 + r |= 1; 81 81 + break; 82 82 + case 17: 83 83 + /* Marvel PHY on many xilinx boards. */ 84 84 + r = 0x8000; /* 1000Mb */ 85 85 + break; 86 86 + case 18: 87 87 + { 88 88 + /* Diagnostics reg. */ 89 89 + int duplex = 0; 90 90 + int speed_100 = 0; 91 91 + 92 92 + if (!phy->link) { 93 93 + break; 94 94 + } 95 95 + 96 96 + /* Are we advertising 100 half or 100 duplex ? */ 97 97 + speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); 98 98 + speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); 99 99 + 100 100 + /* Are we advertising 10 duplex or 100 duplex ? */ 101 101 + duplex = !!(phy->regs[4] & ADVERTISE_100FULL); 102 102 + duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); 103 103 + r = (speed_100 << 10) | (duplex << 11); 104 104 + } 105 105 + break; 106 106 + 107 107 + default: 108 108 + r = phy->regs[regnum]; 109 109 + break; 110 110 + } 111 111 + DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum)); 112 112 + return r; 113 113 + } 114 114 + 115 115 + static void 116 116 + tdk_write(struct PHY *phy, unsigned int req, unsigned int data) 117 117 + { 118 118 + int regnum; 119 119 + 120 120 + regnum = req & 0x1f; 121 121 + DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data)); 122 122 + switch (regnum) { 123 123 + default: 124 124 + phy->regs[regnum] = data; 125 125 + break; 126 126 + } 127 127 + } 128 128 + 129 129 + static void 130 130 + tdk_init(struct PHY *phy) 131 131 + { 132 132 + phy->regs[0] = 0x3100; 133 133 + /* PHY Id. */ 134 134 + phy->regs[2] = 0x0300; 135 135 + phy->regs[3] = 0xe400; 136 136 + /* Autonegotiation advertisement reg. */ 137 137 + phy->regs[4] = 0x01E1; 138 138 + phy->link = 1; 139 139 + 140 140 + phy->read = tdk_read; 141 141 + phy->write = tdk_write; 142 142 + } 143 143 + 144 144 + struct MDIOBus { 145 145 + /* bus. */ 146 146 + int mdc; 147 147 + int mdio; 148 148 + 149 149 + /* decoder. */ 150 150 + enum { 151 151 + PREAMBLE, 152 152 + SOF, 153 153 + OPC, 154 154 + ADDR, 155 155 + REQ, 156 156 + TURNAROUND, 157 157 + DATA 158 158 + } state; 159 159 + unsigned int drive; 160 160 + 161 161 + unsigned int cnt; 162 162 + unsigned int addr; 163 163 + unsigned int opc; 164 164 + unsigned int req; 165 165 + unsigned int data; 166 166 + 167 167 + struct PHY *devs[32]; 168 168 + }; 169 169 + 170 170 + static void 171 171 + mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 172 172 + { 173 173 + bus->devs[addr & 0x1f] = phy; 174 174 + } 175 175 + 176 176 + #ifdef USE_THIS_DEAD_CODE 177 177 + static void 178 178 + mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr) 179 179 + { 180 180 + bus->devs[addr & 0x1f] = NULL; 181 181 + } 182 182 + #endif 183 183 + 184 184 + static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr, 185 185 + unsigned int reg) 186 186 + { 187 187 + struct PHY *phy; 188 188 + uint16_t data; 189 189 + 190 190 + phy = bus->devs[addr]; 191 191 + if (phy && phy->read) { 192 192 + data = phy->read(phy, reg); 193 193 + } else { 194 194 + data = 0xffff; 195 195 + } 196 196 + DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 197 197 + return data; 198 198 + } 199 199 + 200 200 + static void mdio_write_req(struct MDIOBus *bus, unsigned int addr, 201 201 + unsigned int reg, uint16_t data) 202 202 + { 203 203 + struct PHY *phy; 204 204 + 205 205 + DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data)); 206 206 + phy = bus->devs[addr]; 207 207 + if (phy && phy->write) { 208 208 + phy->write(phy, reg, data); 209 209 + } 210 210 + } 211 211 + 212 212 + #define DENET(x) 213 213 + 214 214 + #define R_RAF (0x000 / 4) 215 215 + enum { 216 216 + RAF_MCAST_REJ = (1 << 1), 217 217 + RAF_BCAST_REJ = (1 << 2), 218 218 + RAF_EMCF_EN = (1 << 12), 219 219 + RAF_NEWFUNC_EN = (1 << 11) 220 220 + }; 221 221 + 222 222 + #define R_IS (0x00C / 4) 223 223 + enum { 224 224 + IS_HARD_ACCESS_COMPLETE = 1, 225 225 + IS_AUTONEG = (1 << 1), 226 226 + IS_RX_COMPLETE = (1 << 2), 227 227 + IS_RX_REJECT = (1 << 3), 228 228 + IS_TX_COMPLETE = (1 << 5), 229 229 + IS_RX_DCM_LOCK = (1 << 6), 230 230 + IS_MGM_RDY = (1 << 7), 231 231 + IS_PHY_RST_DONE = (1 << 8), 232 232 + }; 233 233 + 234 234 + #define R_IP (0x010 / 4) 235 235 + #define R_IE (0x014 / 4) 236 236 + #define R_UAWL (0x020 / 4) 237 237 + #define R_UAWU (0x024 / 4) 238 238 + #define R_PPST (0x030 / 4) 239 239 + enum { 240 240 + PPST_LINKSTATUS = (1 << 0), 241 241 + PPST_PHY_LINKSTATUS = (1 << 7), 242 242 + }; 243 243 + 244 244 + #define R_STATS_RX_BYTESL (0x200 / 4) 245 245 + #define R_STATS_RX_BYTESH (0x204 / 4) 246 246 + #define R_STATS_TX_BYTESL (0x208 / 4) 247 247 + #define R_STATS_TX_BYTESH (0x20C / 4) 248 248 + #define R_STATS_RXL (0x290 / 4) 249 249 + #define R_STATS_RXH (0x294 / 4) 250 250 + #define R_STATS_RX_BCASTL (0x2a0 / 4) 251 251 + #define R_STATS_RX_BCASTH (0x2a4 / 4) 252 252 + #define R_STATS_RX_MCASTL (0x2a8 / 4) 253 253 + #define R_STATS_RX_MCASTH (0x2ac / 4) 254 254 + 255 255 + #define R_RCW0 (0x400 / 4) 256 256 + #define R_RCW1 (0x404 / 4) 257 257 + enum { 258 258 + RCW1_VLAN = (1 << 27), 259 259 + RCW1_RX = (1 << 28), 260 260 + RCW1_FCS = (1 << 29), 261 261 + RCW1_JUM = (1 << 30), 262 262 + RCW1_RST = (1 << 31), 263 263 + }; 264 264 + 265 265 + #define R_TC (0x408 / 4) 266 266 + enum { 267 267 + TC_VLAN = (1 << 27), 268 268 + TC_TX = (1 << 28), 269 269 + TC_FCS = (1 << 29), 270 270 + TC_JUM = (1 << 30), 271 271 + TC_RST = (1 << 31), 272 272 + }; 273 273 + 274 274 + #define R_EMMC (0x410 / 4) 275 275 + enum { 276 276 + EMMC_LINKSPEED_10MB = (0 << 30), 277 277 + EMMC_LINKSPEED_100MB = (1 << 30), 278 278 + EMMC_LINKSPEED_1000MB = (2 << 30), 279 279 + }; 280 280 + 281 281 + #define R_PHYC (0x414 / 4) 282 282 + 283 283 + #define R_MC (0x500 / 4) 284 284 + #define MC_EN (1 << 6) 285 285 + 286 286 + #define R_MCR (0x504 / 4) 287 287 + #define R_MWD (0x508 / 4) 288 288 + #define R_MRD (0x50c / 4) 289 289 + #define R_MIS (0x600 / 4) 290 290 + #define R_MIP (0x620 / 4) 291 291 + #define R_MIE (0x640 / 4) 292 292 + #define R_MIC (0x640 / 4) 293 293 + 294 294 + #define R_UAW0 (0x700 / 4) 295 295 + #define R_UAW1 (0x704 / 4) 296 296 + #define R_FMI (0x708 / 4) 297 297 + #define R_AF0 (0x710 / 4) 298 298 + #define R_AF1 (0x714 / 4) 299 299 + #define R_MAX (0x34 / 4) 300 300 + 301 301 + /* Indirect registers. */ 302 302 + struct TEMAC { 303 303 + struct MDIOBus mdio_bus; 304 304 + struct PHY phy; 305 305 + 306 306 + void *parent; 307 307 + }; 308 308 + 309 309 + struct XilinxAXIEnet { 310 310 + SysBusDevice busdev; 311 311 + qemu_irq irq; 312 312 + void *dmach; 313 313 + NICState *nic; 314 314 + NICConf conf; 315 315 + 316 316 + 317 317 + uint32_t c_rxmem; 318 318 + uint32_t c_txmem; 319 319 + uint32_t c_phyaddr; 320 320 + 321 321 + struct TEMAC TEMAC; 322 322 + 323 323 + /* MII regs. */ 324 324 + union { 325 325 + uint32_t regs[4]; 326 326 + struct { 327 327 + uint32_t mc; 328 328 + uint32_t mcr; 329 329 + uint32_t mwd; 330 330 + uint32_t mrd; 331 331 + }; 332 332 + } mii; 333 333 + 334 334 + struct { 335 335 + uint64_t rx_bytes; 336 336 + uint64_t tx_bytes; 337 337 + 338 338 + uint64_t rx; 339 339 + uint64_t rx_bcast; 340 340 + uint64_t rx_mcast; 341 341 + } stats; 342 342 + 343 343 + /* Receive configuration words. */ 344 344 + uint32_t rcw[2]; 345 345 + /* Transmit config. */ 346 346 + uint32_t tc; 347 347 + uint32_t emmc; 348 348 + uint32_t phyc; 349 349 + 350 350 + /* Unicast Address Word. */ 351 351 + uint32_t uaw[2]; 352 352 + /* Unicast address filter used with extended mcast. */ 353 353 + uint32_t ext_uaw[2]; 354 354 + uint32_t fmi; 355 355 + 356 356 + uint32_t regs[R_MAX]; 357 357 + 358 358 + /* Multicast filter addrs. */ 359 359 + uint32_t maddr[4][2]; 360 360 + /* 32K x 1 lookup filter. */ 361 361 + uint32_t ext_mtable[1024]; 362 362 + 363 363 + 364 364 + uint8_t *rxmem; 365 365 + }; 366 366 + 367 367 + static void axienet_rx_reset(struct XilinxAXIEnet *s) 368 368 + { 369 369 + s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN; 370 370 + } 371 371 + 372 372 + static void axienet_tx_reset(struct XilinxAXIEnet *s) 373 373 + { 374 374 + s->tc = TC_JUM | TC_TX | TC_VLAN; 375 375 + } 376 376 + 377 377 + static inline int axienet_rx_resetting(struct XilinxAXIEnet *s) 378 378 + { 379 379 + return s->rcw[1] & RCW1_RST; 380 380 + } 381 381 + 382 382 + static inline int axienet_rx_enabled(struct XilinxAXIEnet *s) 383 383 + { 384 384 + return s->rcw[1] & RCW1_RX; 385 385 + } 386 386 + 387 387 + static inline int axienet_extmcf_enabled(struct XilinxAXIEnet *s) 388 388 + { 389 389 + return !!(s->regs[R_RAF] & RAF_EMCF_EN); 390 390 + } 391 391 + 392 392 + static inline int axienet_newfunc_enabled(struct XilinxAXIEnet *s) 393 393 + { 394 394 + return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN); 395 395 + } 396 396 + 397 397 + static void axienet_reset(struct XilinxAXIEnet *s) 398 398 + { 399 399 + axienet_rx_reset(s); 400 400 + axienet_tx_reset(s); 401 401 + 402 402 + s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS; 403 403 + s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE; 404 404 + 405 405 + s->emmc = EMMC_LINKSPEED_100MB; 406 406 + } 407 407 + 408 408 + static void enet_update_irq(struct XilinxAXIEnet *s) 409 409 + { 410 410 + s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE]; 411 411 + qemu_set_irq(s->irq, !!s->regs[R_IP]); 412 412 + } 413 413 + 414 414 + static uint32_t enet_readl(void *opaque, target_phys_addr_t addr) 415 415 + { 416 416 + struct XilinxAXIEnet *s = opaque; 417 417 + uint32_t r = 0; 418 418 + addr >>= 2; 419 419 + 420 420 + switch (addr) { 421 421 + case R_RCW0: 422 422 + case R_RCW1: 423 423 + r = s->rcw[addr & 1]; 424 424 + break; 425 425 + 426 426 + case R_TC: 427 427 + r = s->tc; 428 428 + break; 429 429 + 430 430 + case R_EMMC: 431 431 + r = s->emmc; 432 432 + break; 433 433 + 434 434 + case R_PHYC: 435 435 + r = s->phyc; 436 436 + break; 437 437 + 438 438 + case R_MCR: 439 439 + r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */ 440 440 + break; 441 441 + 442 442 + case R_STATS_RX_BYTESL: 443 443 + case R_STATS_RX_BYTESH: 444 444 + r = s->stats.rx_bytes >> (32 * (addr & 1)); 445 445 + break; 446 446 + 447 447 + case R_STATS_TX_BYTESL: 448 448 + case R_STATS_TX_BYTESH: 449 449 + r = s->stats.tx_bytes >> (32 * (addr & 1)); 450 450 + break; 451 451 + 452 452 + case R_STATS_RXL: 453 453 + case R_STATS_RXH: 454 454 + r = s->stats.rx >> (32 * (addr & 1)); 455 455 + break; 456 456 + case R_STATS_RX_BCASTL: 457 457 + case R_STATS_RX_BCASTH: 458 458 + r = s->stats.rx_bcast >> (32 * (addr & 1)); 459 459 + break; 460 460 + case R_STATS_RX_MCASTL: 461 461 + case R_STATS_RX_MCASTH: 462 462 + r = s->stats.rx_mcast >> (32 * (addr & 1)); 463 463 + break; 464 464 + 465 465 + case R_MC: 466 466 + case R_MWD: 467 467 + case R_MRD: 468 468 + r = s->mii.regs[addr & 3]; 469 469 + break; 470 470 + 471 471 + case R_UAW0: 472 472 + case R_UAW1: 473 473 + r = s->uaw[addr & 1]; 474 474 + break; 475 475 + 476 476 + case R_UAWU: 477 477 + case R_UAWL: 478 478 + r = s->ext_uaw[addr & 1]; 479 479 + break; 480 480 + 481 481 + case R_FMI: 482 482 + r = s->fmi; 483 483 + break; 484 484 + 485 485 + case R_AF0: 486 486 + case R_AF1: 487 487 + r = s->maddr[s->fmi & 3][addr & 1]; 488 488 + break; 489 489 + 490 490 + case 0x8000 ... 0x83ff: 491 491 + r = s->ext_mtable[addr - 0x8000]; 492 492 + break; 493 493 + 494 494 + default: 495 495 + if (addr < ARRAY_SIZE(s->regs)) { 496 496 + r = s->regs[addr]; 497 497 + } 498 498 + DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 499 499 + __func__, addr * 4, r)); 500 500 + break; 501 501 + } 502 502 + return r; 503 503 + } 504 504 + 505 505 + static void 506 506 + enet_writel(void *opaque, target_phys_addr_t addr, uint32_t value) 507 507 + { 508 508 + struct XilinxAXIEnet *s = opaque; 509 509 + struct TEMAC *t = &s->TEMAC; 510 510 + 511 511 + addr >>= 2; 512 512 + switch (addr) { 513 513 + case R_RCW0: 514 514 + case R_RCW1: 515 515 + s->rcw[addr & 1] = value; 516 516 + if ((addr & 1) && value & RCW1_RST) { 517 517 + axienet_rx_reset(s); 518 518 + } 519 519 + break; 520 520 + 521 521 + case R_TC: 522 522 + s->tc = value; 523 523 + if (value & TC_RST) { 524 524 + axienet_tx_reset(s); 525 525 + } 526 526 + break; 527 527 + 528 528 + case R_EMMC: 529 529 + s->emmc = value; 530 530 + break; 531 531 + 532 532 + case R_PHYC: 533 533 + s->phyc = value; 534 534 + break; 535 535 + 536 536 + case R_MC: 537 537 + value &= ((1 < 7) - 1); 538 538 + 539 539 + /* Enable the MII. */ 540 540 + if (value & MC_EN) { 541 541 + unsigned int miiclkdiv = value & ((1 << 6) - 1); 542 542 + if (!miiclkdiv) { 543 543 + qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n"); 544 544 + } 545 545 + } 546 546 + s->mii.mc = value; 547 547 + break; 548 548 + 549 549 + case R_MCR: { 550 550 + unsigned int phyaddr = (value >> 24) & 0x1f; 551 551 + unsigned int regaddr = (value >> 16) & 0x1f; 552 552 + unsigned int op = (value >> 14) & 3; 553 553 + unsigned int initiate = (value >> 11) & 1; 554 554 + 555 555 + if (initiate) { 556 556 + if (op == 1) { 557 557 + mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd); 558 558 + } else if (op == 2) { 559 559 + s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr); 560 560 + } else { 561 561 + qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op); 562 562 + } 563 563 + } 564 564 + s->mii.mcr = value; 565 565 + break; 566 566 + } 567 567 + 568 568 + case R_MWD: 569 569 + case R_MRD: 570 570 + s->mii.regs[addr & 3] = value; 571 571 + break; 572 572 + 573 573 + 574 574 + case R_UAW0: 575 575 + case R_UAW1: 576 576 + s->uaw[addr & 1] = value; 577 577 + break; 578 578 + 579 579 + case R_UAWL: 580 580 + case R_UAWU: 581 581 + s->ext_uaw[addr & 1] = value; 582 582 + break; 583 583 + 584 584 + case R_FMI: 585 585 + s->fmi = value; 586 586 + break; 587 587 + 588 588 + case R_AF0: 589 589 + case R_AF1: 590 590 + s->maddr[s->fmi & 3][addr & 1] = value; 591 591 + break; 592 592 + 593 593 + case 0x8000 ... 0x83ff: 594 594 + s->ext_mtable[addr - 0x8000] = value; 595 595 + break; 596 596 + 597 597 + default: 598 598 + DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", 599 599 + __func__, addr * 4, value)); 600 600 + if (addr < ARRAY_SIZE(s->regs)) { 601 601 + s->regs[addr] = value; 602 602 + } 603 603 + break; 604 604 + } 605 605 + enet_update_irq(s); 606 606 + } 607 607 + 608 608 + static CPUReadMemoryFunc * const enet_read[] = { 609 609 + &enet_readl, 610 610 + &enet_readl, 611 611 + &enet_readl, 612 612 + }; 613 613 + 614 614 + static CPUWriteMemoryFunc * const enet_write[] = { 615 615 + &enet_writel, 616 616 + &enet_writel, 617 617 + &enet_writel, 618 618 + }; 619 619 + 620 620 + static int eth_can_rx(VLANClientState *nc) 621 621 + { 622 622 + struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque; 623 623 + 624 624 + /* RX enabled? */ 625 625 + return !axienet_rx_resetting(s) && axienet_rx_enabled(s); 626 626 + } 627 627 + 628 628 + static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1) 629 629 + { 630 630 + int match = 1; 631 631 + 632 632 + if (memcmp(buf, &f0, 4)) { 633 633 + match = 0; 634 634 + } 635 635 + 636 636 + if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) { 637 637 + match = 0; 638 638 + } 639 639 + 640 640 + return match; 641 641 + } 642 642 + 643 643 + static ssize_t eth_rx(VLANClientState *nc, const uint8_t *buf, size_t size) 644 644 + { 645 645 + struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque; 646 646 + static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 647 647 + 0xff, 0xff, 0xff}; 648 648 + static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52}; 649 649 + uint32_t app[6] = {0}; 650 650 + int promisc = s->fmi & (1 << 31); 651 651 + int unicast, broadcast, multicast, ip_multicast = 0; 652 652 + uint32_t csum32; 653 653 + uint16_t csum16; 654 654 + int i; 655 655 + 656 656 + s = s; 657 657 + DENET(qemu_log("%s: %zd bytes\n", __func__, size)); 658 658 + 659 659 + unicast = ~buf[0] & 0x1; 660 660 + broadcast = memcmp(buf, sa_bcast, 6) == 0; 661 661 + multicast = !unicast && !broadcast; 662 662 + if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) { 663 663 + ip_multicast = 1; 664 664 + } 665 665 + 666 666 + /* Jumbo or vlan sizes ? */ 667 667 + if (!(s->rcw[1] & RCW1_JUM)) { 668 668 + if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) { 669 669 + return size; 670 670 + } 671 671 + } 672 672 + 673 673 + /* Basic Address filters. If you want to use the extended filters 674 674 + you'll generally have to place the ethernet mac into promiscuous mode 675 675 + to avoid the basic filtering from dropping most frames. */ 676 676 + if (!promisc) { 677 677 + if (unicast) { 678 678 + if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) { 679 679 + return size; 680 680 + } 681 681 + } else { 682 682 + if (broadcast) { 683 683 + /* Broadcast. */ 684 684 + if (s->regs[R_RAF] & RAF_BCAST_REJ) { 685 685 + return size; 686 686 + } 687 687 + } else { 688 688 + int drop = 1; 689 689 + 690 690 + /* Multicast. */ 691 691 + if (s->regs[R_RAF] & RAF_MCAST_REJ) { 692 692 + return size; 693 693 + } 694 694 + 695 695 + for (i = 0; i < 4; i++) { 696 696 + if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) { 697 697 + drop = 0; 698 698 + break; 699 699 + } 700 700 + } 701 701 + 702 702 + if (drop) { 703 703 + return size; 704 704 + } 705 705 + } 706 706 + } 707 707 + } 708 708 + 709 709 + /* Extended mcast filtering enabled? */ 710 710 + if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) { 711 711 + if (unicast) { 712 712 + if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) { 713 713 + return size; 714 714 + } 715 715 + } else { 716 716 + if (broadcast) { 717 717 + /* Broadcast. ??? */ 718 718 + if (s->regs[R_RAF] & RAF_BCAST_REJ) { 719 719 + return size; 720 720 + } 721 721 + } else { 722 722 + int idx, bit; 723 723 + 724 724 + /* Multicast. */ 725 725 + if (!memcmp(buf, sa_ipmcast, 3)) { 726 726 + return size; 727 727 + } 728 728 + 729 729 + idx = (buf[4] & 0x7f) << 8; 730 730 + idx |= buf[5]; 731 731 + 732 732 + bit = 1 << (idx & 0x1f); 733 733 + idx >>= 5; 734 734 + 735 735 + if (!(s->ext_mtable[idx] & bit)) { 736 736 + return size; 737 737 + } 738 738 + } 739 739 + } 740 740 + } 741 741 + 742 742 + if (size < 12) { 743 743 + s->regs[R_IS] |= IS_RX_REJECT; 744 744 + enet_update_irq(s); 745 745 + return -1; 746 746 + } 747 747 + 748 748 + if (size > (s->c_rxmem - 4)) { 749 749 + size = s->c_rxmem - 4; 750 750 + } 751 751 + 752 752 + memcpy(s->rxmem, buf, size); 753 753 + memset(s->rxmem + size, 0, 4); /* Clear the FCS. */ 754 754 + 755 755 + if (s->rcw[1] & RCW1_FCS) { 756 756 + size += 4; /* fcs is inband. */ 757 757 + } 758 758 + 759 759 + app[0] = 5 << 28; 760 760 + csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14); 761 761 + /* Fold it once. */ 762 762 + csum32 = (csum32 & 0xffff) + (csum32 >> 16); 763 763 + /* And twice to get rid of possible carries. */ 764 764 + csum16 = (csum32 & 0xffff) + (csum32 >> 16); 765 765 + app[3] = csum16; 766 766 + app[4] = size & 0xffff; 767 767 + 768 768 + s->stats.rx_bytes += size; 769 769 + s->stats.rx++; 770 770 + if (multicast) { 771 771 + s->stats.rx_mcast++; 772 772 + app[2] |= 1 | (ip_multicast << 1); 773 773 + } else if (broadcast) { 774 774 + s->stats.rx_bcast++; 775 775 + app[2] |= 1 << 3; 776 776 + } 777 777 + 778 778 + /* Good frame. */ 779 779 + app[2] |= 1 << 6; 780 780 + 781 781 + xlx_dma_push_to_dma(s->dmach, (void *)s->rxmem, size, app); 782 782 + 783 783 + s->regs[R_IS] |= IS_RX_COMPLETE; 784 784 + enet_update_irq(s); 785 785 + return size; 786 786 + } 787 787 + 788 788 + static void eth_cleanup(VLANClientState *nc) 789 789 + { 790 790 + /* FIXME. */ 791 791 + struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque; 792 792 + qemu_free(s->rxmem); 793 793 + qemu_free(s); 794 794 + } 795 795 + 796 796 + static void 797 797 + axienet_stream_push(void *opaque, uint8_t *buf, size_t size, uint32_t *hdr) 798 798 + { 799 799 + struct XilinxAXIEnet *s = opaque; 800 800 + 801 801 + /* TX enable ? */ 802 802 + if (!(s->tc & TC_TX)) { 803 803 + return; 804 804 + } 805 805 + 806 806 + /* Jumbo or vlan sizes ? */ 807 807 + if (!(s->tc & TC_JUM)) { 808 808 + if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) { 809 809 + return; 810 810 + } 811 811 + } 812 812 + 813 813 + if (hdr[0] & 1) { 814 814 + unsigned int start_off = hdr[1] >> 16; 815 815 + unsigned int write_off = hdr[1] & 0xffff; 816 816 + uint32_t tmp_csum; 817 817 + uint16_t csum; 818 818 + 819 819 + tmp_csum = net_checksum_add(size - start_off, 820 820 + (uint8_t *)buf + start_off); 821 821 + /* Accumulate the seed. */ 822 822 + tmp_csum += hdr[2] & 0xffff; 823 823 + 824 824 + /* Fold the 32bit partial checksum. */ 825 825 + csum = net_checksum_finish(tmp_csum); 826 826 + 827 827 + /* Writeback. */ 828 828 + buf[write_off] = csum >> 8; 829 829 + buf[write_off + 1] = csum & 0xff; 830 830 + } 831 831 + 832 832 + qemu_send_packet(&s->nic->nc, buf, size); 833 833 + 834 834 + s->stats.tx_bytes += size; 835 835 + s->regs[R_IS] |= IS_TX_COMPLETE; 836 836 + enet_update_irq(s); 837 837 + } 838 838 + 839 839 + static NetClientInfo net_xilinx_enet_info = { 840 840 + .type = NET_CLIENT_TYPE_NIC, 841 841 + .size = sizeof(NICState), 842 842 + .can_receive = eth_can_rx, 843 843 + .receive = eth_rx, 844 844 + .cleanup = eth_cleanup, 845 845 + }; 846 846 + 847 847 + static int xilinx_enet_init(SysBusDevice *dev) 848 848 + { 849 849 + struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev); 850 850 + int enet_regs; 851 851 + 852 852 + sysbus_init_irq(dev, &s->irq); 853 853 + 854 854 + if (!s->dmach) { 855 855 + hw_error("Unconnected Xilinx Ethernet MAC.\n"); 856 856 + } 857 857 + 858 858 + xlx_dma_connect_client(s->dmach, s, axienet_stream_push); 859 859 + 860 860 + enet_regs = cpu_register_io_memory(enet_read, enet_write, s, 861 861 + DEVICE_LITTLE_ENDIAN); 862 862 + sysbus_init_mmio(dev, 0x40000, enet_regs); 863 863 + 864 864 + qemu_macaddr_default_if_unset(&s->conf.macaddr); 865 865 + s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, 866 866 + dev->qdev.info->name, dev->qdev.id, s); 867 867 + qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); 868 868 + 869 869 + tdk_init(&s->TEMAC.phy); 870 870 + mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr); 871 871 + 872 872 + s->TEMAC.parent = s; 873 873 + 874 874 + s->rxmem = qemu_malloc(s->c_rxmem); 875 875 + axienet_reset(s); 876 876 + 877 877 + return 0; 878 878 + } 879 879 + 880 880 + static SysBusDeviceInfo xilinx_enet_info = { 881 881 + .init = xilinx_enet_init, 882 882 + .qdev.name = "xilinx,axienet", 883 883 + .qdev.size = sizeof(struct XilinxAXIEnet), 884 884 + .qdev.props = (Property[]) { 885 885 + DEFINE_PROP_UINT32("phyaddr", struct XilinxAXIEnet, c_phyaddr, 7), 886 886 + DEFINE_PROP_UINT32("c_rxmem", struct XilinxAXIEnet, c_rxmem, 0x1000), 887 887 + DEFINE_PROP_UINT32("c_txmem", struct XilinxAXIEnet, c_txmem, 0x1000), 888 888 + DEFINE_PROP_PTR("dmach", struct XilinxAXIEnet, dmach), 889 889 + DEFINE_NIC_PROPERTIES(struct XilinxAXIEnet, conf), 890 890 + DEFINE_PROP_END_OF_LIST(), 891 891 + } 892 892 + }; 893 893 + static void xilinx_enet_register(void) 894 894 + { 895 895 + sysbus_register_withprop(&xilinx_enet_info); 896 896 + } 897 897 + 898 898 + device_init(xilinx_enet_register)