jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/xtensa: Use env_cpu, env_archcpu
Cleanup in the boilerplate that each target must define.
Replace xtensa_env_get_cpu with env_archcpu. The combination
CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h"
so that the definition of env_cpu is available.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+22
-33
+1
-1
hw/xtensa/pic_cpu.c
+1
-1
hw/xtensa/pic_cpu.c
+1
-1
linux-user/xtensa/cpu_loop.c
+1
-1
linux-user/xtensa/cpu_loop.c
+6
-11
target/xtensa/cpu.h
+6
-11
target/xtensa/cpu.h
···
559
559
CPUXtensaState env;
560
560
};
561
561
562
-
static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
563
-
{
564
-
return container_of(env, XtensaCPU, env);
565
-
}
566
-
567
562
#define ENV_OFFSET offsetof(XtensaCPU, env)
568
563
569
564
···
724
719
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
725
720
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
726
721
722
+
typedef CPUXtensaState CPUArchState;
723
+
typedef XtensaCPU ArchCPU;
724
+
725
+
#include "exec/cpu-all.h"
726
+
727
727
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
728
728
target_ulong *cs_base, uint32_t *flags)
729
729
{
730
-
CPUState *cs = CPU(xtensa_env_get_cpu(env));
730
+
CPUState *cs = env_cpu(env);
731
731
732
732
*pc = env->pc;
733
733
*cs_base = 0;
···
796
796
*flags |= XTENSA_TBFLAG_YIELD;
797
797
}
798
798
}
799
-
800
-
typedef CPUXtensaState CPUArchState;
801
-
typedef XtensaCPU ArchCPU;
802
-
803
-
#include "exec/cpu-all.h"
804
799
805
800
#endif
+2
-2
target/xtensa/dbg_helper.c
+2
-2
target/xtensa/dbg_helper.c
···
71
71
static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
72
72
uint32_t dbreakc)
73
73
{
74
-
CPUState *cs = CPU(xtensa_env_get_cpu(env));
74
+
CPUState *cs = env_cpu(env);
75
75
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
76
76
uint32_t mask = dbreakc | ~DBREAKC_MASK;
77
77
···
118
118
set_dbreak(env, i, env->sregs[DBREAKA + i], v);
119
119
} else {
120
120
if (env->cpu_watchpoint[i]) {
121
-
CPUState *cs = CPU(xtensa_env_get_cpu(env));
121
+
CPUState *cs = env_cpu(env);
122
122
123
123
cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
124
124
env->cpu_watchpoint[i] = NULL;
+4
-5
target/xtensa/exc_helper.c
+4
-5
target/xtensa/exc_helper.c
···
34
34
35
35
void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
36
36
{
37
-
CPUState *cs = CPU(xtensa_env_get_cpu(env));
37
+
CPUState *cs = env_cpu(env);
38
38
39
39
cs->exception_index = excp;
40
40
if (excp == EXCP_YIELD) {
···
100
100
101
101
void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
102
102
{
103
-
CPUState *cpu;
103
+
CPUState *cpu = env_cpu(env);
104
104
105
105
env->pc = pc;
106
106
env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
···
111
111
qemu_mutex_unlock_iothread();
112
112
113
113
if (env->pending_irq_level) {
114
-
cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
114
+
cpu_loop_exit(cpu);
115
115
return;
116
116
}
117
117
118
-
cpu = CPU(xtensa_env_get_cpu(env));
119
118
cpu->halted = 1;
120
119
HELPER(exception)(env, EXCP_HLT);
121
120
}
···
165
164
(env->config->level_mask[level] &
166
165
env->sregs[INTSET] &
167
166
env->sregs[INTENABLE])) {
168
-
CPUState *cs = CPU(xtensa_env_get_cpu(env));
167
+
CPUState *cs = env_cpu(env);
169
168
170
169
if (level > 1) {
171
170
env->sregs[EPC1 + level - 1] = env->pc;
+1
-1
target/xtensa/helper.c
+1
-1
target/xtensa/helper.c
+6
-11
target/xtensa/mmu_helper.c
+6
-11
target/xtensa/mmu_helper.c
···
71
71
72
72
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
73
73
{
74
-
XtensaCPU *cpu = xtensa_env_get_cpu(env);
75
-
76
74
v = (v & 0xffffff00) | 0x1;
77
75
if (v != env->sregs[RASID]) {
78
76
env->sregs[RASID] = v;
79
-
tlb_flush(CPU(cpu));
77
+
tlb_flush(env_cpu(env));
80
78
}
81
79
}
82
80
···
276
274
unsigned wi, unsigned ei,
277
275
uint32_t vpn, uint32_t pte)
278
276
{
279
-
XtensaCPU *cpu = xtensa_env_get_cpu(env);
280
-
CPUState *cs = CPU(cpu);
277
+
CPUState *cs = env_cpu(env);
281
278
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
282
279
283
280
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
···
503
500
uint32_t wi;
504
501
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
505
502
if (entry->variable && entry->asid) {
506
-
tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
503
+
tlb_flush_page(env_cpu(env), entry->vaddr);
507
504
entry->asid = 0;
508
505
}
509
506
}
···
844
841
845
842
static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
846
843
{
847
-
CPUState *cs = CPU(xtensa_env_get_cpu(env));
844
+
CPUState *cs = env_cpu(env);
848
845
uint32_t paddr;
849
846
uint32_t page_size;
850
847
unsigned access;
···
924
921
925
922
void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v)
926
923
{
927
-
XtensaCPU *cpu = xtensa_env_get_cpu(env);
928
-
929
924
v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1;
930
925
931
926
if (v != env->sregs[MPUENB]) {
932
927
env->sregs[MPUENB] = v;
933
-
tlb_flush(CPU(cpu));
928
+
tlb_flush(env_cpu(env));
934
929
}
935
930
}
936
931
···
942
937
env->mpu_fg[segment].vaddr = v & -env->config->mpu_align;
943
938
env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK;
944
939
env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v);
945
-
tlb_flush(CPU(xtensa_env_get_cpu(env)));
940
+
tlb_flush(env_cpu(env));
946
941
}
947
942
}
948
943