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target/mips: Fix loongson multimedia condition instructions

Loongson multimedia condition instructions were previously implemented as
write 0 to rd due to lack of documentation. So I just confirmed with Loongson
about their encoding and implemented them correctly.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200324122212.11156-1-jiaxun.yang@flygoat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

authored by

Jiaxun Yang and committed by
Richard Henderson 84878f4c 12781462

+31 -4
+31 -4
target/mips/translate.c
··· 5529 5529 { 5530 5530 uint32_t opc, shift_max; 5531 5531 TCGv_i64 t0, t1; 5532 + TCGCond cond; 5532 5533 5533 5534 opc = MASK_LMI(ctx->opcode); 5534 5535 switch (opc) { ··· 5862 5863 5863 5864 case OPC_SEQU_CP2: 5864 5865 case OPC_SEQ_CP2: 5866 + cond = TCG_COND_EQ; 5867 + goto do_cc_cond; 5868 + break; 5865 5869 case OPC_SLTU_CP2: 5870 + cond = TCG_COND_LTU; 5871 + goto do_cc_cond; 5872 + break; 5866 5873 case OPC_SLT_CP2: 5874 + cond = TCG_COND_LT; 5875 + goto do_cc_cond; 5876 + break; 5867 5877 case OPC_SLEU_CP2: 5878 + cond = TCG_COND_LEU; 5879 + goto do_cc_cond; 5880 + break; 5868 5881 case OPC_SLE_CP2: 5869 - /* 5870 - * ??? Document is unclear: Set FCC[CC]. Does that mean the 5871 - * FD field is the CC field? 5872 - */ 5882 + cond = TCG_COND_LE; 5883 + do_cc_cond: 5884 + { 5885 + int cc = (ctx->opcode >> 8) & 0x7; 5886 + TCGv_i64 t64 = tcg_temp_new_i64(); 5887 + TCGv_i32 t32 = tcg_temp_new_i32(); 5888 + 5889 + tcg_gen_setcond_i64(cond, t64, t0, t1); 5890 + tcg_gen_extrl_i64_i32(t32, t64); 5891 + tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32, 5892 + get_fp_bit(cc), 1); 5893 + 5894 + tcg_temp_free_i32(t32); 5895 + tcg_temp_free_i64(t64); 5896 + } 5897 + goto no_rd; 5898 + break; 5873 5899 default: 5874 5900 MIPS_INVAL("loongson_cp2"); 5875 5901 generate_exception_end(ctx, EXCP_RI); ··· 5878 5904 5879 5905 gen_store_fpr64(ctx, t0, rd); 5880 5906 5907 + no_rd: 5881 5908 tcg_temp_free_i64(t0); 5882 5909 tcg_temp_free_i64(t1); 5883 5910 }