jcs.org / qemu
qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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target/arm: Add isar_feature_aa32_vfp_simd

Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

authored by

Richard Henderson and committed by
Peter Maydell 7fbc6a40 25f1d9f3

+37 -26
+10 -10
hw/intc/armv7m_nvic.c
··· 1262 1262 case 0xd84: /* CSSELR */ 1263 1263 return cpu->env.v7m.csselr[attrs.secure]; 1264 1264 case 0xd88: /* CPACR */ 1265 - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1265 + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { 1266 1266 return 0; 1267 1267 } 1268 1268 return cpu->env.v7m.cpacr[attrs.secure]; 1269 1269 case 0xd8c: /* NSACR */ 1270 - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1270 + if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { 1271 1271 return 0; 1272 1272 } 1273 1273 return cpu->env.v7m.nsacr; ··· 1417 1417 } 1418 1418 return cpu->env.v7m.sfar; 1419 1419 case 0xf34: /* FPCCR */ 1420 - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1420 + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { 1421 1421 return 0; 1422 1422 } 1423 1423 if (attrs.secure) { ··· 1444 1444 return value; 1445 1445 } 1446 1446 case 0xf38: /* FPCAR */ 1447 - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1447 + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { 1448 1448 return 0; 1449 1449 } 1450 1450 return cpu->env.v7m.fpcar[attrs.secure]; 1451 1451 case 0xf3c: /* FPDSCR */ 1452 - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1452 + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { 1453 1453 return 0; 1454 1454 } 1455 1455 return cpu->env.v7m.fpdscr[attrs.secure]; ··· 1711 1711 } 1712 1712 break; 1713 1713 case 0xd88: /* CPACR */ 1714 - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1714 + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1715 1715 /* We implement only the Floating Point extension's CP10/CP11 */ 1716 1716 cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); 1717 1717 } 1718 1718 break; 1719 1719 case 0xd8c: /* NSACR */ 1720 - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1720 + if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { 1721 1721 /* We implement only the Floating Point extension's CP10/CP11 */ 1722 1722 cpu->env.v7m.nsacr = value & (3 << 10); 1723 1723 } ··· 1951 1951 break; 1952 1952 } 1953 1953 case 0xf34: /* FPCCR */ 1954 - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 1954 + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1955 1955 /* Not all bits here are banked. */ 1956 1956 uint32_t fpccr_s; 1957 1957 ··· 2005 2005 } 2006 2006 break; 2007 2007 case 0xf38: /* FPCAR */ 2008 - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 2008 + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 2009 2009 value &= ~7; 2010 2010 cpu->env.v7m.fpcar[attrs.secure] = value; 2011 2011 } 2012 2012 break; 2013 2013 case 0xf3c: /* FPDSCR */ 2014 - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { 2014 + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 2015 2015 value &= 0x07c00000; 2016 2016 cpu->env.v7m.fpdscr[attrs.secure] = value; 2017 2017 }
+2 -2
linux-user/arm/signal.c
··· 346 346 setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]); 347 347 /* Save coprocessor signal frame. */ 348 348 regspace = uc->tuc_regspace; 349 - if (arm_feature(env, ARM_FEATURE_VFP)) { 349 + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { 350 350 regspace = setup_sigframe_v2_vfp(regspace, env); 351 351 } 352 352 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { ··· 671 671 672 672 /* Restore coprocessor signal frame */ 673 673 regspace = uc->tuc_regspace; 674 - if (arm_feature(env, ARM_FEATURE_VFP)) { 674 + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { 675 675 regspace = restore_sigframe_v2_vfp(env, regspace); 676 676 if (!regspace) { 677 677 return 1;
+6 -5
target/arm/arch_dump.c
··· 363 363 int cpuid, void *opaque) 364 364 { 365 365 struct arm_note note; 366 - CPUARMState *env = &ARM_CPU(cs)->env; 366 + ARMCPU *cpu = ARM_CPU(cs); 367 + CPUARMState *env = &cpu->env; 367 368 DumpState *s = opaque; 368 - int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP); 369 + int ret, i; 370 + bool fpvalid = cpu_isar_feature(aa32_vfp_simd, cpu); 369 371 370 372 arm_note_init(&note, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus)); 371 373 ··· 444 446 ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) 445 447 { 446 448 ARMCPU *cpu = ARM_CPU(first_cpu); 447 - CPUARMState *env = &cpu->env; 448 449 size_t note_size; 449 450 450 451 if (class == ELFCLASS64) { ··· 452 453 note_size += AARCH64_PRFPREG_NOTE_SIZE; 453 454 #ifdef TARGET_AARCH64 454 455 if (cpu_isar_feature(aa64_sve, cpu)) { 455 - note_size += AARCH64_SVE_NOTE_SIZE(env); 456 + note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env); 456 457 } 457 458 #endif 458 459 } else { 459 460 note_size = ARM_PRSTATUS_NOTE_SIZE; 460 - if (arm_feature(env, ARM_FEATURE_VFP)) { 461 + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 461 462 note_size += ARM_VFP_NOTE_SIZE; 462 463 } 463 464 }
+2 -2
target/arm/cpu.c
··· 293 293 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 294 294 } 295 295 296 - if (arm_feature(env, ARM_FEATURE_VFP)) { 296 + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 297 297 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 298 298 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 299 299 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; ··· 1011 1011 int numvfpregs = 0; 1012 1012 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1013 1013 numvfpregs = 32; 1014 - } else if (arm_feature(env, ARM_FEATURE_VFP)) { 1014 + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1015 1015 numvfpregs = 16; 1016 1016 } 1017 1017 for (i = 0; i < numvfpregs; i++) {
+9
target/arm/cpu.h
··· 3450 3450 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3451 3451 } 3452 3452 3453 + static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3454 + { 3455 + /* 3456 + * Return true if either VFP or SIMD is implemented. 3457 + * In this case, a minimum of VFP w/ D0-D15. 3458 + */ 3459 + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3460 + } 3461 + 3453 3462 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3454 3463 { 3455 3464 /* Return true if D16-D31 are implemented */
+2 -2
target/arm/helper.c
··· 894 894 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. 895 895 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. 896 896 */ 897 - if (arm_feature(env, ARM_FEATURE_VFP)) { 897 + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { 898 898 /* VFP coprocessor: cp10 & cp11 [23:20] */ 899 899 mask |= (1 << 31) | (1 << 30) | (0xf << 20); 900 900 ··· 7814 7814 } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { 7815 7815 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 7816 7816 35, "arm-vfp3.xml", 0); 7817 - } else if (arm_feature(env, ARM_FEATURE_VFP)) { 7817 + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 7818 7818 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 7819 7819 19, "arm-vfp.xml", 0); 7820 7820 }
+6 -5
target/arm/m_helper.c
··· 738 738 */ 739 739 uint32_t sig = 0xfefa125a; 740 740 741 - if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) { 741 + if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) 742 + || (lr & R_V7M_EXCRET_FTYPE_MASK)) { 742 743 sig |= 1; 743 744 } 744 745 return sig; ··· 841 842 842 843 if (dotailchain) { 843 844 /* Sanitize LR FType and PREFIX bits */ 844 - if (!arm_feature(env, ARM_FEATURE_VFP)) { 845 + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { 845 846 lr |= R_V7M_EXCRET_FTYPE_MASK; 846 847 } 847 848 lr = deposit32(lr, 24, 8, 0xff); ··· 1373 1374 1374 1375 ftype = excret & R_V7M_EXCRET_FTYPE_MASK; 1375 1376 1376 - if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { 1377 + if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) { 1377 1378 qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception " 1378 1379 "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " 1379 1380 "if FPU not present\n", ··· 2450 2451 * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0, 2451 2452 * RES0 if the FPU is not present, and is stored in the S bank 2452 2453 */ 2453 - if (arm_feature(env, ARM_FEATURE_VFP) && 2454 + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) && 2454 2455 extract32(env->v7m.nsacr, 10, 1)) { 2455 2456 env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; 2456 2457 env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK; ··· 2565 2566 env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; 2566 2567 env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; 2567 2568 } 2568 - if (arm_feature(env, ARM_FEATURE_VFP)) { 2569 + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { 2569 2570 /* 2570 2571 * SFPA is RAZ/WI from NS or if no FPU. 2571 2572 * FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.