jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/arm/allwinner-h3: add System Control module
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200311221854.30370-6-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Niek Linnenbank
and committed by
Peter Maydell
7e83c9dd
2e4dfe80
+219
-1
+8
-1
hw/arm/allwinner-h3.c
+8
-1
hw/arm/allwinner-h3.c
···
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37
[AW_H3_SRAM_A1] = 0x00000000,
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[AW_H3_SRAM_A2] = 0x00044000,
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[AW_H3_SRAM_C] = 0x00010000,
40
+
[AW_H3_SYSCTRL] = 0x01c00000,
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[AW_H3_EHCI0] = 0x01c1a000,
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[AW_H3_OHCI0] = 0x01c1a400,
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[AW_H3_EHCI1] = 0x01c1b000,
···
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} unimplemented[] = {
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{ "d-engine", 0x01000000, 4 * MiB },
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{ "d-inter", 0x01400000, 128 * KiB },
69
-
{ "syscon", 0x01c00000, 4 * KiB },
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{ "dma", 0x01c02000, 4 * KiB },
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{ "nfdc", 0x01c03000, 4 * KiB },
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{ "ts", 0x01c06000, 4 * KiB },
···
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sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
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TYPE_AW_H3_CCU);
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+
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sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
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TYPE_AW_H3_SYSCTRL);
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}
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static void allwinner_h3_realize(DeviceState *dev, Error **errp)
···
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/* Clock Control Unit */
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qdev_init_nofail(DEVICE(&s->ccu));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
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+
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+
/* System Control */
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+
qdev_init_nofail(DEVICE(&s->sysctrl));
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+
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
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/* Universal Serial Bus */
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sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
+1
hw/misc/Makefile.objs
+1
hw/misc/Makefile.objs
···
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29
common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o
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common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-ccu.o
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+
common-obj-$(CONFIG_ALLWINNER_H3) += allwinner-h3-sysctrl.o
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common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o
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common-obj-$(CONFIG_NSERIES) += cbus.o
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common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o
+140
hw/misc/allwinner-h3-sysctrl.c
+140
hw/misc/allwinner-h3-sysctrl.c
···
1
+
/*
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+
* Allwinner H3 System Control emulation
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+
*
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+
* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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+
*
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* This program is free software: you can redistribute it and/or modify
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+
* it under the terms of the GNU General Public License as published by
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+
* the Free Software Foundation, either version 2 of the License, or
9
+
* (at your option) any later version.
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+
*
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* This program is distributed in the hope that it will be useful,
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+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
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+
*
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+
* You should have received a copy of the GNU General Public License
17
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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+
*/
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+
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/misc/allwinner-h3-sysctrl.h"
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+
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/* System Control register offsets */
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enum {
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REG_VER = 0x24, /* Version */
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REG_EMAC_PHY_CLK = 0x30, /* EMAC PHY Clock */
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};
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+
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#define REG_INDEX(offset) (offset / sizeof(uint32_t))
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+
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/* System Control register reset values */
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enum {
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REG_VER_RST = 0x0,
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REG_EMAC_PHY_CLK_RST = 0x58000,
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};
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+
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static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
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const uint32_t idx = REG_INDEX(offset);
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+
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if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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+
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return s->regs[idx];
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}
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+
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static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwH3SysCtrlState *s = AW_H3_SYSCTRL(opaque);
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const uint32_t idx = REG_INDEX(offset);
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+
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if (idx >= AW_H3_SYSCTRL_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return;
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}
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+
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switch (offset) {
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case REG_VER: /* Version */
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break;
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default:
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s->regs[idx] = (uint32_t) val;
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break;
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}
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}
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+
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static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
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.read = allwinner_h3_sysctrl_read,
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.write = allwinner_h3_sysctrl_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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+
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static void allwinner_h3_sysctrl_reset(DeviceState *dev)
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{
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AwH3SysCtrlState *s = AW_H3_SYSCTRL(dev);
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+
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/* Set default values for registers */
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s->regs[REG_INDEX(REG_VER)] = REG_VER_RST;
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s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] = REG_EMAC_PHY_CLK_RST;
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}
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+
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static void allwinner_h3_sysctrl_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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AwH3SysCtrlState *s = AW_H3_SYSCTRL(obj);
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+
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/* Memory mapping */
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memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops, s,
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TYPE_AW_H3_SYSCTRL, 4 * KiB);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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+
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static const VMStateDescription allwinner_h3_sysctrl_vmstate = {
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.name = "allwinner-h3-sysctrl",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NUM),
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VMSTATE_END_OF_LIST()
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}
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};
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+
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static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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+
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dc->reset = allwinner_h3_sysctrl_reset;
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dc->vmsd = &allwinner_h3_sysctrl_vmstate;
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}
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+
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static const TypeInfo allwinner_h3_sysctrl_info = {
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.name = TYPE_AW_H3_SYSCTRL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = allwinner_h3_sysctrl_init,
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.instance_size = sizeof(AwH3SysCtrlState),
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.class_init = allwinner_h3_sysctrl_class_init,
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};
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static void allwinner_h3_sysctrl_register(void)
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{
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type_register_static(&allwinner_h3_sysctrl_info);
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}
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+
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type_init(allwinner_h3_sysctrl_register)
+3
include/hw/arm/allwinner-h3.h
+3
include/hw/arm/allwinner-h3.h
···
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40
#include "hw/timer/allwinner-a10-pit.h"
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#include "hw/intc/arm_gic.h"
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#include "hw/misc/allwinner-h3-ccu.h"
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#include "hw/misc/allwinner-h3-sysctrl.h"
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#include "target/arm/cpu.h"
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/**
···
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AW_H3_SRAM_A1,
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AW_H3_SRAM_A2,
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AW_H3_SRAM_C,
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AW_H3_SYSCTRL,
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AW_H3_EHCI0,
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AW_H3_OHCI0,
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AW_H3_EHCI1,
···
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const hwaddr *memmap;
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AwA10PITState timer;
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AwH3ClockCtlState ccu;
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AwH3SysCtrlState sysctrl;
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GICState gic;
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MemoryRegion sram_a1;
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MemoryRegion sram_a2;
+67
include/hw/misc/allwinner-h3-sysctrl.h
+67
include/hw/misc/allwinner-h3-sysctrl.h
···
1
+
/*
2
+
* Allwinner H3 System Control emulation
3
+
*
4
+
* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5
+
*
6
+
* This program is free software: you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License as published by
8
+
* the Free Software Foundation, either version 2 of the License, or
9
+
* (at your option) any later version.
10
+
*
11
+
* This program is distributed in the hope that it will be useful,
12
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
15
+
*
16
+
* You should have received a copy of the GNU General Public License
17
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
18
+
*/
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+
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#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
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#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
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+
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#include "qom/object.h"
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#include "hw/sysbus.h"
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+
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/**
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* @name Constants
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* @{
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*/
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+
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/** Highest register address used by System Control device */
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#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
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+
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/** Total number of known registers */
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#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
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sizeof(uint32_t)) + 1)
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+
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/** @} */
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+
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/**
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* @name Object model
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* @{
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*/
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+
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#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
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#define AW_H3_SYSCTRL(obj) \
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OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL)
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+
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/** @} */
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+
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/**
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* Allwinner H3 System Control object instance state
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*/
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typedef struct AwH3SysCtrlState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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+
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/** Maps I/O registers in physical memory */
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MemoryRegion iomem;
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+
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/** Array of hardware registers */
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uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
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+
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} AwH3SysCtrlState;
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+
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#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */