jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
gdbstub: Fix i386/x86_64 machine description and add control registers
The machine description we send is being (silently) thrown on the floor
by GDB and GDB silently uses the default machine description, because
the xml parse fails on <feature> nested within <feature>.
Changes to the xml in qemu source code have no effect.
In addition, the default machine description has fs_base, which fails to
be retrieved, which breaks the whole register window. Add it and the
other control registers.
Signed-off-by: Doug Gale <doug16k@gmail.com>
Message-Id: <20190124040457.2546-1-doug16k@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
authored by
Doug Gale
and committed by
Paolo Bonzini
7b0f97ba
1edead0f
+580
-265
+2
-2
configure
+2
-2
configure
···
7137
7137
case "$target_name" in
7138
7138
i386)
7139
7139
mttcg="yes"
7140
-
gdb_xml_files="i386-32bit.xml i386-32bit-core.xml i386-32bit-sse.xml"
7140
+
gdb_xml_files="i386-32bit.xml"
7141
7141
target_compiler=$cross_cc_i386
7142
7142
target_compiler_cflags=$cross_cc_ccflags_i386
7143
7143
;;
7144
7144
x86_64)
7145
7145
TARGET_BASE_ARCH=i386
7146
7146
mttcg="yes"
7147
-
gdb_xml_files="i386-64bit.xml i386-64bit-core.xml i386-64bit-sse.xml"
7147
+
gdb_xml_files="i386-64bit.xml"
7148
7148
target_compiler=$cross_cc_x86_64
7149
7149
;;
7150
7150
alpha)
-65
gdb-xml/i386-32bit-core.xml
-65
gdb-xml/i386-32bit-core.xml
···
1
-
<?xml version="1.0"?>
2
-
<!-- Copyright (C) 2010-2015 Free Software Foundation, Inc.
3
-
4
-
Copying and distribution of this file, with or without modification,
5
-
are permitted in any medium without royalty provided the copyright
6
-
notice and this notice are preserved. -->
7
-
8
-
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
9
-
<feature name="org.gnu.gdb.i386.core">
10
-
<flags id="i386_eflags" size="4">
11
-
<field name="CF" start="0" end="0"/>
12
-
<field name="" start="1" end="1"/>
13
-
<field name="PF" start="2" end="2"/>
14
-
<field name="AF" start="4" end="4"/>
15
-
<field name="ZF" start="6" end="6"/>
16
-
<field name="SF" start="7" end="7"/>
17
-
<field name="TF" start="8" end="8"/>
18
-
<field name="IF" start="9" end="9"/>
19
-
<field name="DF" start="10" end="10"/>
20
-
<field name="OF" start="11" end="11"/>
21
-
<field name="NT" start="14" end="14"/>
22
-
<field name="RF" start="16" end="16"/>
23
-
<field name="VM" start="17" end="17"/>
24
-
<field name="AC" start="18" end="18"/>
25
-
<field name="VIF" start="19" end="19"/>
26
-
<field name="VIP" start="20" end="20"/>
27
-
<field name="ID" start="21" end="21"/>
28
-
</flags>
29
-
30
-
<reg name="eax" bitsize="32" type="int32"/>
31
-
<reg name="ecx" bitsize="32" type="int32"/>
32
-
<reg name="edx" bitsize="32" type="int32"/>
33
-
<reg name="ebx" bitsize="32" type="int32"/>
34
-
<reg name="esp" bitsize="32" type="data_ptr"/>
35
-
<reg name="ebp" bitsize="32" type="data_ptr"/>
36
-
<reg name="esi" bitsize="32" type="int32"/>
37
-
<reg name="edi" bitsize="32" type="int32"/>
38
-
39
-
<reg name="eip" bitsize="32" type="code_ptr"/>
40
-
<reg name="eflags" bitsize="32" type="i386_eflags"/>
41
-
<reg name="cs" bitsize="32" type="int32"/>
42
-
<reg name="ss" bitsize="32" type="int32"/>
43
-
<reg name="ds" bitsize="32" type="int32"/>
44
-
<reg name="es" bitsize="32" type="int32"/>
45
-
<reg name="fs" bitsize="32" type="int32"/>
46
-
<reg name="gs" bitsize="32" type="int32"/>
47
-
48
-
<reg name="st0" bitsize="80" type="i387_ext"/>
49
-
<reg name="st1" bitsize="80" type="i387_ext"/>
50
-
<reg name="st2" bitsize="80" type="i387_ext"/>
51
-
<reg name="st3" bitsize="80" type="i387_ext"/>
52
-
<reg name="st4" bitsize="80" type="i387_ext"/>
53
-
<reg name="st5" bitsize="80" type="i387_ext"/>
54
-
<reg name="st6" bitsize="80" type="i387_ext"/>
55
-
<reg name="st7" bitsize="80" type="i387_ext"/>
56
-
57
-
<reg name="fctrl" bitsize="32" type="int" group="float"/>
58
-
<reg name="fstat" bitsize="32" type="int" group="float"/>
59
-
<reg name="ftag" bitsize="32" type="int" group="float"/>
60
-
<reg name="fiseg" bitsize="32" type="int" group="float"/>
61
-
<reg name="fioff" bitsize="32" type="int" group="float"/>
62
-
<reg name="foseg" bitsize="32" type="int" group="float"/>
63
-
<reg name="fooff" bitsize="32" type="int" group="float"/>
64
-
<reg name="fop" bitsize="32" type="int" group="float"/>
65
-
</feature>
-52
gdb-xml/i386-32bit-sse.xml
-52
gdb-xml/i386-32bit-sse.xml
···
1
-
<?xml version="1.0"?>
2
-
<!-- Copyright (C) 2010-2017 Free Software Foundation, Inc.
3
-
4
-
Copying and distribution of this file, with or without modification,
5
-
are permitted in any medium without royalty provided the copyright
6
-
notice and this notice are preserved. -->
7
-
8
-
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
9
-
<feature name="org.gnu.gdb.i386.32bit.sse">
10
-
<vector id="v4f" type="ieee_single" count="4"/>
11
-
<vector id="v2d" type="ieee_double" count="2"/>
12
-
<vector id="v16i8" type="int8" count="16"/>
13
-
<vector id="v8i16" type="int16" count="8"/>
14
-
<vector id="v4i32" type="int32" count="4"/>
15
-
<vector id="v2i64" type="int64" count="2"/>
16
-
<union id="vec128">
17
-
<field name="v4_float" type="v4f"/>
18
-
<field name="v2_double" type="v2d"/>
19
-
<field name="v16_int8" type="v16i8"/>
20
-
<field name="v8_int16" type="v8i16"/>
21
-
<field name="v4_int32" type="v4i32"/>
22
-
<field name="v2_int64" type="v2i64"/>
23
-
<field name="uint128" type="uint128"/>
24
-
</union>
25
-
<flags id="i386_mxcsr" size="4">
26
-
<field name="IE" start="0" end="0"/>
27
-
<field name="DE" start="1" end="1"/>
28
-
<field name="ZE" start="2" end="2"/>
29
-
<field name="OE" start="3" end="3"/>
30
-
<field name="UE" start="4" end="4"/>
31
-
<field name="PE" start="5" end="5"/>
32
-
<field name="DAZ" start="6" end="6"/>
33
-
<field name="IM" start="7" end="7"/>
34
-
<field name="DM" start="8" end="8"/>
35
-
<field name="ZM" start="9" end="9"/>
36
-
<field name="OM" start="10" end="10"/>
37
-
<field name="UM" start="11" end="11"/>
38
-
<field name="PM" start="12" end="12"/>
39
-
<field name="FZ" start="15" end="15"/>
40
-
</flags>
41
-
42
-
<reg name="xmm0" bitsize="128" type="vec128" regnum="32"/>
43
-
<reg name="xmm1" bitsize="128" type="vec128"/>
44
-
<reg name="xmm2" bitsize="128" type="vec128"/>
45
-
<reg name="xmm3" bitsize="128" type="vec128"/>
46
-
<reg name="xmm4" bitsize="128" type="vec128"/>
47
-
<reg name="xmm5" bitsize="128" type="vec128"/>
48
-
<reg name="xmm6" bitsize="128" type="vec128"/>
49
-
<reg name="xmm7" bitsize="128" type="vec128"/>
50
-
51
-
<reg name="mxcsr" bitsize="32" type="i386_mxcsr" group="vector"/>
52
-
</feature>
+181
-3
gdb-xml/i386-32bit.xml
+181
-3
gdb-xml/i386-32bit.xml
···
8
8
<!-- I386 with SSE -->
9
9
10
10
<!DOCTYPE target SYSTEM "gdb-target.dtd">
11
-
<feature name="org.gnu.gdb.i386.32bit">
12
-
<xi:include href="i386-32bit-core.xml"/>
13
-
<xi:include href="i386-32bit-sse.xml"/>
11
+
<feature name="org.gnu.gdb.i386.core">
12
+
<flags id="i386_eflags" size="4">
13
+
<field name="" start="22" end="31"/>
14
+
<field name="ID" start="21" end="21"/>
15
+
<field name="VIP" start="20" end="20"/>
16
+
<field name="VIF" start="19" end="19"/>
17
+
<field name="AC" start="18" end="18"/>
18
+
<field name="VM" start="17" end="17"/>
19
+
<field name="RF" start="16" end="16"/>
20
+
<field name="" start="15" end="15"/>
21
+
<field name="NT" start="14" end="14"/>
22
+
<field name="IOPL" start="12" end="13"/>
23
+
<field name="OF" start="11" end="11"/>
24
+
<field name="DF" start="10" end="10"/>
25
+
<field name="IF" start="9" end="9"/>
26
+
<field name="TF" start="8" end="8"/>
27
+
<field name="SF" start="7" end="7"/>
28
+
<field name="ZF" start="6" end="6"/>
29
+
<field name="" start="5" end="5"/>
30
+
<field name="AF" start="4" end="4"/>
31
+
<field name="" start="3" end="3"/>
32
+
<field name="PF" start="2" end="2"/>
33
+
<field name="" start="1" end="1"/>
34
+
<field name="CF" start="0" end="0"/>
35
+
</flags>
36
+
37
+
<reg name="eax" bitsize="32" type="int32" regnum="0"/>
38
+
<reg name="ecx" bitsize="32" type="int32"/>
39
+
<reg name="edx" bitsize="32" type="int32"/>
40
+
<reg name="ebx" bitsize="32" type="int32"/>
41
+
<reg name="esp" bitsize="32" type="data_ptr"/>
42
+
<reg name="ebp" bitsize="32" type="data_ptr"/>
43
+
<reg name="esi" bitsize="32" type="int32"/>
44
+
<reg name="edi" bitsize="32" type="int32"/>
45
+
46
+
<reg name="eip" bitsize="32" type="code_ptr"/>
47
+
<reg name="eflags" bitsize="32" type="i386_eflags"/>
48
+
49
+
<reg name="cs" bitsize="32" type="int32"/>
50
+
<reg name="ss" bitsize="32" type="int32"/>
51
+
<reg name="ds" bitsize="32" type="int32"/>
52
+
<reg name="es" bitsize="32" type="int32"/>
53
+
<reg name="fs" bitsize="32" type="int32"/>
54
+
<reg name="gs" bitsize="32" type="int32"/>
55
+
56
+
<!-- Segment descriptor caches and TLS base MSRs -->
57
+
58
+
<!--reg name="cs_base" bitsize="32" type="int32"/>
59
+
<reg name="ss_base" bitsize="32" type="int32"/>
60
+
<reg name="ds_base" bitsize="32" type="int32"/>
61
+
<reg name="es_base" bitsize="32" type="int32"/-->
62
+
<reg name="fs_base" bitsize="32" type="int32"/>
63
+
<reg name="gs_base" bitsize="32" type="int32"/>
64
+
<reg name="k_gs_base" bitsize="32" type="int32"/>
65
+
66
+
<flags id="i386_cr0" size="4">
67
+
<field name="PG" start="31" end="31"/>
68
+
<field name="CD" start="30" end="30"/>
69
+
<field name="NW" start="29" end="29"/>
70
+
<field name="AM" start="18" end="18"/>
71
+
<field name="WP" start="16" end="16"/>
72
+
<field name="NE" start="5" end="5"/>
73
+
<field name="ET" start="4" end="4"/>
74
+
<field name="TS" start="3" end="3"/>
75
+
<field name="EM" start="2" end="2"/>
76
+
<field name="MP" start="1" end="1"/>
77
+
<field name="PE" start="0" end="0"/>
78
+
</flags>
79
+
80
+
<flags id="i386_cr3" size="4">
81
+
<field name="PDBR" start="12" end="31"/>
82
+
<!--field name="" start="3" end="11"/>
83
+
<field name="WT" start="2" end="2"/>
84
+
<field name="CD" start="1" end="1"/>
85
+
<field name="" start="0" end="0"/-->
86
+
<field name="PCID" start="0" end="11"/>
87
+
</flags>
88
+
89
+
<flags id="i386_cr4" size="4">
90
+
<field name="VME" start="0" end="0"/>
91
+
<field name="PVI" start="1" end="1"/>
92
+
<field name="TSD" start="2" end="2"/>
93
+
<field name="DE" start="3" end="3"/>
94
+
<field name="PSE" start="4" end="4"/>
95
+
<field name="PAE" start="5" end="5"/>
96
+
<field name="MCE" start="6" end="6"/>
97
+
<field name="PGE" start="7" end="7"/>
98
+
<field name="PCE" start="8" end="8"/>
99
+
<field name="OSFXSR" start="9" end="9"/>
100
+
<field name="OSXMMEXCPT" start="10" end="10"/>
101
+
<field name="UMIP" start="11" end="11"/>
102
+
<field name="LA57" start="12" end="12"/>
103
+
<field name="VMXE" start="13" end="13"/>
104
+
<field name="SMXE" start="14" end="14"/>
105
+
<field name="FSGSBASE" start="16" end="16"/>
106
+
<field name="PCIDE" start="17" end="17"/>
107
+
<field name="OSXSAVE" start="18" end="18"/>
108
+
<field name="SMEP" start="20" end="20"/>
109
+
<field name="SMAP" start="21" end="21"/>
110
+
<field name="PKE" start="22" end="22"/>
111
+
</flags>
112
+
113
+
<flags id="i386_efer" size="8">
114
+
<field name="TCE" start="15" end="15"/>
115
+
<field name="FFXSR" start="14" end="14"/>
116
+
<field name="LMSLE" start="13" end="13"/>
117
+
<field name="SVME" start="12" end="12"/>
118
+
<field name="NXE" start="11" end="11"/>
119
+
<field name="LMA" start="10" end="10"/>
120
+
<field name="LME" start="8" end="8"/>
121
+
<field name="SCE" start="0" end="0"/>
122
+
</flags>
123
+
124
+
<reg name="cr0" bitsize="32" type="i386_cr0"/>
125
+
<reg name="cr2" bitsize="32" type="int32"/>
126
+
<reg name="cr3" bitsize="32" type="i386_cr3"/>
127
+
<reg name="cr4" bitsize="32" type="i386_cr4"/>
128
+
<reg name="cr8" bitsize="32" type="int32"/>
129
+
<reg name="efer" bitsize="32" type="i386_efer"/>
130
+
131
+
<reg name="st0" bitsize="80" type="i387_ext"/>
132
+
<reg name="st1" bitsize="80" type="i387_ext"/>
133
+
<reg name="st2" bitsize="80" type="i387_ext"/>
134
+
<reg name="st3" bitsize="80" type="i387_ext"/>
135
+
<reg name="st4" bitsize="80" type="i387_ext"/>
136
+
<reg name="st5" bitsize="80" type="i387_ext"/>
137
+
<reg name="st6" bitsize="80" type="i387_ext"/>
138
+
<reg name="st7" bitsize="80" type="i387_ext"/>
139
+
140
+
<reg name="fctrl" bitsize="32" type="int" group="float"/>
141
+
<reg name="fstat" bitsize="32" type="int" group="float"/>
142
+
<reg name="ftag" bitsize="32" type="int" group="float"/>
143
+
<reg name="fiseg" bitsize="32" type="int" group="float"/>
144
+
<reg name="fioff" bitsize="32" type="int" group="float"/>
145
+
<reg name="foseg" bitsize="32" type="int" group="float"/>
146
+
<reg name="fooff" bitsize="32" type="int" group="float"/>
147
+
<reg name="fop" bitsize="32" type="int" group="float"/>
148
+
<!--/feature>
149
+
<feature name="org.gnu.gdb.i386.32bit.sse"-->
150
+
<vector id="v4f" type="ieee_single" count="4"/>
151
+
<vector id="v2d" type="ieee_double" count="2"/>
152
+
<vector id="v16i8" type="int8" count="16"/>
153
+
<vector id="v8i16" type="int16" count="8"/>
154
+
<vector id="v4i32" type="int32" count="4"/>
155
+
<vector id="v2i64" type="int64" count="2"/>
156
+
<union id="vec128">
157
+
<field name="v4_float" type="v4f"/>
158
+
<field name="v2_double" type="v2d"/>
159
+
<field name="v16_int8" type="v16i8"/>
160
+
<field name="v8_int16" type="v8i16"/>
161
+
<field name="v4_int32" type="v4i32"/>
162
+
<field name="v2_int64" type="v2i64"/>
163
+
<field name="uint128" type="uint128"/>
164
+
</union>
165
+
<flags id="i386_mxcsr" size="4">
166
+
<field name="IE" start="0" end="0"/>
167
+
<field name="DE" start="1" end="1"/>
168
+
<field name="ZE" start="2" end="2"/>
169
+
<field name="OE" start="3" end="3"/>
170
+
<field name="UE" start="4" end="4"/>
171
+
<field name="PE" start="5" end="5"/>
172
+
<field name="DAZ" start="6" end="6"/>
173
+
<field name="IM" start="7" end="7"/>
174
+
<field name="DM" start="8" end="8"/>
175
+
<field name="ZM" start="9" end="9"/>
176
+
<field name="OM" start="10" end="10"/>
177
+
<field name="UM" start="11" end="11"/>
178
+
<field name="PM" start="12" end="12"/>
179
+
<field name="FZ" start="15" end="15"/>
180
+
</flags>
181
+
182
+
<reg name="xmm0" bitsize="128" type="vec128"/>
183
+
<reg name="xmm1" bitsize="128" type="vec128"/>
184
+
<reg name="xmm2" bitsize="128" type="vec128"/>
185
+
<reg name="xmm3" bitsize="128" type="vec128"/>
186
+
<reg name="xmm4" bitsize="128" type="vec128"/>
187
+
<reg name="xmm5" bitsize="128" type="vec128"/>
188
+
<reg name="xmm6" bitsize="128" type="vec128"/>
189
+
<reg name="xmm7" bitsize="128" type="vec128"/>
190
+
191
+
<reg name="mxcsr" bitsize="32" type="i386_mxcsr" group="vector"/>
14
192
</feature>
-73
gdb-xml/i386-64bit-core.xml
-73
gdb-xml/i386-64bit-core.xml
···
1
-
<?xml version="1.0"?>
2
-
<!-- Copyright (C) 2010-2015 Free Software Foundation, Inc.
3
-
4
-
Copying and distribution of this file, with or without modification,
5
-
are permitted in any medium without royalty provided the copyright
6
-
notice and this notice are preserved. -->
7
-
8
-
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
9
-
<feature name="org.gnu.gdb.i386.core">
10
-
<flags id="i386_eflags" size="4">
11
-
<field name="CF" start="0" end="0"/>
12
-
<field name="" start="1" end="1"/>
13
-
<field name="PF" start="2" end="2"/>
14
-
<field name="AF" start="4" end="4"/>
15
-
<field name="ZF" start="6" end="6"/>
16
-
<field name="SF" start="7" end="7"/>
17
-
<field name="TF" start="8" end="8"/>
18
-
<field name="IF" start="9" end="9"/>
19
-
<field name="DF" start="10" end="10"/>
20
-
<field name="OF" start="11" end="11"/>
21
-
<field name="NT" start="14" end="14"/>
22
-
<field name="RF" start="16" end="16"/>
23
-
<field name="VM" start="17" end="17"/>
24
-
<field name="AC" start="18" end="18"/>
25
-
<field name="VIF" start="19" end="19"/>
26
-
<field name="VIP" start="20" end="20"/>
27
-
<field name="ID" start="21" end="21"/>
28
-
</flags>
29
-
30
-
<reg name="rax" bitsize="64" type="int64"/>
31
-
<reg name="rbx" bitsize="64" type="int64"/>
32
-
<reg name="rcx" bitsize="64" type="int64"/>
33
-
<reg name="rdx" bitsize="64" type="int64"/>
34
-
<reg name="rsi" bitsize="64" type="int64"/>
35
-
<reg name="rdi" bitsize="64" type="int64"/>
36
-
<reg name="rbp" bitsize="64" type="data_ptr"/>
37
-
<reg name="rsp" bitsize="64" type="data_ptr"/>
38
-
<reg name="r8" bitsize="64" type="int64"/>
39
-
<reg name="r9" bitsize="64" type="int64"/>
40
-
<reg name="r10" bitsize="64" type="int64"/>
41
-
<reg name="r11" bitsize="64" type="int64"/>
42
-
<reg name="r12" bitsize="64" type="int64"/>
43
-
<reg name="r13" bitsize="64" type="int64"/>
44
-
<reg name="r14" bitsize="64" type="int64"/>
45
-
<reg name="r15" bitsize="64" type="int64"/>
46
-
47
-
<reg name="rip" bitsize="64" type="code_ptr"/>
48
-
<reg name="eflags" bitsize="32" type="i386_eflags"/>
49
-
<reg name="cs" bitsize="32" type="int32"/>
50
-
<reg name="ss" bitsize="32" type="int32"/>
51
-
<reg name="ds" bitsize="32" type="int32"/>
52
-
<reg name="es" bitsize="32" type="int32"/>
53
-
<reg name="fs" bitsize="32" type="int32"/>
54
-
<reg name="gs" bitsize="32" type="int32"/>
55
-
56
-
<reg name="st0" bitsize="80" type="i387_ext"/>
57
-
<reg name="st1" bitsize="80" type="i387_ext"/>
58
-
<reg name="st2" bitsize="80" type="i387_ext"/>
59
-
<reg name="st3" bitsize="80" type="i387_ext"/>
60
-
<reg name="st4" bitsize="80" type="i387_ext"/>
61
-
<reg name="st5" bitsize="80" type="i387_ext"/>
62
-
<reg name="st6" bitsize="80" type="i387_ext"/>
63
-
<reg name="st7" bitsize="80" type="i387_ext"/>
64
-
65
-
<reg name="fctrl" bitsize="32" type="int" group="float"/>
66
-
<reg name="fstat" bitsize="32" type="int" group="float"/>
67
-
<reg name="ftag" bitsize="32" type="int" group="float"/>
68
-
<reg name="fiseg" bitsize="32" type="int" group="float"/>
69
-
<reg name="fioff" bitsize="32" type="int" group="float"/>
70
-
<reg name="foseg" bitsize="32" type="int" group="float"/>
71
-
<reg name="fooff" bitsize="32" type="int" group="float"/>
72
-
<reg name="fop" bitsize="32" type="int" group="float"/>
73
-
</feature>
-60
gdb-xml/i386-64bit-sse.xml
-60
gdb-xml/i386-64bit-sse.xml
···
1
-
<?xml version="1.0"?>
2
-
<!-- Copyright (C) 2010-2017 Free Software Foundation, Inc.
3
-
4
-
Copying and distribution of this file, with or without modification,
5
-
are permitted in any medium without royalty provided the copyright
6
-
notice and this notice are preserved. -->
7
-
8
-
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
9
-
<feature name="org.gnu.gdb.i386.64bit.sse">
10
-
<vector id="v4f" type="ieee_single" count="4"/>
11
-
<vector id="v2d" type="ieee_double" count="2"/>
12
-
<vector id="v16i8" type="int8" count="16"/>
13
-
<vector id="v8i16" type="int16" count="8"/>
14
-
<vector id="v4i32" type="int32" count="4"/>
15
-
<vector id="v2i64" type="int64" count="2"/>
16
-
<union id="vec128">
17
-
<field name="v4_float" type="v4f"/>
18
-
<field name="v2_double" type="v2d"/>
19
-
<field name="v16_int8" type="v16i8"/>
20
-
<field name="v8_int16" type="v8i16"/>
21
-
<field name="v4_int32" type="v4i32"/>
22
-
<field name="v2_int64" type="v2i64"/>
23
-
<field name="uint128" type="uint128"/>
24
-
</union>
25
-
<flags id="i386_mxcsr" size="4">
26
-
<field name="IE" start="0" end="0"/>
27
-
<field name="DE" start="1" end="1"/>
28
-
<field name="ZE" start="2" end="2"/>
29
-
<field name="OE" start="3" end="3"/>
30
-
<field name="UE" start="4" end="4"/>
31
-
<field name="PE" start="5" end="5"/>
32
-
<field name="DAZ" start="6" end="6"/>
33
-
<field name="IM" start="7" end="7"/>
34
-
<field name="DM" start="8" end="8"/>
35
-
<field name="ZM" start="9" end="9"/>
36
-
<field name="OM" start="10" end="10"/>
37
-
<field name="UM" start="11" end="11"/>
38
-
<field name="PM" start="12" end="12"/>
39
-
<field name="FZ" start="15" end="15"/>
40
-
</flags>
41
-
42
-
<reg name="xmm0" bitsize="128" type="vec128" regnum="40"/>
43
-
<reg name="xmm1" bitsize="128" type="vec128"/>
44
-
<reg name="xmm2" bitsize="128" type="vec128"/>
45
-
<reg name="xmm3" bitsize="128" type="vec128"/>
46
-
<reg name="xmm4" bitsize="128" type="vec128"/>
47
-
<reg name="xmm5" bitsize="128" type="vec128"/>
48
-
<reg name="xmm6" bitsize="128" type="vec128"/>
49
-
<reg name="xmm7" bitsize="128" type="vec128"/>
50
-
<reg name="xmm8" bitsize="128" type="vec128"/>
51
-
<reg name="xmm9" bitsize="128" type="vec128"/>
52
-
<reg name="xmm10" bitsize="128" type="vec128"/>
53
-
<reg name="xmm11" bitsize="128" type="vec128"/>
54
-
<reg name="xmm12" bitsize="128" type="vec128"/>
55
-
<reg name="xmm13" bitsize="128" type="vec128"/>
56
-
<reg name="xmm14" bitsize="128" type="vec128"/>
57
-
<reg name="xmm15" bitsize="128" type="vec128"/>
58
-
59
-
<reg name="mxcsr" bitsize="32" type="i386_mxcsr" group="vector"/>
60
-
</feature>
+206
-4
gdb-xml/i386-64bit.xml
+206
-4
gdb-xml/i386-64bit.xml
···
5
5
are permitted in any medium without royalty provided the copyright
6
6
notice and this notice are preserved. -->
7
7
8
-
<!-- I386 64bit -->
8
+
<!-- x86_64 64bit -->
9
9
10
10
<!DOCTYPE target SYSTEM "gdb-target.dtd">
11
-
<feature name="org.gnu.gdb.i386.64bit">
12
-
<xi:include href="i386-64bit-core.xml"/>
13
-
<xi:include href="i386-64bit-sse.xml"/>
11
+
12
+
<feature name="org.gnu.gdb.i386.core">
13
+
<flags id="x64_eflags" size="4">
14
+
<field name="" start="22" end="31"/>
15
+
<field name="ID" start="21" end="21"/>
16
+
<field name="VIP" start="20" end="20"/>
17
+
<field name="VIF" start="19" end="19"/>
18
+
<field name="AC" start="18" end="18"/>
19
+
<field name="VM" start="17" end="17"/>
20
+
<field name="RF" start="16" end="16"/>
21
+
<field name="" start="15" end="15"/>
22
+
<field name="NT" start="14" end="14"/>
23
+
<field name="IOPL" start="12" end="13"/>
24
+
<field name="OF" start="11" end="11"/>
25
+
<field name="DF" start="10" end="10"/>
26
+
<field name="IF" start="9" end="9"/>
27
+
<field name="TF" start="8" end="8"/>
28
+
<field name="SF" start="7" end="7"/>
29
+
<field name="ZF" start="6" end="6"/>
30
+
<field name="" start="5" end="5"/>
31
+
<field name="AF" start="4" end="4"/>
32
+
<field name="" start="3" end="3"/>
33
+
<field name="PF" start="2" end="2"/>
34
+
<field name="" start="1" end="1"/>
35
+
<field name="CF" start="0" end="0"/>
36
+
</flags>
37
+
38
+
<!-- General registers -->
39
+
40
+
<reg name="rax" bitsize="64" type="int64" regnum="0"/>
41
+
<reg name="rbx" bitsize="64" type="int64"/>
42
+
<reg name="rcx" bitsize="64" type="int64"/>
43
+
<reg name="rdx" bitsize="64" type="int64"/>
44
+
<reg name="rsi" bitsize="64" type="int64"/>
45
+
<reg name="rdi" bitsize="64" type="int64"/>
46
+
<reg name="rbp" bitsize="64" type="data_ptr"/>
47
+
<reg name="rsp" bitsize="64" type="data_ptr"/>
48
+
<reg name="r8" bitsize="64" type="int64"/>
49
+
<reg name="r9" bitsize="64" type="int64"/>
50
+
<reg name="r10" bitsize="64" type="int64"/>
51
+
<reg name="r11" bitsize="64" type="int64"/>
52
+
<reg name="r12" bitsize="64" type="int64"/>
53
+
<reg name="r13" bitsize="64" type="int64"/>
54
+
<reg name="r14" bitsize="64" type="int64"/>
55
+
<reg name="r15" bitsize="64" type="int64"/>
56
+
57
+
<reg name="rip" bitsize="64" type="code_ptr"/>
58
+
<reg name="eflags" bitsize="32" type="x64_eflags"/>
59
+
60
+
<!-- Segment registers -->
61
+
62
+
<reg name="cs" bitsize="32" type="int32"/>
63
+
<reg name="ss" bitsize="32" type="int32"/>
64
+
<reg name="ds" bitsize="32" type="int32"/>
65
+
<reg name="es" bitsize="32" type="int32"/>
66
+
<reg name="fs" bitsize="32" type="int32"/>
67
+
<reg name="gs" bitsize="32" type="int32"/>
68
+
69
+
<!-- Segment descriptor caches and TLS base MSRs -->
70
+
71
+
<!--reg name="cs_base" bitsize="64" type="int64"/>
72
+
<reg name="ss_base" bitsize="64" type="int64"/>
73
+
<reg name="ds_base" bitsize="64" type="int64"/>
74
+
<reg name="es_base" bitsize="64" type="int64"/-->
75
+
<reg name="fs_base" bitsize="64" type="int64"/>
76
+
<reg name="gs_base" bitsize="64" type="int64"/>
77
+
<reg name="k_gs_base" bitsize="64" type="int64"/>
78
+
79
+
<!-- Control registers -->
80
+
81
+
<flags id="x64_cr0" size="8">
82
+
<field name="PG" start="31" end="31"/>
83
+
<field name="CD" start="30" end="30"/>
84
+
<field name="NW" start="29" end="29"/>
85
+
<field name="AM" start="18" end="18"/>
86
+
<field name="WP" start="16" end="16"/>
87
+
<field name="NE" start="5" end="5"/>
88
+
<field name="ET" start="4" end="4"/>
89
+
<field name="TS" start="3" end="3"/>
90
+
<field name="EM" start="2" end="2"/>
91
+
<field name="MP" start="1" end="1"/>
92
+
<field name="PE" start="0" end="0"/>
93
+
</flags>
94
+
95
+
<flags id="x64_cr3" size="8">
96
+
<field name="PDBR" start="12" end="63"/>
97
+
<!--field name="" start="3" end="11"/>
98
+
<field name="WT" start="2" end="2"/>
99
+
<field name="CD" start="1" end="1"/>
100
+
<field name="" start="0" end="0"/-->
101
+
<field name="PCID" start="0" end="11"/>
102
+
</flags>
103
+
104
+
<flags id="x64_cr4" size="8">
105
+
<field name="PKE" start="22" end="22"/>
106
+
<field name="SMAP" start="21" end="21"/>
107
+
<field name="SMEP" start="20" end="20"/>
108
+
<field name="OSXSAVE" start="18" end="18"/>
109
+
<field name="PCIDE" start="17" end="17"/>
110
+
<field name="FSGSBASE" start="16" end="16"/>
111
+
<field name="SMXE" start="14" end="14"/>
112
+
<field name="VMXE" start="13" end="13"/>
113
+
<field name="LA57" start="12" end="12"/>
114
+
<field name="UMIP" start="11" end="11"/>
115
+
<field name="OSXMMEXCPT" start="10" end="10"/>
116
+
<field name="OSFXSR" start="9" end="9"/>
117
+
<field name="PCE" start="8" end="8"/>
118
+
<field name="PGE" start="7" end="7"/>
119
+
<field name="MCE" start="6" end="6"/>
120
+
<field name="PAE" start="5" end="5"/>
121
+
<field name="PSE" start="4" end="4"/>
122
+
<field name="DE" start="3" end="3"/>
123
+
<field name="TSD" start="2" end="2"/>
124
+
<field name="PVI" start="1" end="1"/>
125
+
<field name="VME" start="0" end="0"/>
126
+
</flags>
127
+
128
+
<flags id="x64_efer" size="8">
129
+
<field name="TCE" start="15" end="15"/>
130
+
<field name="FFXSR" start="14" end="14"/>
131
+
<field name="LMSLE" start="13" end="13"/>
132
+
<field name="SVME" start="12" end="12"/>
133
+
<field name="NXE" start="11" end="11"/>
134
+
<field name="LMA" start="10" end="10"/>
135
+
<field name="LME" start="8" end="8"/>
136
+
<field name="SCE" start="0" end="0"/>
137
+
</flags>
138
+
139
+
<reg name="cr0" bitsize="64" type="x64_cr0"/>
140
+
<reg name="cr2" bitsize="64" type="int64"/>
141
+
<reg name="cr3" bitsize="64" type="x64_cr3"/>
142
+
<reg name="cr4" bitsize="64" type="x64_cr4"/>
143
+
<reg name="cr8" bitsize="64" type="int64"/>
144
+
<reg name="efer" bitsize="64" type="x64_efer"/>
145
+
146
+
<!-- x87 FPU -->
147
+
148
+
<reg name="st0" bitsize="80" type="i387_ext"/>
149
+
<reg name="st1" bitsize="80" type="i387_ext"/>
150
+
<reg name="st2" bitsize="80" type="i387_ext"/>
151
+
<reg name="st3" bitsize="80" type="i387_ext"/>
152
+
<reg name="st4" bitsize="80" type="i387_ext"/>
153
+
<reg name="st5" bitsize="80" type="i387_ext"/>
154
+
<reg name="st6" bitsize="80" type="i387_ext"/>
155
+
<reg name="st7" bitsize="80" type="i387_ext"/>
156
+
157
+
<reg name="fctrl" bitsize="32" type="int" group="float"/>
158
+
<reg name="fstat" bitsize="32" type="int" group="float"/>
159
+
<reg name="ftag" bitsize="32" type="int" group="float"/>
160
+
<reg name="fiseg" bitsize="32" type="int" group="float"/>
161
+
<reg name="fioff" bitsize="32" type="int" group="float"/>
162
+
<reg name="foseg" bitsize="32" type="int" group="float"/>
163
+
<reg name="fooff" bitsize="32" type="int" group="float"/>
164
+
<reg name="fop" bitsize="32" type="int" group="float"/>
165
+
166
+
<vector id="v4f" type="ieee_single" count="4"/>
167
+
<vector id="v2d" type="ieee_double" count="2"/>
168
+
<vector id="v16i8" type="int8" count="16"/>
169
+
<vector id="v8i16" type="int16" count="8"/>
170
+
<vector id="v4i32" type="int32" count="4"/>
171
+
<vector id="v2i64" type="int64" count="2"/>
172
+
<union id="vec128">
173
+
<field name="v4_float" type="v4f"/>
174
+
<field name="v2_double" type="v2d"/>
175
+
<field name="v16_int8" type="v16i8"/>
176
+
<field name="v8_int16" type="v8i16"/>
177
+
<field name="v4_int32" type="v4i32"/>
178
+
<field name="v2_int64" type="v2i64"/>
179
+
<field name="uint128" type="uint128"/>
180
+
</union>
181
+
<flags id="x64_mxcsr" size="4">
182
+
<field name="IE" start="0" end="0"/>
183
+
<field name="DE" start="1" end="1"/>
184
+
<field name="ZE" start="2" end="2"/>
185
+
<field name="OE" start="3" end="3"/>
186
+
<field name="UE" start="4" end="4"/>
187
+
<field name="PE" start="5" end="5"/>
188
+
<field name="DAZ" start="6" end="6"/>
189
+
<field name="IM" start="7" end="7"/>
190
+
<field name="DM" start="8" end="8"/>
191
+
<field name="ZM" start="9" end="9"/>
192
+
<field name="OM" start="10" end="10"/>
193
+
<field name="UM" start="11" end="11"/>
194
+
<field name="PM" start="12" end="12"/>
195
+
<field name="FZ" start="15" end="15"/>
196
+
</flags>
197
+
198
+
<reg name="xmm0" bitsize="128" type="vec128"/>
199
+
<reg name="xmm1" bitsize="128" type="vec128"/>
200
+
<reg name="xmm2" bitsize="128" type="vec128"/>
201
+
<reg name="xmm3" bitsize="128" type="vec128"/>
202
+
<reg name="xmm4" bitsize="128" type="vec128"/>
203
+
<reg name="xmm5" bitsize="128" type="vec128"/>
204
+
<reg name="xmm6" bitsize="128" type="vec128"/>
205
+
<reg name="xmm7" bitsize="128" type="vec128"/>
206
+
<reg name="xmm8" bitsize="128" type="vec128"/>
207
+
<reg name="xmm9" bitsize="128" type="vec128"/>
208
+
<reg name="xmm10" bitsize="128" type="vec128"/>
209
+
<reg name="xmm11" bitsize="128" type="vec128"/>
210
+
<reg name="xmm12" bitsize="128" type="vec128"/>
211
+
<reg name="xmm13" bitsize="128" type="vec128"/>
212
+
<reg name="xmm14" bitsize="128" type="vec128"/>
213
+
<reg name="xmm15" bitsize="128" type="vec128"/>
214
+
215
+
<reg name="mxcsr" bitsize="32" type="x64_mxcsr" group="vector"/>
14
216
</feature>
+2
-2
target/i386/cpu.c
+2
-2
target/i386/cpu.c
···
5870
5870
cc->gdb_arch_name = x86_gdb_arch_name;
5871
5871
#ifdef TARGET_X86_64
5872
5872
cc->gdb_core_xml_file = "i386-64bit.xml";
5873
-
cc->gdb_num_core_regs = 57;
5873
+
cc->gdb_num_core_regs = 66;
5874
5874
#else
5875
5875
cc->gdb_core_xml_file = "i386-32bit.xml";
5876
-
cc->gdb_num_core_regs = 41;
5876
+
cc->gdb_num_core_regs = 50;
5877
5877
#endif
5878
5878
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
5879
5879
cc->debug_excp_handler = breakpoint_handler;
+189
-4
target/i386/gdbstub.c
+189
-4
target/i386/gdbstub.c
···
32
32
#endif
33
33
static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
34
34
35
+
/*
36
+
* Keep these in sync with assignment to
37
+
* gdb_num_core_regs in target/i386/cpu.c
38
+
* and with the machine description
39
+
*/
40
+
41
+
/*
42
+
* SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base
43
+
*/
44
+
45
+
/*
46
+
* general regs -----> 8 or 16
47
+
*/
48
+
#define IDX_NB_IP 1
49
+
#define IDX_NB_FLAGS 1
50
+
#define IDX_NB_SEG (6 + 3)
51
+
#define IDX_NB_CTL 6
52
+
#define IDX_NB_FP 16
53
+
/*
54
+
* fpu regs ----------> 8 or 16
55
+
*/
56
+
#define IDX_NB_MXCSR 1
57
+
/*
58
+
* total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66
59
+
*/
60
+
35
61
#define IDX_IP_REG CPU_NB_REGS
36
-
#define IDX_FLAGS_REG (IDX_IP_REG + 1)
37
-
#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
38
-
#define IDX_FP_REGS (IDX_SEG_REGS + 6)
39
-
#define IDX_XMM_REGS (IDX_FP_REGS + 16)
62
+
#define IDX_FLAGS_REG (IDX_IP_REG + IDX_NB_IP)
63
+
#define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS)
64
+
#define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG)
65
+
#define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL)
66
+
#define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP)
40
67
#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
68
+
69
+
#define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0)
70
+
#define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1)
71
+
#define IDX_CTL_CR3_REG (IDX_CTL_REGS + 2)
72
+
#define IDX_CTL_CR4_REG (IDX_CTL_REGS + 3)
73
+
#define IDX_CTL_CR8_REG (IDX_CTL_REGS + 4)
74
+
#define IDX_CTL_EFER_REG (IDX_CTL_REGS + 5)
75
+
76
+
#ifdef TARGET_X86_64
77
+
#define GDB_FORCE_64 1
78
+
#else
79
+
#define GDB_FORCE_64 0
80
+
#endif
81
+
41
82
42
83
int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
43
84
{
44
85
X86CPU *cpu = X86_CPU(cs);
45
86
CPUX86State *env = &cpu->env;
46
87
88
+
uint64_t tpr;
89
+
47
90
/* N.B. GDB can't deal with changes in registers or sizes in the middle
48
91
of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
49
92
as if we're on a 64-bit cpu. */
···
104
147
return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
105
148
case IDX_SEG_REGS + 5:
106
149
return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
150
+
151
+
case IDX_SEG_REGS + 6:
152
+
if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
153
+
return gdb_get_reg64(mem_buf, env->segs[R_FS].base);
154
+
}
155
+
return gdb_get_reg32(mem_buf, env->segs[R_FS].base);
156
+
157
+
case IDX_SEG_REGS + 7:
158
+
if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
159
+
return gdb_get_reg64(mem_buf, env->segs[R_GS].base);
160
+
}
161
+
return gdb_get_reg32(mem_buf, env->segs[R_GS].base);
162
+
163
+
case IDX_SEG_REGS + 8:
164
+
#ifdef TARGET_X86_64
165
+
if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
166
+
return gdb_get_reg64(mem_buf, env->kernelgsbase);
167
+
}
168
+
return gdb_get_reg32(mem_buf, env->kernelgsbase);
169
+
#else
170
+
return gdb_get_reg32(mem_buf, 0);
171
+
#endif
107
172
108
173
case IDX_FP_REGS + 8:
109
174
return gdb_get_reg32(mem_buf, env->fpuc);
···
125
190
126
191
case IDX_MXCSR_REG:
127
192
return gdb_get_reg32(mem_buf, env->mxcsr);
193
+
194
+
case IDX_CTL_CR0_REG:
195
+
if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
196
+
return gdb_get_reg64(mem_buf, env->cr[0]);
197
+
}
198
+
return gdb_get_reg32(mem_buf, env->cr[0]);
199
+
200
+
case IDX_CTL_CR2_REG:
201
+
if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
202
+
return gdb_get_reg64(mem_buf, env->cr[2]);
203
+
}
204
+
return gdb_get_reg32(mem_buf, env->cr[2]);
205
+
206
+
case IDX_CTL_CR3_REG:
207
+
if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
208
+
return gdb_get_reg64(mem_buf, env->cr[3]);
209
+
}
210
+
return gdb_get_reg32(mem_buf, env->cr[3]);
211
+
212
+
case IDX_CTL_CR4_REG:
213
+
if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
214
+
return gdb_get_reg64(mem_buf, env->cr[4]);
215
+
}
216
+
return gdb_get_reg32(mem_buf, env->cr[4]);
217
+
218
+
case IDX_CTL_CR8_REG:
219
+
#ifdef CONFIG_SOFTMMU
220
+
tpr = cpu_get_apic_tpr(cpu->apic_state);
221
+
#else
222
+
tpr = 0;
223
+
#endif
224
+
if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
225
+
return gdb_get_reg64(mem_buf, tpr);
226
+
}
227
+
return gdb_get_reg32(mem_buf, tpr);
228
+
229
+
case IDX_CTL_EFER_REG:
230
+
if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
231
+
return gdb_get_reg64(mem_buf, env->efer);
232
+
}
233
+
return gdb_get_reg32(mem_buf, env->efer);
128
234
}
129
235
}
130
236
return 0;
···
229
335
case IDX_SEG_REGS + 5:
230
336
return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
231
337
338
+
case IDX_SEG_REGS + 6:
339
+
if (env->hflags & HF_CS64_MASK) {
340
+
env->segs[R_FS].base = ldq_p(mem_buf);
341
+
return 8;
342
+
}
343
+
env->segs[R_FS].base = ldl_p(mem_buf);
344
+
return 4;
345
+
346
+
case IDX_SEG_REGS + 7:
347
+
if (env->hflags & HF_CS64_MASK) {
348
+
env->segs[R_GS].base = ldq_p(mem_buf);
349
+
return 8;
350
+
}
351
+
env->segs[R_GS].base = ldl_p(mem_buf);
352
+
return 4;
353
+
354
+
#ifdef TARGET_X86_64
355
+
case IDX_SEG_REGS + 8:
356
+
if (env->hflags & HF_CS64_MASK) {
357
+
env->kernelgsbase = ldq_p(mem_buf);
358
+
return 8;
359
+
}
360
+
env->kernelgsbase = ldl_p(mem_buf);
361
+
return 4;
362
+
#endif
363
+
232
364
case IDX_FP_REGS + 8:
233
365
cpu_set_fpuc(env, ldl_p(mem_buf));
234
366
return 4;
···
253
385
case IDX_MXCSR_REG:
254
386
cpu_set_mxcsr(env, ldl_p(mem_buf));
255
387
return 4;
388
+
389
+
case IDX_CTL_CR0_REG:
390
+
if (env->hflags & HF_CS64_MASK) {
391
+
cpu_x86_update_cr0(env, ldq_p(mem_buf));
392
+
return 8;
393
+
}
394
+
cpu_x86_update_cr0(env, ldl_p(mem_buf));
395
+
return 4;
396
+
397
+
case IDX_CTL_CR2_REG:
398
+
if (env->hflags & HF_CS64_MASK) {
399
+
env->cr[2] = ldq_p(mem_buf);
400
+
return 8;
401
+
}
402
+
env->cr[2] = ldl_p(mem_buf);
403
+
return 4;
404
+
405
+
case IDX_CTL_CR3_REG:
406
+
if (env->hflags & HF_CS64_MASK) {
407
+
cpu_x86_update_cr3(env, ldq_p(mem_buf));
408
+
return 8;
409
+
}
410
+
cpu_x86_update_cr3(env, ldl_p(mem_buf));
411
+
return 4;
412
+
413
+
case IDX_CTL_CR4_REG:
414
+
if (env->hflags & HF_CS64_MASK) {
415
+
cpu_x86_update_cr4(env, ldq_p(mem_buf));
416
+
return 8;
417
+
}
418
+
cpu_x86_update_cr4(env, ldl_p(mem_buf));
419
+
return 4;
420
+
421
+
case IDX_CTL_CR8_REG:
422
+
if (env->hflags & HF_CS64_MASK) {
423
+
#ifdef CONFIG_SOFTMMU
424
+
cpu_set_apic_tpr(cpu->apic_state, ldq_p(mem_buf));
425
+
#endif
426
+
return 8;
427
+
}
428
+
#ifdef CONFIG_SOFTMMU
429
+
cpu_set_apic_tpr(cpu->apic_state, ldl_p(mem_buf));
430
+
#endif
431
+
return 4;
432
+
433
+
case IDX_CTL_EFER_REG:
434
+
if (env->hflags & HF_CS64_MASK) {
435
+
cpu_load_efer(env, ldq_p(mem_buf));
436
+
return 8;
437
+
}
438
+
cpu_load_efer(env, ldl_p(mem_buf));
439
+
return 4;
440
+
256
441
}
257
442
}
258
443
/* Unrecognised register. */