jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/misc: Add support for ADC controller in Xilinx Zynq 7000
Add support for the Xilinx XADC core used in Zynq 7000.
References:
- Zynq-7000 All Programmable SoC Technical Reference Manual
- 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC
Dual 12-Bit 1 MSPS Analog-to-Digital Converter
Tested with Linux using QEMU machine xilinx-zynq-a9 with devicetree
files zynq-zc702.dtb and zynq-zc706.dtb, and kernel configuration
multi_v7_defconfig.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
[ PC changes:
* Changed macro names to match TRM where possible
* Made programmers model macro scheme consistent
* Dropped XADC_ZYNQ_ prefix on local macros
* Fix ALM field width
* Update threshold-comparison interrupts in _update_ints()
* factored out DFIFO pushes into helper. Renamed to "push/pop"
* Changed xadc_reg to 10 bits and added OOB check.
* Reduced scope of MCTL reset to just stop channel coms.
* Added dummy read data to write commands
* Changed _ to - seperators in string names and filenames
* Dropped ------------ in header comment
* Catchall'ed _update_ints() in _write handler.
* Minor whitespace changes.
* Use ZYNQ_XADC_FIFO_DEPTH instead of ARRAY_SIZE()
]
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Guenter Roeck
and committed by
Peter Maydell
74fcbd22
f3bcfc56
+355
+6
hw/arm/xilinx_zynq.c
+6
hw/arm/xilinx_zynq.c
···
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#include "hw/block/flash.h"
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#include "sysemu/block-backend.h"
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#include "hw/loader.h"
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#include "hw/misc/zynq-xadc.h"
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#include "hw/ssi.h"
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#include "qemu/error-report.h"
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···
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
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dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
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dev = qdev_create(NULL, "pl330");
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qdev_prop_set_uint8(dev, "num_chnls", 8);
+1
hw/misc/Makefile.objs
+1
hw/misc/Makefile.objs
+302
hw/misc/zynq-xadc.c
+302
hw/misc/zynq-xadc.c
···
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/*
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* ADC registers for Xilinx Zynq Platform
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*
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* Copyright (c) 2015 Guenter Roeck
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* Based on hw/misc/zynq_slcr.c, written by Michal Simek
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/hw.h"
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#include "hw/misc/zynq-xadc.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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+
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enum {
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CFG = 0x000 / 4,
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INT_STS,
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INT_MASK,
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MSTS,
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CMDFIFO,
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RDFIFO,
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MCTL,
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};
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#define CFG_ENABLE BIT(31)
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#define CFG_CFIFOTH_SHIFT 20
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#define CFG_CFIFOTH_LENGTH 4
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#define CFG_DFIFOTH_SHIFT 16
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#define CFG_DFIFOTH_LENGTH 4
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#define CFG_WEDGE BIT(13)
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#define CFG_REDGE BIT(12)
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#define CFG_TCKRATE_SHIFT 8
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#define CFG_TCKRATE_LENGTH 2
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#define CFG_TCKRATE_DIV(x) (0x1 << (x - 1))
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#define CFG_IGAP_SHIFT 0
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#define CFG_IGAP_LENGTH 5
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#define INT_CFIFO_LTH BIT(9)
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#define INT_DFIFO_GTH BIT(8)
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#define INT_OT BIT(7)
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#define INT_ALM_SHIFT 0
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#define INT_ALM_LENGTH 7
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#define INT_ALM_MASK (((1 << INT_ALM_LENGTH) - 1) << INT_ALM_SHIFT)
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#define INT_ALL (INT_CFIFO_LTH | INT_DFIFO_GTH | INT_OT | INT_ALM_MASK)
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#define MSTS_CFIFO_LVL_SHIFT 16
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#define MSTS_CFIFO_LVL_LENGTH 4
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#define MSTS_DFIFO_LVL_SHIFT 12
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#define MSTS_DFIFO_LVL_LENGTH 4
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#define MSTS_CFIFOF BIT(11)
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#define MSTS_CFIFOE BIT(10)
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#define MSTS_DFIFOF BIT(9)
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#define MSTS_DFIFOE BIT(8)
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#define MSTS_OT BIT(7)
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#define MSTS_ALM_SHIFT 0
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#define MSTS_ALM_LENGTH 7
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#define MCTL_RESET BIT(4)
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#define CMD_NOP 0x00
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#define CMD_READ 0x01
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#define CMD_WRITE 0x02
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static void zynq_xadc_update_ints(ZynqXADCState *s)
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{
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/* We are fast, commands are actioned instantly so the CFIFO is always
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* empty (and below threshold).
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*/
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s->regs[INT_STS] |= INT_CFIFO_LTH;
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if (s->xadc_dfifo_entries >
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extract32(s->regs[CFG], CFG_DFIFOTH_SHIFT, CFG_DFIFOTH_LENGTH)) {
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s->regs[INT_STS] |= INT_DFIFO_GTH;
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}
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qemu_set_irq(s->qemu_irq, !!(s->regs[INT_STS] & ~s->regs[INT_MASK]));
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}
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static void zynq_xadc_reset(DeviceState *d)
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{
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ZynqXADCState *s = ZYNQ_XADC(d);
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s->regs[CFG] = 0x14 << CFG_IGAP_SHIFT |
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CFG_TCKRATE_DIV(4) << CFG_TCKRATE_SHIFT | CFG_REDGE;
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s->regs[INT_STS] = INT_CFIFO_LTH;
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s->regs[INT_MASK] = 0xffffffff;
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s->regs[CMDFIFO] = 0;
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s->regs[RDFIFO] = 0;
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s->regs[MCTL] = MCTL_RESET;
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memset(s->xadc_regs, 0, sizeof(s->xadc_regs));
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memset(s->xadc_dfifo, 0, sizeof(s->xadc_dfifo));
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s->xadc_dfifo_entries = 0;
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zynq_xadc_update_ints(s);
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}
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static uint16_t xadc_pop_dfifo(ZynqXADCState *s)
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{
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uint16_t rv = s->xadc_dfifo[0];
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int i;
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if (s->xadc_dfifo_entries > 0) {
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s->xadc_dfifo_entries--;
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}
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for (i = 0; i < s->xadc_dfifo_entries; i++) {
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s->xadc_dfifo[i] = s->xadc_dfifo[i + 1];
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}
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s->xadc_dfifo[s->xadc_dfifo_entries] = 0;
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zynq_xadc_update_ints(s);
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return rv;
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}
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static void xadc_push_dfifo(ZynqXADCState *s, uint16_t regval)
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{
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if (s->xadc_dfifo_entries < ZYNQ_XADC_FIFO_DEPTH) {
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s->xadc_dfifo[s->xadc_dfifo_entries++] = s->xadc_read_reg_previous;
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}
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s->xadc_read_reg_previous = regval;
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zynq_xadc_update_ints(s);
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}
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static bool zynq_xadc_check_offset(hwaddr offset, bool rnw)
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{
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switch (offset) {
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case CFG:
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case INT_MASK:
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case INT_STS:
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case MCTL:
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return true;
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case RDFIFO:
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case MSTS:
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return rnw; /* read only */
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case CMDFIFO:
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return !rnw; /* write only */
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default:
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return false;
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}
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}
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static uint64_t zynq_xadc_read(void *opaque, hwaddr offset, unsigned size)
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{
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ZynqXADCState *s = opaque;
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int reg = offset / 4;
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uint32_t rv = 0;
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if (!zynq_xadc_check_offset(reg, true)) {
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qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid read access to "
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"addr %" HWADDR_PRIx "\n", offset);
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return 0;
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}
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switch (reg) {
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case CFG:
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case INT_MASK:
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case INT_STS:
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case MCTL:
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rv = s->regs[reg];
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break;
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case MSTS:
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rv = MSTS_CFIFOE;
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rv |= s->xadc_dfifo_entries << MSTS_DFIFO_LVL_SHIFT;
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if (!s->xadc_dfifo_entries) {
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rv |= MSTS_DFIFOE;
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} else if (s->xadc_dfifo_entries == ZYNQ_XADC_FIFO_DEPTH) {
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rv |= MSTS_DFIFOF;
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}
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break;
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case RDFIFO:
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rv = xadc_pop_dfifo(s);
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break;
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}
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return rv;
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}
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static void zynq_xadc_write(void *opaque, hwaddr offset, uint64_t val,
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unsigned size)
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{
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ZynqXADCState *s = (ZynqXADCState *)opaque;
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int reg = offset / 4;
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int xadc_reg;
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int xadc_cmd;
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int xadc_data;
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if (!zynq_xadc_check_offset(reg, false)) {
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qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid write access "
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"to addr %" HWADDR_PRIx "\n", offset);
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return;
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}
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switch (reg) {
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case CFG:
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s->regs[CFG] = val;
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break;
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case INT_STS:
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s->regs[INT_STS] &= ~val;
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break;
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case INT_MASK:
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s->regs[INT_MASK] = val & INT_ALL;
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break;
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case CMDFIFO:
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xadc_cmd = extract32(val, 26, 4);
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xadc_reg = extract32(val, 16, 10);
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xadc_data = extract32(val, 0, 16);
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if (s->regs[MCTL] & MCTL_RESET) {
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qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Sending command "
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"while comm channel held in reset: %" PRIx32 "\n",
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(uint32_t) val);
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break;
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}
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if (xadc_reg > ZYNQ_XADC_NUM_ADC_REGS && xadc_cmd != CMD_NOP) {
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qemu_log_mask(LOG_GUEST_ERROR, "read/write op to invalid xadc "
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"reg 0x%x\n", xadc_reg);
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break;
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}
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switch (xadc_cmd) {
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case CMD_READ:
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xadc_push_dfifo(s, s->xadc_regs[xadc_reg]);
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break;
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case CMD_WRITE:
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s->xadc_regs[xadc_reg] = xadc_data;
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/* fallthrough */
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case CMD_NOP:
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xadc_push_dfifo(s, 0);
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break;
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}
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break;
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case MCTL:
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s->regs[MCTL] = val & 0x00fffeff;
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break;
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}
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zynq_xadc_update_ints(s);
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}
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static const MemoryRegionOps xadc_ops = {
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.read = zynq_xadc_read,
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.write = zynq_xadc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void zynq_xadc_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ZynqXADCState *s = ZYNQ_XADC(obj);
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memory_region_init_io(&s->iomem, obj, &xadc_ops, s, "zynq-xadc",
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ZYNQ_XADC_MMIO_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->qemu_irq);
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}
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+
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static const VMStateDescription vmstate_zynq_xadc = {
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.name = "zynq-xadc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, ZynqXADCState, ZYNQ_XADC_NUM_IO_REGS),
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VMSTATE_UINT16_ARRAY(xadc_regs, ZynqXADCState,
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ZYNQ_XADC_NUM_ADC_REGS),
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VMSTATE_UINT16_ARRAY(xadc_dfifo, ZynqXADCState,
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ZYNQ_XADC_FIFO_DEPTH),
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VMSTATE_UINT16(xadc_read_reg_previous, ZynqXADCState),
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VMSTATE_UINT16(xadc_dfifo_entries, ZynqXADCState),
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VMSTATE_END_OF_LIST()
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}
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};
280
+
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static void zynq_xadc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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+
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dc->vmsd = &vmstate_zynq_xadc;
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dc->reset = zynq_xadc_reset;
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}
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+
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static const TypeInfo zynq_xadc_info = {
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.class_init = zynq_xadc_class_init,
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.name = TYPE_ZYNQ_XADC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ZynqXADCState),
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.instance_init = zynq_xadc_init,
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};
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+
297
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static void zynq_xadc_register_types(void)
298
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{
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type_register_static(&zynq_xadc_info);
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}
301
+
302
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type_init(zynq_xadc_register_types)
+46
include/hw/misc/zynq-xadc.h
+46
include/hw/misc/zynq-xadc.h
···
1
+
/*
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* Device model for Zynq ADC controller
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*
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* Copyright (c) 2015 Guenter Roeck <linux@roeck-us.net>
5
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*
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* This program is free software; you can redistribute it and/or
7
+
* modify it under the terms of the GNU General Public License
8
+
* as published by the Free Software Foundation; either version
9
+
* 2 of the License, or (at your option) any later version.
10
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*
11
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* You should have received a copy of the GNU General Public License along
12
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* with this program; if not, see <http://www.gnu.org/licenses/>.
13
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*/
14
+
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#ifndef ZYNQ_XADC_H
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#define ZYNQ_XADC_H
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+
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#include "hw/sysbus.h"
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+
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#define ZYNQ_XADC_MMIO_SIZE 0x0020
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#define ZYNQ_XADC_NUM_IO_REGS (ZYNQ_XADC_MMIO_SIZE / 4)
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#define ZYNQ_XADC_NUM_ADC_REGS 128
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#define ZYNQ_XADC_FIFO_DEPTH 15
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25
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#define TYPE_ZYNQ_XADC "xlnx,zynq-xadc"
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#define ZYNQ_XADC(obj) \
27
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OBJECT_CHECK(ZynqXADCState, (obj), TYPE_ZYNQ_XADC)
28
+
29
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typedef struct ZynqXADCState {
30
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/*< private >*/
31
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SysBusDevice parent_obj;
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+
33
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/*< public >*/
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MemoryRegion iomem;
35
+
36
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uint32_t regs[ZYNQ_XADC_NUM_IO_REGS];
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uint16_t xadc_regs[ZYNQ_XADC_NUM_ADC_REGS];
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uint16_t xadc_read_reg_previous;
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uint16_t xadc_dfifo[ZYNQ_XADC_FIFO_DEPTH];
40
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uint16_t xadc_dfifo_entries;
41
+
42
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struct IRQState *qemu_irq;
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+
44
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} ZynqXADCState;
45
+
46
+
#endif /* ZYNQ_XADC_H */