jcs.org / qemu
qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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target/arm: Implement FP data-processing (2 source) for fp16

We missed all of the scalar fp16 binary operations.

Cc: qemu-stable@nongnu.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit b8f5171cf01420a9f0ee895c5591e9b9914f391a)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>

authored by

Richard Henderson and committed by
Michael Roth 7133cd4c d1ed4a60

+65
+65
target/arm/translate-a64.c
··· 5056 5056 tcg_temp_free_i64(tcg_res); 5057 5057 } 5058 5058 5059 + /* Floating-point data-processing (2 source) - half precision */ 5060 + static void handle_fp_2src_half(DisasContext *s, int opcode, 5061 + int rd, int rn, int rm) 5062 + { 5063 + TCGv_i32 tcg_op1; 5064 + TCGv_i32 tcg_op2; 5065 + TCGv_i32 tcg_res; 5066 + TCGv_ptr fpst; 5067 + 5068 + tcg_res = tcg_temp_new_i32(); 5069 + fpst = get_fpstatus_ptr(true); 5070 + tcg_op1 = read_fp_hreg(s, rn); 5071 + tcg_op2 = read_fp_hreg(s, rm); 5072 + 5073 + switch (opcode) { 5074 + case 0x0: /* FMUL */ 5075 + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); 5076 + break; 5077 + case 0x1: /* FDIV */ 5078 + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); 5079 + break; 5080 + case 0x2: /* FADD */ 5081 + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); 5082 + break; 5083 + case 0x3: /* FSUB */ 5084 + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); 5085 + break; 5086 + case 0x4: /* FMAX */ 5087 + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); 5088 + break; 5089 + case 0x5: /* FMIN */ 5090 + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); 5091 + break; 5092 + case 0x6: /* FMAXNM */ 5093 + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); 5094 + break; 5095 + case 0x7: /* FMINNM */ 5096 + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); 5097 + break; 5098 + case 0x8: /* FNMUL */ 5099 + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); 5100 + tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); 5101 + break; 5102 + default: 5103 + g_assert_not_reached(); 5104 + } 5105 + 5106 + write_fp_sreg(s, rd, tcg_res); 5107 + 5108 + tcg_temp_free_ptr(fpst); 5109 + tcg_temp_free_i32(tcg_op1); 5110 + tcg_temp_free_i32(tcg_op2); 5111 + tcg_temp_free_i32(tcg_res); 5112 + } 5113 + 5059 5114 /* Floating point data-processing (2 source) 5060 5115 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 5061 5116 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ ··· 5087 5142 return; 5088 5143 } 5089 5144 handle_fp_2src_double(s, opcode, rd, rn, rm); 5145 + break; 5146 + case 3: 5147 + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { 5148 + unallocated_encoding(s); 5149 + return; 5150 + } 5151 + if (!fp_access_check(s)) { 5152 + return; 5153 + } 5154 + handle_fp_2src_half(s, opcode, rd, rn, rm); 5090 5155 break; 5091 5156 default: 5092 5157 unallocated_encoding(s);