jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
Remove Sun4c, Sun4d and a few CPUs
Sun4c and Sun4d architectures and related CPUs are not fully implemented
(especially Sun4c MMU) and there has been no interest for them.
Likewise, a few CPUs (Cypress, Ross etc) are only half implemented.
Remove the machines and CPUs, they can be re-added if needed later.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
+6
-955
+1
-1
hw/intc/Makefile.objs
+1
-1
hw/intc/Makefile.objs
···
7
7
common-obj-$(CONFIG_IMX) += imx_avic.o
8
8
common-obj-$(CONFIG_LM32) += lm32_pic.o
9
9
common-obj-$(CONFIG_REALVIEW) += realview_gic.o
10
-
common-obj-$(CONFIG_SLAVIO) += sbi.o slavio_intctl.o sun4c_intctl.o
10
+
common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o
11
11
common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
12
12
common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
13
13
-156
hw/intc/sbi.c
-156
hw/intc/sbi.c
···
1
-
/*
2
-
* QEMU Sparc SBI interrupt controller emulation
3
-
*
4
-
* Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
5
-
*
6
-
* Permission is hereby granted, free of charge, to any person obtaining a copy
7
-
* of this software and associated documentation files (the "Software"), to deal
8
-
* in the Software without restriction, including without limitation the rights
9
-
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
-
* copies of the Software, and to permit persons to whom the Software is
11
-
* furnished to do so, subject to the following conditions:
12
-
*
13
-
* The above copyright notice and this permission notice shall be included in
14
-
* all copies or substantial portions of the Software.
15
-
*
16
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
-
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
-
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
-
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
-
* THE SOFTWARE.
23
-
*/
24
-
25
-
#include "hw/sysbus.h"
26
-
27
-
//#define DEBUG_IRQ
28
-
29
-
#ifdef DEBUG_IRQ
30
-
#define DPRINTF(fmt, ...) \
31
-
do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
32
-
#else
33
-
#define DPRINTF(fmt, ...)
34
-
#endif
35
-
36
-
#define MAX_CPUS 16
37
-
38
-
#define SBI_NREGS 16
39
-
40
-
typedef struct SBIState {
41
-
SysBusDevice busdev;
42
-
MemoryRegion iomem;
43
-
uint32_t regs[SBI_NREGS];
44
-
uint32_t intreg_pending[MAX_CPUS];
45
-
qemu_irq cpu_irqs[MAX_CPUS];
46
-
uint32_t pil_out[MAX_CPUS];
47
-
} SBIState;
48
-
49
-
#define SBI_SIZE (SBI_NREGS * 4)
50
-
51
-
static void sbi_set_irq(void *opaque, int irq, int level)
52
-
{
53
-
}
54
-
55
-
static uint64_t sbi_mem_read(void *opaque, hwaddr addr,
56
-
unsigned size)
57
-
{
58
-
SBIState *s = opaque;
59
-
uint32_t saddr, ret;
60
-
61
-
saddr = addr >> 2;
62
-
switch (saddr) {
63
-
default:
64
-
ret = s->regs[saddr];
65
-
break;
66
-
}
67
-
DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
68
-
69
-
return ret;
70
-
}
71
-
72
-
static void sbi_mem_write(void *opaque, hwaddr addr,
73
-
uint64_t val, unsigned dize)
74
-
{
75
-
SBIState *s = opaque;
76
-
uint32_t saddr;
77
-
78
-
saddr = addr >> 2;
79
-
DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, (int)val);
80
-
switch (saddr) {
81
-
default:
82
-
s->regs[saddr] = val;
83
-
break;
84
-
}
85
-
}
86
-
87
-
static const MemoryRegionOps sbi_mem_ops = {
88
-
.read = sbi_mem_read,
89
-
.write = sbi_mem_write,
90
-
.endianness = DEVICE_NATIVE_ENDIAN,
91
-
.valid = {
92
-
.min_access_size = 4,
93
-
.max_access_size = 4,
94
-
},
95
-
};
96
-
97
-
static const VMStateDescription vmstate_sbi = {
98
-
.name ="sbi",
99
-
.version_id = 1,
100
-
.minimum_version_id = 1,
101
-
.minimum_version_id_old = 1,
102
-
.fields = (VMStateField []) {
103
-
VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS),
104
-
VMSTATE_END_OF_LIST()
105
-
}
106
-
};
107
-
108
-
static void sbi_reset(DeviceState *d)
109
-
{
110
-
SBIState *s = container_of(d, SBIState, busdev.qdev);
111
-
unsigned int i;
112
-
113
-
for (i = 0; i < MAX_CPUS; i++) {
114
-
s->intreg_pending[i] = 0;
115
-
}
116
-
}
117
-
118
-
static int sbi_init1(SysBusDevice *dev)
119
-
{
120
-
SBIState *s = FROM_SYSBUS(SBIState, dev);
121
-
unsigned int i;
122
-
123
-
qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS);
124
-
for (i = 0; i < MAX_CPUS; i++) {
125
-
sysbus_init_irq(dev, &s->cpu_irqs[i]);
126
-
}
127
-
128
-
memory_region_init_io(&s->iomem, &sbi_mem_ops, s, "sbi", SBI_SIZE);
129
-
sysbus_init_mmio(dev, &s->iomem);
130
-
131
-
return 0;
132
-
}
133
-
134
-
static void sbi_class_init(ObjectClass *klass, void *data)
135
-
{
136
-
DeviceClass *dc = DEVICE_CLASS(klass);
137
-
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
138
-
139
-
k->init = sbi_init1;
140
-
dc->reset = sbi_reset;
141
-
dc->vmsd = &vmstate_sbi;
142
-
}
143
-
144
-
static const TypeInfo sbi_info = {
145
-
.name = "sbi",
146
-
.parent = TYPE_SYS_BUS_DEVICE,
147
-
.instance_size = sizeof(SBIState),
148
-
.class_init = sbi_class_init,
149
-
};
150
-
151
-
static void sbi_register_types(void)
152
-
{
153
-
type_register_static(&sbi_info);
154
-
}
155
-
156
-
type_init(sbi_register_types)
-208
hw/intc/sun4c_intctl.c
-208
hw/intc/sun4c_intctl.c
···
1
-
/*
2
-
* QEMU Sparc Sun4c interrupt controller emulation
3
-
*
4
-
* Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
5
-
*
6
-
* Permission is hereby granted, free of charge, to any person obtaining a copy
7
-
* of this software and associated documentation files (the "Software"), to deal
8
-
* in the Software without restriction, including without limitation the rights
9
-
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
-
* copies of the Software, and to permit persons to whom the Software is
11
-
* furnished to do so, subject to the following conditions:
12
-
*
13
-
* The above copyright notice and this permission notice shall be included in
14
-
* all copies or substantial portions of the Software.
15
-
*
16
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
-
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
-
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
-
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
-
* THE SOFTWARE.
23
-
*/
24
-
25
-
#include "hw/hw.h"
26
-
#include "hw/sparc/sun4m.h"
27
-
#include "monitor/monitor.h"
28
-
#include "hw/sysbus.h"
29
-
30
-
//#define DEBUG_IRQ_COUNT
31
-
//#define DEBUG_IRQ
32
-
33
-
#ifdef DEBUG_IRQ
34
-
#define DPRINTF(fmt, ...) \
35
-
do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
36
-
#else
37
-
#define DPRINTF(fmt, ...)
38
-
#endif
39
-
40
-
/*
41
-
* Registers of interrupt controller in sun4c.
42
-
*
43
-
*/
44
-
45
-
#define MAX_PILS 16
46
-
47
-
typedef struct Sun4c_INTCTLState {
48
-
SysBusDevice busdev;
49
-
MemoryRegion iomem;
50
-
#ifdef DEBUG_IRQ_COUNT
51
-
uint64_t irq_count;
52
-
#endif
53
-
qemu_irq cpu_irqs[MAX_PILS];
54
-
const uint32_t *intbit_to_level;
55
-
uint32_t pil_out;
56
-
uint8_t reg;
57
-
uint8_t pending;
58
-
} Sun4c_INTCTLState;
59
-
60
-
#define INTCTL_SIZE 1
61
-
62
-
static void sun4c_check_interrupts(void *opaque);
63
-
64
-
static uint64_t sun4c_intctl_mem_read(void *opaque, hwaddr addr,
65
-
unsigned size)
66
-
{
67
-
Sun4c_INTCTLState *s = opaque;
68
-
uint32_t ret;
69
-
70
-
ret = s->reg;
71
-
DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
72
-
73
-
return ret;
74
-
}
75
-
76
-
static void sun4c_intctl_mem_write(void *opaque, hwaddr addr,
77
-
uint64_t val, unsigned size)
78
-
{
79
-
Sun4c_INTCTLState *s = opaque;
80
-
81
-
DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, (unsigned)val);
82
-
val &= 0xbf;
83
-
s->reg = val;
84
-
sun4c_check_interrupts(s);
85
-
}
86
-
87
-
static const MemoryRegionOps sun4c_intctl_mem_ops = {
88
-
.read = sun4c_intctl_mem_read,
89
-
.write = sun4c_intctl_mem_write,
90
-
.endianness = DEVICE_NATIVE_ENDIAN,
91
-
.valid = {
92
-
.min_access_size = 1,
93
-
.max_access_size = 1,
94
-
},
95
-
};
96
-
97
-
static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
98
-
99
-
static void sun4c_check_interrupts(void *opaque)
100
-
{
101
-
Sun4c_INTCTLState *s = opaque;
102
-
uint32_t pil_pending;
103
-
unsigned int i;
104
-
105
-
pil_pending = 0;
106
-
if (s->pending && !(s->reg & 0x80000000)) {
107
-
for (i = 0; i < 8; i++) {
108
-
if (s->pending & (1 << i))
109
-
pil_pending |= 1 << intbit_to_level[i];
110
-
}
111
-
}
112
-
113
-
for (i = 0; i < MAX_PILS; i++) {
114
-
if (pil_pending & (1 << i)) {
115
-
if (!(s->pil_out & (1 << i)))
116
-
qemu_irq_raise(s->cpu_irqs[i]);
117
-
} else {
118
-
if (s->pil_out & (1 << i))
119
-
qemu_irq_lower(s->cpu_irqs[i]);
120
-
}
121
-
}
122
-
s->pil_out = pil_pending;
123
-
}
124
-
125
-
/*
126
-
* "irq" here is the bit number in the system interrupt register
127
-
*/
128
-
static void sun4c_set_irq(void *opaque, int irq, int level)
129
-
{
130
-
Sun4c_INTCTLState *s = opaque;
131
-
uint32_t mask = 1 << irq;
132
-
uint32_t pil = intbit_to_level[irq];
133
-
134
-
DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
135
-
level);
136
-
if (pil > 0) {
137
-
if (level) {
138
-
#ifdef DEBUG_IRQ_COUNT
139
-
s->irq_count++;
140
-
#endif
141
-
s->pending |= mask;
142
-
} else {
143
-
s->pending &= ~mask;
144
-
}
145
-
sun4c_check_interrupts(s);
146
-
}
147
-
}
148
-
149
-
static const VMStateDescription vmstate_sun4c_intctl = {
150
-
.name ="sun4c_intctl",
151
-
.version_id = 1,
152
-
.minimum_version_id = 1,
153
-
.minimum_version_id_old = 1,
154
-
.fields = (VMStateField []) {
155
-
VMSTATE_UINT8(reg, Sun4c_INTCTLState),
156
-
VMSTATE_UINT8(pending, Sun4c_INTCTLState),
157
-
VMSTATE_END_OF_LIST()
158
-
}
159
-
};
160
-
161
-
static void sun4c_intctl_reset(DeviceState *d)
162
-
{
163
-
Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev);
164
-
165
-
s->reg = 1;
166
-
s->pending = 0;
167
-
}
168
-
169
-
static int sun4c_intctl_init1(SysBusDevice *dev)
170
-
{
171
-
Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
172
-
unsigned int i;
173
-
174
-
memory_region_init_io(&s->iomem, &sun4c_intctl_mem_ops, s,
175
-
"intctl", INTCTL_SIZE);
176
-
sysbus_init_mmio(dev, &s->iomem);
177
-
qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
178
-
179
-
for (i = 0; i < MAX_PILS; i++) {
180
-
sysbus_init_irq(dev, &s->cpu_irqs[i]);
181
-
}
182
-
183
-
return 0;
184
-
}
185
-
186
-
static void sun4c_intctl_class_init(ObjectClass *klass, void *data)
187
-
{
188
-
DeviceClass *dc = DEVICE_CLASS(klass);
189
-
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
190
-
191
-
k->init = sun4c_intctl_init1;
192
-
dc->reset = sun4c_intctl_reset;
193
-
dc->vmsd = &vmstate_sun4c_intctl;
194
-
}
195
-
196
-
static const TypeInfo sun4c_intctl_info = {
197
-
.name = "sun4c_intctl",
198
-
.parent = TYPE_SYS_BUS_DEVICE,
199
-
.instance_size = sizeof(Sun4c_INTCTLState),
200
-
.class_init = sun4c_intctl_class_init,
201
-
};
202
-
203
-
static void sun4c_intctl_register_types(void)
204
-
{
205
-
type_register_static(&sun4c_intctl_info);
206
-
}
207
-
208
-
type_init(sun4c_intctl_register_types)
+2
-461
hw/sparc/sun4m.c
+2
-461
hw/sparc/sun4m.c
···
55
55
* SPARCstation 20/xx, SPARCserver 20
56
56
* SPARCstation 4
57
57
*
58
-
* Sun4d architecture was used in the following machines:
59
-
*
60
-
* SPARCcenter 2000
61
-
* SPARCserver 1000
62
-
*
63
-
* Sun4c architecture was used in the following machines:
64
-
* SPARCstation 1/1+, SPARCserver 1/1+
65
-
* SPARCstation SLC
66
-
* SPARCstation IPC
67
-
* SPARCstation ELC
68
-
* SPARCstation IPX
69
-
*
70
58
* See for example: http://www.sunhelp.org/faq/sunref1.html
71
59
*/
72
60
···
99
87
uint64_t max_mem;
100
88
const char * const default_cpu_model;
101
89
uint32_t ecc_version;
102
-
uint32_t iommu_version;
103
-
uint16_t machine_id;
104
-
uint8_t nvram_machine_id;
105
-
};
106
-
107
-
#define MAX_IOUNITS 5
108
-
109
-
struct sun4d_hwdef {
110
-
hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
111
-
hwaddr counter_base, nvram_base, ms_kb_base;
112
-
hwaddr serial_base;
113
-
hwaddr espdma_base, esp_base;
114
-
hwaddr ledma_base, le_base;
115
-
hwaddr tcx_base;
116
-
hwaddr sbi_base;
117
-
uint64_t max_mem;
118
-
const char * const default_cpu_model;
119
-
uint32_t iounit_version;
120
-
uint16_t machine_id;
121
-
uint8_t nvram_machine_id;
122
-
};
123
-
124
-
struct sun4c_hwdef {
125
-
hwaddr iommu_base, slavio_base;
126
-
hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
127
-
hwaddr serial_base, fd_base;
128
-
hwaddr idreg_base, dma_base, esp_base, le_base;
129
-
hwaddr tcx_base, aux1_base;
130
-
uint64_t max_mem;
131
-
const char * const default_cpu_model;
132
90
uint32_t iommu_version;
133
91
uint16_t machine_id;
134
92
uint8_t nvram_machine_id;
···
1052
1010
}
1053
1011
1054
1012
enum {
1055
-
ss2_id = 0,
1056
1013
ss5_id = 32,
1057
1014
vger_id,
1058
1015
lx_id,
···
1062
1019
ss10_id = 64,
1063
1020
ss20_id,
1064
1021
ss600mp_id,
1065
-
ss1000_id = 96,
1066
-
ss2000_id,
1067
1022
};
1068
1023
1069
1024
static const struct sun4m_hwdef sun4m_hwdefs[] = {
···
1504
1459
DEFAULT_MACHINE_OPTIONS,
1505
1460
};
1506
1461
1507
-
static const struct sun4d_hwdef sun4d_hwdefs[] = {
1508
-
/* SS-1000 */
1509
-
{
1510
-
.iounit_bases = {
1511
-
0xfe0200000ULL,
1512
-
0xfe1200000ULL,
1513
-
0xfe2200000ULL,
1514
-
0xfe3200000ULL,
1515
-
-1,
1516
-
},
1517
-
.tcx_base = 0x820000000ULL,
1518
-
.slavio_base = 0xf00000000ULL,
1519
-
.ms_kb_base = 0xf00240000ULL,
1520
-
.serial_base = 0xf00200000ULL,
1521
-
.nvram_base = 0xf00280000ULL,
1522
-
.counter_base = 0xf00300000ULL,
1523
-
.espdma_base = 0x800081000ULL,
1524
-
.esp_base = 0x800080000ULL,
1525
-
.ledma_base = 0x800040000ULL,
1526
-
.le_base = 0x800060000ULL,
1527
-
.sbi_base = 0xf02800000ULL,
1528
-
.nvram_machine_id = 0x80,
1529
-
.machine_id = ss1000_id,
1530
-
.iounit_version = 0x03000000,
1531
-
.max_mem = 0xf00000000ULL,
1532
-
.default_cpu_model = "TI SuperSparc II",
1533
-
},
1534
-
/* SS-2000 */
1535
-
{
1536
-
.iounit_bases = {
1537
-
0xfe0200000ULL,
1538
-
0xfe1200000ULL,
1539
-
0xfe2200000ULL,
1540
-
0xfe3200000ULL,
1541
-
0xfe4200000ULL,
1542
-
},
1543
-
.tcx_base = 0x820000000ULL,
1544
-
.slavio_base = 0xf00000000ULL,
1545
-
.ms_kb_base = 0xf00240000ULL,
1546
-
.serial_base = 0xf00200000ULL,
1547
-
.nvram_base = 0xf00280000ULL,
1548
-
.counter_base = 0xf00300000ULL,
1549
-
.espdma_base = 0x800081000ULL,
1550
-
.esp_base = 0x800080000ULL,
1551
-
.ledma_base = 0x800040000ULL,
1552
-
.le_base = 0x800060000ULL,
1553
-
.sbi_base = 0xf02800000ULL,
1554
-
.nvram_machine_id = 0x80,
1555
-
.machine_id = ss2000_id,
1556
-
.iounit_version = 0x03000000,
1557
-
.max_mem = 0xf00000000ULL,
1558
-
.default_cpu_model = "TI SuperSparc II",
1559
-
},
1560
-
};
1561
-
1562
-
static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
1563
-
{
1564
-
DeviceState *dev;
1565
-
SysBusDevice *s;
1566
-
unsigned int i;
1567
-
1568
-
dev = qdev_create(NULL, "sbi");
1569
-
qdev_init_nofail(dev);
1570
-
1571
-
s = SYS_BUS_DEVICE(dev);
1572
-
1573
-
for (i = 0; i < MAX_CPUS; i++) {
1574
-
sysbus_connect_irq(s, i, *parent_irq[i]);
1575
-
}
1576
-
1577
-
sysbus_mmio_map(s, 0, addr);
1578
-
1579
-
return dev;
1580
-
}
1581
-
1582
-
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1583
-
const char *boot_device,
1584
-
const char *kernel_filename,
1585
-
const char *kernel_cmdline,
1586
-
const char *initrd_filename, const char *cpu_model)
1587
-
{
1588
-
unsigned int i;
1589
-
void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1590
-
qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1591
-
espdma_irq, ledma_irq;
1592
-
qemu_irq esp_reset, dma_enable;
1593
-
unsigned long kernel_size;
1594
-
void *fw_cfg;
1595
-
DeviceState *dev;
1596
-
1597
-
/* init CPUs */
1598
-
if (!cpu_model)
1599
-
cpu_model = hwdef->default_cpu_model;
1600
-
1601
-
for(i = 0; i < smp_cpus; i++) {
1602
-
cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1603
-
}
1604
-
1605
-
for (i = smp_cpus; i < MAX_CPUS; i++)
1606
-
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1607
-
1608
-
/* set up devices */
1609
-
ram_init(0, RAM_size, hwdef->max_mem);
1610
-
1611
-
prom_init(hwdef->slavio_base, bios_name);
1612
-
1613
-
dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1614
-
1615
-
for (i = 0; i < 32; i++) {
1616
-
sbi_irq[i] = qdev_get_gpio_in(dev, i);
1617
-
}
1618
-
for (i = 0; i < MAX_CPUS; i++) {
1619
-
sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1620
-
}
1621
-
1622
-
for (i = 0; i < MAX_IOUNITS; i++)
1623
-
if (hwdef->iounit_bases[i] != (hwaddr)-1)
1624
-
iounits[i] = iommu_init(hwdef->iounit_bases[i],
1625
-
hwdef->iounit_version,
1626
-
sbi_irq[0]);
1627
-
1628
-
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1629
-
iounits[0], &espdma_irq, 0);
1630
-
1631
-
/* should be lebuffer instead */
1632
-
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1633
-
iounits[0], &ledma_irq, 0);
1634
-
1635
-
if (graphic_depth != 8 && graphic_depth != 24) {
1636
-
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1637
-
exit (1);
1638
-
}
1639
-
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1640
-
graphic_depth);
1641
-
1642
-
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1643
-
1644
-
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1645
-
1646
-
slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1647
-
1648
-
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1649
-
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1650
-
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1651
-
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1652
-
escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1653
-
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1654
-
1655
-
if (drive_get_max_bus(IF_SCSI) > 0) {
1656
-
fprintf(stderr, "qemu: too many SCSI bus\n");
1657
-
exit(1);
1658
-
}
1659
-
1660
-
esp_init(hwdef->esp_base, 2,
1661
-
espdma_memory_read, espdma_memory_write,
1662
-
espdma, espdma_irq, &esp_reset, &dma_enable);
1663
-
1664
-
qdev_connect_gpio_out(espdma, 0, esp_reset);
1665
-
qdev_connect_gpio_out(espdma, 1, dma_enable);
1666
-
1667
-
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1668
-
RAM_size);
1669
-
1670
-
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1671
-
boot_device, RAM_size, kernel_size, graphic_width,
1672
-
graphic_height, graphic_depth, hwdef->nvram_machine_id,
1673
-
"Sun4d");
1674
-
1675
-
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1676
-
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1677
-
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1678
-
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1679
-
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1680
-
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1681
-
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1682
-
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1683
-
if (kernel_cmdline) {
1684
-
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1685
-
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1686
-
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1687
-
} else {
1688
-
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1689
-
}
1690
-
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1691
-
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1692
-
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1693
-
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1694
-
}
1695
-
1696
-
/* SPARCserver 1000 hardware initialisation */
1697
-
static void ss1000_init(QEMUMachineInitArgs *args)
1698
-
{
1699
-
ram_addr_t RAM_size = args->ram_size;
1700
-
const char *cpu_model = args->cpu_model;
1701
-
const char *kernel_filename = args->kernel_filename;
1702
-
const char *kernel_cmdline = args->kernel_cmdline;
1703
-
const char *initrd_filename = args->initrd_filename;
1704
-
const char *boot_device = args->boot_device;
1705
-
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1706
-
kernel_cmdline, initrd_filename, cpu_model);
1707
-
}
1708
-
1709
-
/* SPARCcenter 2000 hardware initialisation */
1710
-
static void ss2000_init(QEMUMachineInitArgs *args)
1711
-
{
1712
-
ram_addr_t RAM_size = args->ram_size;
1713
-
const char *cpu_model = args->cpu_model;
1714
-
const char *kernel_filename = args->kernel_filename;
1715
-
const char *kernel_cmdline = args->kernel_cmdline;
1716
-
const char *initrd_filename = args->initrd_filename;
1717
-
const char *boot_device = args->boot_device;
1718
-
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1719
-
kernel_cmdline, initrd_filename, cpu_model);
1720
-
}
1721
-
1722
-
static QEMUMachine ss1000_machine = {
1723
-
.name = "SS-1000",
1724
-
.desc = "Sun4d platform, SPARCserver 1000",
1725
-
.init = ss1000_init,
1726
-
.block_default_type = IF_SCSI,
1727
-
.max_cpus = 8,
1728
-
DEFAULT_MACHINE_OPTIONS,
1729
-
};
1730
-
1731
-
static QEMUMachine ss2000_machine = {
1732
-
.name = "SS-2000",
1733
-
.desc = "Sun4d platform, SPARCcenter 2000",
1734
-
.init = ss2000_init,
1735
-
.block_default_type = IF_SCSI,
1736
-
.max_cpus = 20,
1737
-
DEFAULT_MACHINE_OPTIONS,
1738
-
};
1739
-
1740
-
static const struct sun4c_hwdef sun4c_hwdefs[] = {
1741
-
/* SS-2 */
1742
-
{
1743
-
.iommu_base = 0xf8000000,
1744
-
.tcx_base = 0xfe000000,
1745
-
.slavio_base = 0xf6000000,
1746
-
.intctl_base = 0xf5000000,
1747
-
.counter_base = 0xf3000000,
1748
-
.ms_kb_base = 0xf0000000,
1749
-
.serial_base = 0xf1000000,
1750
-
.nvram_base = 0xf2000000,
1751
-
.fd_base = 0xf7200000,
1752
-
.dma_base = 0xf8400000,
1753
-
.esp_base = 0xf8800000,
1754
-
.le_base = 0xf8c00000,
1755
-
.aux1_base = 0xf7400003,
1756
-
.nvram_machine_id = 0x55,
1757
-
.machine_id = ss2_id,
1758
-
.max_mem = 0x10000000,
1759
-
.default_cpu_model = "Cypress CY7C601",
1760
-
},
1761
-
};
1762
-
1763
-
static DeviceState *sun4c_intctl_init(hwaddr addr,
1764
-
qemu_irq *parent_irq)
1765
-
{
1766
-
DeviceState *dev;
1767
-
SysBusDevice *s;
1768
-
unsigned int i;
1769
-
1770
-
dev = qdev_create(NULL, "sun4c_intctl");
1771
-
qdev_init_nofail(dev);
1772
-
1773
-
s = SYS_BUS_DEVICE(dev);
1774
-
1775
-
for (i = 0; i < MAX_PILS; i++) {
1776
-
sysbus_connect_irq(s, i, parent_irq[i]);
1777
-
}
1778
-
sysbus_mmio_map(s, 0, addr);
1779
-
1780
-
return dev;
1781
-
}
1782
-
1783
-
static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1784
-
const char *boot_device,
1785
-
const char *kernel_filename,
1786
-
const char *kernel_cmdline,
1787
-
const char *initrd_filename, const char *cpu_model)
1788
-
{
1789
-
void *iommu, *espdma, *ledma, *nvram;
1790
-
qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1791
-
qemu_irq esp_reset, dma_enable;
1792
-
qemu_irq fdc_tc;
1793
-
unsigned long kernel_size;
1794
-
DriveInfo *fd[MAX_FD];
1795
-
void *fw_cfg;
1796
-
DeviceState *dev;
1797
-
unsigned int i;
1798
-
1799
-
/* init CPU */
1800
-
if (!cpu_model)
1801
-
cpu_model = hwdef->default_cpu_model;
1802
-
1803
-
cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1804
-
1805
-
/* set up devices */
1806
-
ram_init(0, RAM_size, hwdef->max_mem);
1807
-
1808
-
prom_init(hwdef->slavio_base, bios_name);
1809
-
1810
-
dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1811
-
1812
-
for (i = 0; i < 8; i++) {
1813
-
slavio_irq[i] = qdev_get_gpio_in(dev, i);
1814
-
}
1815
-
1816
-
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1817
-
slavio_irq[1]);
1818
-
1819
-
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1820
-
iommu, &espdma_irq, 0);
1821
-
1822
-
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1823
-
slavio_irq[3], iommu, &ledma_irq, 1);
1824
-
1825
-
if (graphic_depth != 8 && graphic_depth != 24) {
1826
-
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1827
-
exit (1);
1828
-
}
1829
-
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1830
-
graphic_depth);
1831
-
1832
-
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1833
-
1834
-
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1835
-
1836
-
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1837
-
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1838
-
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1839
-
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1840
-
escc_init(hwdef->serial_base, slavio_irq[1],
1841
-
slavio_irq[1], serial_hds[0], serial_hds[1],
1842
-
ESCC_CLOCK, 1);
1843
-
1844
-
if (hwdef->fd_base != (hwaddr)-1) {
1845
-
/* there is zero or one floppy drive */
1846
-
memset(fd, 0, sizeof(fd));
1847
-
fd[0] = drive_get(IF_FLOPPY, 0, 0);
1848
-
sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1849
-
&fdc_tc);
1850
-
} else {
1851
-
fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1852
-
}
1853
-
1854
-
slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1855
-
1856
-
if (drive_get_max_bus(IF_SCSI) > 0) {
1857
-
fprintf(stderr, "qemu: too many SCSI bus\n");
1858
-
exit(1);
1859
-
}
1860
-
1861
-
esp_init(hwdef->esp_base, 2,
1862
-
espdma_memory_read, espdma_memory_write,
1863
-
espdma, espdma_irq, &esp_reset, &dma_enable);
1864
-
1865
-
qdev_connect_gpio_out(espdma, 0, esp_reset);
1866
-
qdev_connect_gpio_out(espdma, 1, dma_enable);
1867
-
1868
-
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1869
-
RAM_size);
1870
-
1871
-
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1872
-
boot_device, RAM_size, kernel_size, graphic_width,
1873
-
graphic_height, graphic_depth, hwdef->nvram_machine_id,
1874
-
"Sun4c");
1875
-
1876
-
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1877
-
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1878
-
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1879
-
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1880
-
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1881
-
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1882
-
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1883
-
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1884
-
if (kernel_cmdline) {
1885
-
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1886
-
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1887
-
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1888
-
} else {
1889
-
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1890
-
}
1891
-
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1892
-
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1893
-
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1894
-
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1895
-
}
1896
-
1897
-
/* SPARCstation 2 hardware initialisation */
1898
-
static void ss2_init(QEMUMachineInitArgs *args)
1899
-
{
1900
-
ram_addr_t RAM_size = args->ram_size;
1901
-
const char *cpu_model = args->cpu_model;
1902
-
const char *kernel_filename = args->kernel_filename;
1903
-
const char *kernel_cmdline = args->kernel_cmdline;
1904
-
const char *initrd_filename = args->initrd_filename;
1905
-
const char *boot_device = args->boot_device;
1906
-
sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1907
-
kernel_cmdline, initrd_filename, cpu_model);
1908
-
}
1909
-
1910
-
static QEMUMachine ss2_machine = {
1911
-
.name = "SS-2",
1912
-
.desc = "Sun4c platform, SPARCstation 2",
1913
-
.init = ss2_init,
1914
-
.block_default_type = IF_SCSI,
1915
-
DEFAULT_MACHINE_OPTIONS,
1916
-
};
1917
-
1918
1462
static void sun4m_register_types(void)
1919
1463
{
1920
1464
type_register_static(&idreg_info);
···
1923
1467
type_register_static(&ram_info);
1924
1468
}
1925
1469
1926
-
static void ss2_machine_init(void)
1470
+
static void sun4m_machine_init(void)
1927
1471
{
1928
1472
qemu_register_machine(&ss5_machine);
1929
1473
qemu_register_machine(&ss10_machine);
···
1934
1478
qemu_register_machine(&ss4_machine);
1935
1479
qemu_register_machine(&scls_machine);
1936
1480
qemu_register_machine(&sbook_machine);
1937
-
qemu_register_machine(&ss1000_machine);
1938
-
qemu_register_machine(&ss2000_machine);
1939
-
qemu_register_machine(&ss2_machine);
1940
1481
}
1941
1482
1942
1483
type_init(sun4m_register_types)
1943
-
machine_init(ss2_machine_init);
1484
+
machine_init(sun4m_machine_init);
+3
-7
qemu-doc.texi
+3
-7
qemu-doc.texi
···
1958
1958
The emulation is somewhat complete. SMP up to 16 CPUs is supported,
1959
1959
but Linux limits the number of usable CPUs to 4.
1960
1960
1961
-
It's also possible to simulate a SPARCstation 2 (sun4c architecture),
1962
-
SPARCserver 1000, or SPARCcenter 2000 (sun4d architecture), but these
1963
-
emulators are not usable yet.
1964
-
1965
-
QEMU emulates the following sun4m/sun4c/sun4d peripherals:
1961
+
QEMU emulates the following sun4m peripherals:
1966
1962
1967
1963
@itemize @minus
1968
1964
@item
1969
-
IOMMU or IO-UNITs
1965
+
IOMMU
1970
1966
@item
1971
1967
TCX Frame buffer
1972
1968
@item
···
2019
2015
-prom-env 'boot-device=sd(0,2,0):d' -prom-env 'boot-args=linux single'
2020
2016
@end example
2021
2017
2022
-
@item -M [SS-4|SS-5|SS-10|SS-20|SS-600MP|LX|Voyager|SPARCClassic] [|SPARCbook|SS-2|SS-1000|SS-2000]
2018
+
@item -M [SS-4|SS-5|SS-10|SS-20|SS-600MP|LX|Voyager|SPARCClassic] [|SPARCbook]
2023
2019
2024
2020
Set the emulated machine type. Default is SS-5.
2025
2021
-122
target-sparc/cpu.c
-122
target-sparc/cpu.c
···
292
292
},
293
293
#else
294
294
{
295
-
.name = "Fujitsu MB86900",
296
-
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */
297
-
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
298
-
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
299
-
.mmu_bm = 0x00004000,
300
-
.mmu_ctpr_mask = 0x007ffff0,
301
-
.mmu_cxr_mask = 0x0000003f,
302
-
.mmu_sfsr_mask = 0xffffffff,
303
-
.mmu_trcr_mask = 0xffffffff,
304
-
.nwindows = 7,
305
-
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
306
-
},
307
-
{
308
295
.name = "Fujitsu MB86904",
309
296
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
310
297
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
···
329
316
.mmu_trcr_mask = 0xffffffff,
330
317
.nwindows = 8,
331
318
.features = CPU_DEFAULT_FEATURES,
332
-
},
333
-
{
334
-
.name = "LSI L64811",
335
-
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */
336
-
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
337
-
.mmu_version = 0x10 << 24,
338
-
.mmu_bm = 0x00004000,
339
-
.mmu_ctpr_mask = 0x007ffff0,
340
-
.mmu_cxr_mask = 0x0000003f,
341
-
.mmu_sfsr_mask = 0xffffffff,
342
-
.mmu_trcr_mask = 0xffffffff,
343
-
.nwindows = 8,
344
-
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
345
-
CPU_FEATURE_FSMULD,
346
-
},
347
-
{
348
-
.name = "Cypress CY7C601",
349
-
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */
350
-
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
351
-
.mmu_version = 0x10 << 24,
352
-
.mmu_bm = 0x00004000,
353
-
.mmu_ctpr_mask = 0x007ffff0,
354
-
.mmu_cxr_mask = 0x0000003f,
355
-
.mmu_sfsr_mask = 0xffffffff,
356
-
.mmu_trcr_mask = 0xffffffff,
357
-
.nwindows = 8,
358
-
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
359
-
CPU_FEATURE_FSMULD,
360
-
},
361
-
{
362
-
.name = "Cypress CY7C611",
363
-
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */
364
-
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
365
-
.mmu_version = 0x10 << 24,
366
-
.mmu_bm = 0x00004000,
367
-
.mmu_ctpr_mask = 0x007ffff0,
368
-
.mmu_cxr_mask = 0x0000003f,
369
-
.mmu_sfsr_mask = 0xffffffff,
370
-
.mmu_trcr_mask = 0xffffffff,
371
-
.nwindows = 8,
372
-
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
373
-
CPU_FEATURE_FSMULD,
374
319
},
375
320
{
376
321
.name = "TI MicroSparc I",
···
491
436
.mmu_sfsr_mask = 0xffffffff,
492
437
.mmu_trcr_mask = 0xffffffff,
493
438
.mxcc_version = 0x00000104,
494
-
.nwindows = 8,
495
-
.features = CPU_DEFAULT_FEATURES,
496
-
},
497
-
{
498
-
.name = "Ross RT625",
499
-
.iu_version = 0x1e000000,
500
-
.fpu_version = 1 << 17,
501
-
.mmu_version = 0x1e000000,
502
-
.mmu_bm = 0x00004000,
503
-
.mmu_ctpr_mask = 0x007ffff0,
504
-
.mmu_cxr_mask = 0x0000003f,
505
-
.mmu_sfsr_mask = 0xffffffff,
506
-
.mmu_trcr_mask = 0xffffffff,
507
-
.nwindows = 8,
508
-
.features = CPU_DEFAULT_FEATURES,
509
-
},
510
-
{
511
-
.name = "Ross RT620",
512
-
.iu_version = 0x1f000000,
513
-
.fpu_version = 1 << 17,
514
-
.mmu_version = 0x1f000000,
515
-
.mmu_bm = 0x00004000,
516
-
.mmu_ctpr_mask = 0x007ffff0,
517
-
.mmu_cxr_mask = 0x0000003f,
518
-
.mmu_sfsr_mask = 0xffffffff,
519
-
.mmu_trcr_mask = 0xffffffff,
520
-
.nwindows = 8,
521
-
.features = CPU_DEFAULT_FEATURES,
522
-
},
523
-
{
524
-
.name = "BIT B5010",
525
-
.iu_version = 0x20000000,
526
-
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
527
-
.mmu_version = 0x20000000,
528
-
.mmu_bm = 0x00004000,
529
-
.mmu_ctpr_mask = 0x007ffff0,
530
-
.mmu_cxr_mask = 0x0000003f,
531
-
.mmu_sfsr_mask = 0xffffffff,
532
-
.mmu_trcr_mask = 0xffffffff,
533
-
.nwindows = 8,
534
-
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
535
-
CPU_FEATURE_FSMULD,
536
-
},
537
-
{
538
-
.name = "Matsushita MN10501",
539
-
.iu_version = 0x50000000,
540
-
.fpu_version = 0 << 17,
541
-
.mmu_version = 0x50000000,
542
-
.mmu_bm = 0x00004000,
543
-
.mmu_ctpr_mask = 0x007ffff0,
544
-
.mmu_cxr_mask = 0x0000003f,
545
-
.mmu_sfsr_mask = 0xffffffff,
546
-
.mmu_trcr_mask = 0xffffffff,
547
-
.nwindows = 8,
548
-
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
549
-
CPU_FEATURE_FSMULD,
550
-
},
551
-
{
552
-
.name = "Weitek W8601",
553
-
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */
554
-
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
555
-
.mmu_version = 0x10 << 24,
556
-
.mmu_bm = 0x00004000,
557
-
.mmu_ctpr_mask = 0x007ffff0,
558
-
.mmu_cxr_mask = 0x0000003f,
559
-
.mmu_sfsr_mask = 0xffffffff,
560
-
.mmu_trcr_mask = 0xffffffff,
561
439
.nwindows = 8,
562
440
.features = CPU_DEFAULT_FEATURES,
563
441
},