jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200603' into staging
This is a collection of RISC-V patches for 5.1.
This incldues removing deprecated features and part of the OpenTitan
support series.
# gpg: Signature made Wed 03 Jun 2020 17:12:43 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20200603:
riscv: Initial commit of OpenTitan machine
target/riscv: Add the lowRISC Ibex CPU
target/riscv: Don't set PMP feature in the cpu init
target/riscv: Disable the MMU correctly
target/riscv: Don't overwrite the reset vector
riscv/boot: Add a missing header include
riscv: sifive_e: Manually define the machine
docs: deprecated: Update the -bios documentation
target/riscv: Drop support for ISA spec version 1.09.1
target/riscv: Remove the deprecated CPUs
hw/riscv: spike: Remove deprecated ISA specific machines
hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
riscv: Change the default behavior if no -bios option is specified
riscv: Suppress the error report for QEMU testing with riscv_find_firmware()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+478
-571
+9
MAINTAINERS
+9
MAINTAINERS
···
1238
1238
F: pc-bios/u-boot-sam460ex-20100605.bin
1239
1239
F: roms/u-boot-sam460ex
1240
1240
1241
+
RISC-V Machines
1242
+
---------------
1243
+
OpenTitan
1244
+
M: Alistair Francis <Alistair.Francis@wdc.com>
1245
+
L: qemu-riscv@nongnu.org
1246
+
S: Supported
1247
+
F: hw/riscv/opentitan.c
1248
+
F: include/hw/riscv/opentitan.h
1249
+
1241
1250
SH4 Machines
1242
1251
------------
1243
1252
R2D
+1
default-configs/riscv32-softmmu.mak
+1
default-configs/riscv32-softmmu.mak
+10
-1
default-configs/riscv64-softmmu.mak
+10
-1
default-configs/riscv64-softmmu.mak
···
1
1
# Default configuration for riscv64-softmmu
2
2
3
-
include riscv32-softmmu.mak
3
+
# Uncomment the following lines to disable these optional devices:
4
+
#
5
+
#CONFIG_PCI_DEVICES=n
6
+
7
+
# Boards:
8
+
#
9
+
CONFIG_SPIKE=y
10
+
CONFIG_SIFIVE_E=y
11
+
CONFIG_SIFIVE_U=y
12
+
CONFIG_RISCV_VIRT=y
+49
-45
docs/system/deprecated.rst
+49
-45
docs/system/deprecated.rst
···
138
138
the guest RAM configured with ``-m`` and QEMU will fail to start up if
139
139
RAM allocation is unsuccessful.
140
140
141
-
RISC-V ``-bios`` (since 4.1)
141
+
RISC-V ``-bios`` (since 5.1)
142
142
''''''''''''''''''''''''''''
143
143
144
144
QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the
145
-
RISC-V virt machine and sifive_u machine.
145
+
RISC-V virt machine and sifive_u machine. QEMU 4.1 had no changes to the
146
+
default behaviour to avoid breakages.
146
147
147
-
QEMU 4.1 has no changes to the default behaviour to avoid breakages. This
148
-
default will change in a future QEMU release, so please prepare now. All users
149
-
of the virt or sifive_u machine must change their command line usage.
148
+
QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``.
150
149
151
-
QEMU 4.1 has three options, please migrate to one of these three:
152
-
1. ``-bios none`` - This is the current default behavior if no -bios option
153
-
is included. QEMU will not automatically load any firmware. It is up
150
+
QEMU 5.1 has three options:
151
+
1. ``-bios default`` - This is the current default behavior if no -bios option
152
+
is included. This option will load the default OpenSBI firmware automatically.
153
+
The firmware is included with the QEMU release and no user interaction is
154
+
required. All a user needs to do is specify the kernel they want to boot
155
+
with the -kernel option
156
+
2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
154
157
to the user to load all the images they need.
155
-
2. ``-bios default`` - In a future QEMU release this will become the default
156
-
behaviour if no -bios option is specified. This option will load the
157
-
default OpenSBI firmware automatically. The firmware is included with
158
-
the QEMU release and no user interaction is required. All a user needs
159
-
to do is specify the kernel they want to boot with the -kernel option
160
158
3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmwrae.
161
159
162
160
``-tb-size`` option (since 5.0)
···
301
299
``acl_remove`` commands are deprecated with no replacement. Authorization
302
300
for VNC should be performed using the pluggable QAuthZ objects.
303
301
304
-
Guest Emulator ISAs
305
-
-------------------
306
-
307
-
RISC-V ISA privledge specification version 1.09.1 (since 4.1)
308
-
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
309
-
310
-
The RISC-V ISA privledge specification version 1.09.1 has been deprecated.
311
-
QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
312
-
should be used instead of the 1.09.1 version.
313
-
314
302
System emulator CPUS
315
303
--------------------
316
304
317
-
RISC-V ISA CPUs (since 4.1)
318
-
'''''''''''''''''''''''''''
319
-
320
-
The RISC-V cpus with the ISA version in the CPU name have been depcreated. The
321
-
four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
322
-
``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
323
-
option when using the ``rv32`` or ``rv64`` CPUs.
324
-
325
-
RISC-V ISA CPUs (since 4.1)
326
-
'''''''''''''''''''''''''''
327
-
328
-
The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
329
-
``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
330
-
via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
331
-
332
305
``compat`` property of server class POWER CPUs (since 5.0)
333
306
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
334
307
···
378
351
379
352
These machine types are very old and likely can not be used for live migration
380
353
from old QEMU versions anymore. A newer machine type should be used instead.
381
-
382
-
``spike_v1.9.1`` and ``spike_v1.10`` (since 4.1)
383
-
''''''''''''''''''''''''''''''''''''''''''''''''
384
-
385
-
The version specific Spike machines have been deprecated in favour of the
386
-
generic ``spike`` machine. If you need to specify an older version of the RISC-V
387
-
spec you can use the ``-cpu rv64gcsu,priv_spec=v1.9.1`` command line argument.
388
354
389
355
Device options
390
356
--------------
···
492
458
493
459
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
494
460
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
461
+
462
+
Guest Emulator ISAs
463
+
-------------------
464
+
465
+
RISC-V ISA privledge specification version 1.09.1 (removed in 5.1)
466
+
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
467
+
468
+
The RISC-V ISA privledge specification version 1.09.1 has been removed.
469
+
QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
470
+
should be used instead of the 1.09.1 version.
471
+
472
+
System emulator CPUS
473
+
--------------------
474
+
475
+
RISC-V ISA Specific CPUs (removed in 5.1)
476
+
'''''''''''''''''''''''''''''''''''''''''
477
+
478
+
The RISC-V cpus with the ISA version in the CPU name have been removed. The
479
+
four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
480
+
``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
481
+
option when using the ``rv32`` or ``rv64`` CPUs.
482
+
483
+
RISC-V no MMU CPUs (removed in 5.1)
484
+
'''''''''''''''''''''''''''''''''''
485
+
486
+
The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`` and
487
+
``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be specified
488
+
via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
489
+
490
+
System emulator machines
491
+
------------------------
492
+
493
+
``spike_v1.9.1`` and ``spike_v1.10`` (removed in 5.1)
494
+
'''''''''''''''''''''''''''''''''''''''''''''''''''''
495
+
496
+
The version specific Spike machines have been removed in favour of the
497
+
generic ``spike`` machine. If you need to specify an older version of the RISC-V
498
+
spec you can use the ``-cpu rv64gcsu,priv_spec=v1.10.0`` command line argument.
495
499
496
500
Related binaries
497
501
----------------
+5
hw/riscv/Kconfig
+5
hw/riscv/Kconfig
+1
hw/riscv/Makefile.objs
+1
hw/riscv/Makefile.objs
+15
-30
hw/riscv/boot.c
+15
-30
hw/riscv/boot.c
···
41
41
{
42
42
char *firmware_filename = NULL;
43
43
44
-
if (!machine->firmware) {
44
+
if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
45
45
/*
46
-
* The user didn't specify -bios.
47
-
* At the moment we default to loading nothing when this hapens.
48
-
* In the future this defaul will change to loading the prebuilt
49
-
* OpenSBI firmware. Let's warn the user and then continue.
50
-
*/
51
-
if (!qtest_enabled()) {
52
-
warn_report("No -bios option specified. Not loading a firmware.");
53
-
warn_report("This default will change in a future QEMU release. " \
54
-
"Please use the -bios option to avoid breakages when "\
55
-
"this happens.");
56
-
warn_report("See QEMU's deprecation documentation for details.");
57
-
}
58
-
return;
59
-
}
60
-
61
-
if (!strcmp(machine->firmware, "default")) {
62
-
/*
63
-
* The user has specified "-bios default". That means we are going to
64
-
* load the OpenSBI binary included in the QEMU source.
65
-
*
66
-
* We can't load the binary by default as it will break existing users
67
-
* as users are already loading their own firmware.
68
-
*
69
-
* Let's try to get everyone to specify the -bios option at all times,
70
-
* so then in the future we can make "-bios default" the default option
71
-
* if no -bios option is set without breaking anything.
46
+
* The user didn't specify -bios, or has specified "-bios default".
47
+
* That means we are going to load the OpenSBI binary included in
48
+
* the QEMU source.
72
49
*/
73
50
firmware_filename = riscv_find_firmware(default_machine_firmware);
74
51
} else if (strcmp(machine->firmware, "none")) {
···
88
65
89
66
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
90
67
if (filename == NULL) {
91
-
error_report("Unable to load the RISC-V firmware \"%s\"",
92
-
firmware_filename);
93
-
exit(1);
68
+
if (!qtest_enabled()) {
69
+
/*
70
+
* We only ship plain binary bios images in the QEMU source.
71
+
* With Spike machine that uses ELF images as the default bios,
72
+
* running QEMU test will complain hence let's suppress the error
73
+
* report for QEMU testing.
74
+
*/
75
+
error_report("Unable to load the RISC-V firmware \"%s\"",
76
+
firmware_filename);
77
+
exit(1);
78
+
}
94
79
}
95
80
96
81
return filename;
+184
hw/riscv/opentitan.c
+184
hw/riscv/opentitan.c
···
1
+
/*
2
+
* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3
+
*
4
+
* Copyright (c) 2020 Western Digital
5
+
*
6
+
* Provides a board compatible with the OpenTitan FPGA platform:
7
+
*
8
+
* This program is free software; you can redistribute it and/or modify it
9
+
* under the terms and conditions of the GNU General Public License,
10
+
* version 2 or later, as published by the Free Software Foundation.
11
+
*
12
+
* This program is distributed in the hope it will be useful, but WITHOUT
13
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15
+
* more details.
16
+
*
17
+
* You should have received a copy of the GNU General Public License along with
18
+
* this program. If not, see <http://www.gnu.org/licenses/>.
19
+
*/
20
+
21
+
#include "qemu/osdep.h"
22
+
#include "hw/riscv/opentitan.h"
23
+
#include "qapi/error.h"
24
+
#include "hw/boards.h"
25
+
#include "hw/misc/unimp.h"
26
+
#include "hw/riscv/boot.h"
27
+
#include "exec/address-spaces.h"
28
+
29
+
static const struct MemmapEntry {
30
+
hwaddr base;
31
+
hwaddr size;
32
+
} ibex_memmap[] = {
33
+
[IBEX_ROM] = { 0x00008000, 0xc000 },
34
+
[IBEX_RAM] = { 0x10000000, 0x10000 },
35
+
[IBEX_FLASH] = { 0x20000000, 0x80000 },
36
+
[IBEX_UART] = { 0x40000000, 0x10000 },
37
+
[IBEX_GPIO] = { 0x40010000, 0x10000 },
38
+
[IBEX_SPI] = { 0x40020000, 0x10000 },
39
+
[IBEX_FLASH_CTRL] = { 0x40030000, 0x10000 },
40
+
[IBEX_PINMUX] = { 0x40070000, 0x10000 },
41
+
[IBEX_RV_TIMER] = { 0x40080000, 0x10000 },
42
+
[IBEX_PLIC] = { 0x40090000, 0x10000 },
43
+
[IBEX_PWRMGR] = { 0x400A0000, 0x10000 },
44
+
[IBEX_RSTMGR] = { 0x400B0000, 0x10000 },
45
+
[IBEX_CLKMGR] = { 0x400C0000, 0x10000 },
46
+
[IBEX_AES] = { 0x40110000, 0x10000 },
47
+
[IBEX_HMAC] = { 0x40120000, 0x10000 },
48
+
[IBEX_ALERT_HANDLER] = { 0x40130000, 0x10000 },
49
+
[IBEX_NMI_GEN] = { 0x40140000, 0x10000 },
50
+
[IBEX_USBDEV] = { 0x40150000, 0x10000 },
51
+
[IBEX_PADCTRL] = { 0x40160000, 0x10000 }
52
+
};
53
+
54
+
static void riscv_opentitan_init(MachineState *machine)
55
+
{
56
+
const struct MemmapEntry *memmap = ibex_memmap;
57
+
OpenTitanState *s = g_new0(OpenTitanState, 1);
58
+
MemoryRegion *sys_mem = get_system_memory();
59
+
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
60
+
61
+
/* Initialize SoC */
62
+
object_initialize_child(OBJECT(machine), "soc", &s->soc,
63
+
sizeof(s->soc), TYPE_RISCV_IBEX_SOC,
64
+
&error_abort, NULL);
65
+
object_property_set_bool(OBJECT(&s->soc), true, "realized",
66
+
&error_abort);
67
+
68
+
memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
69
+
memmap[IBEX_RAM].size, &error_fatal);
70
+
memory_region_add_subregion(sys_mem,
71
+
memmap[IBEX_RAM].base, main_mem);
72
+
73
+
74
+
if (machine->firmware) {
75
+
riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
76
+
}
77
+
78
+
if (machine->kernel_filename) {
79
+
riscv_load_kernel(machine->kernel_filename, NULL);
80
+
}
81
+
}
82
+
83
+
static void riscv_opentitan_machine_init(MachineClass *mc)
84
+
{
85
+
mc->desc = "RISC-V Board compatible with OpenTitan";
86
+
mc->init = riscv_opentitan_init;
87
+
mc->max_cpus = 1;
88
+
mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
89
+
}
90
+
91
+
DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
92
+
93
+
static void riscv_lowrisc_ibex_soc_init(Object *obj)
94
+
{
95
+
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
96
+
97
+
object_initialize_child(obj, "cpus", &s->cpus,
98
+
sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
99
+
&error_abort, NULL);
100
+
}
101
+
102
+
static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
103
+
{
104
+
const struct MemmapEntry *memmap = ibex_memmap;
105
+
MachineState *ms = MACHINE(qdev_get_machine());
106
+
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
107
+
MemoryRegion *sys_mem = get_system_memory();
108
+
109
+
object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
110
+
&error_abort);
111
+
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
112
+
&error_abort);
113
+
object_property_set_bool(OBJECT(&s->cpus), true, "realized",
114
+
&error_abort);
115
+
116
+
/* Boot ROM */
117
+
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
118
+
memmap[IBEX_ROM].size, &error_fatal);
119
+
memory_region_add_subregion(sys_mem,
120
+
memmap[IBEX_ROM].base, &s->rom);
121
+
122
+
/* Flash memory */
123
+
memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
124
+
memmap[IBEX_FLASH].size, &error_fatal);
125
+
memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base,
126
+
&s->flash_mem);
127
+
128
+
create_unimplemented_device("riscv.lowrisc.ibex.uart",
129
+
memmap[IBEX_UART].base, memmap[IBEX_UART].size);
130
+
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
131
+
memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size);
132
+
create_unimplemented_device("riscv.lowrisc.ibex.spi",
133
+
memmap[IBEX_SPI].base, memmap[IBEX_SPI].size);
134
+
create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
135
+
memmap[IBEX_FLASH_CTRL].base, memmap[IBEX_FLASH_CTRL].size);
136
+
create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
137
+
memmap[IBEX_RV_TIMER].base, memmap[IBEX_RV_TIMER].size);
138
+
create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
139
+
memmap[IBEX_PWRMGR].base, memmap[IBEX_PWRMGR].size);
140
+
create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
141
+
memmap[IBEX_RSTMGR].base, memmap[IBEX_RSTMGR].size);
142
+
create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
143
+
memmap[IBEX_CLKMGR].base, memmap[IBEX_CLKMGR].size);
144
+
create_unimplemented_device("riscv.lowrisc.ibex.aes",
145
+
memmap[IBEX_AES].base, memmap[IBEX_AES].size);
146
+
create_unimplemented_device("riscv.lowrisc.ibex.hmac",
147
+
memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size);
148
+
create_unimplemented_device("riscv.lowrisc.ibex.plic",
149
+
memmap[IBEX_PLIC].base, memmap[IBEX_PLIC].size);
150
+
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
151
+
memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size);
152
+
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
153
+
memmap[IBEX_ALERT_HANDLER].base, memmap[IBEX_ALERT_HANDLER].size);
154
+
create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
155
+
memmap[IBEX_NMI_GEN].base, memmap[IBEX_NMI_GEN].size);
156
+
create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
157
+
memmap[IBEX_USBDEV].base, memmap[IBEX_USBDEV].size);
158
+
create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
159
+
memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
160
+
}
161
+
162
+
static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
163
+
{
164
+
DeviceClass *dc = DEVICE_CLASS(oc);
165
+
166
+
dc->realize = riscv_lowrisc_ibex_soc_realize;
167
+
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
168
+
dc->user_creatable = false;
169
+
}
170
+
171
+
static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {
172
+
.name = TYPE_RISCV_IBEX_SOC,
173
+
.parent = TYPE_DEVICE,
174
+
.instance_size = sizeof(LowRISCIbexSoCState),
175
+
.instance_init = riscv_lowrisc_ibex_soc_init,
176
+
.class_init = riscv_lowrisc_ibex_soc_class_init,
177
+
};
178
+
179
+
static void riscv_lowrisc_ibex_soc_register_types(void)
180
+
{
181
+
type_register_static(&riscv_lowrisc_ibex_soc_type_info);
182
+
}
183
+
184
+
type_init(riscv_lowrisc_ibex_soc_register_types)
+30
-11
hw/riscv/sifive_e.c
+30
-11
hw/riscv/sifive_e.c
···
79
79
{
80
80
const struct MemmapEntry *memmap = sifive_e_memmap;
81
81
82
-
SiFiveEState *s = g_new0(SiFiveEState, 1);
82
+
SiFiveEState *s = RISCV_E_MACHINE(machine);
83
83
MemoryRegion *sys_mem = get_system_memory();
84
84
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
85
85
int i;
···
114
114
riscv_load_kernel(machine->kernel_filename, NULL);
115
115
}
116
116
}
117
+
118
+
static void sifive_e_machine_instance_init(Object *obj)
119
+
{
120
+
}
121
+
122
+
static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
123
+
{
124
+
MachineClass *mc = MACHINE_CLASS(oc);
125
+
126
+
mc->desc = "RISC-V Board compatible with SiFive E SDK";
127
+
mc->init = riscv_sifive_e_init;
128
+
mc->max_cpus = 1;
129
+
mc->default_cpu_type = SIFIVE_E_CPU;
130
+
}
131
+
132
+
static const TypeInfo sifive_e_machine_typeinfo = {
133
+
.name = MACHINE_TYPE_NAME("sifive_e"),
134
+
.parent = TYPE_MACHINE,
135
+
.class_init = sifive_e_machine_class_init,
136
+
.instance_init = sifive_e_machine_instance_init,
137
+
.instance_size = sizeof(SiFiveEState),
138
+
};
139
+
140
+
static void sifive_e_machine_init_register_types(void)
141
+
{
142
+
type_register_static(&sifive_e_machine_typeinfo);
143
+
}
144
+
145
+
type_init(sifive_e_machine_init_register_types)
117
146
118
147
static void riscv_sifive_e_soc_init(Object *obj)
119
148
{
···
213
242
memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
214
243
&s->xip_mem);
215
244
}
216
-
217
-
static void riscv_sifive_e_machine_init(MachineClass *mc)
218
-
{
219
-
mc->desc = "RISC-V Board compatible with SiFive E SDK";
220
-
mc->init = riscv_sifive_e_init;
221
-
mc->max_cpus = 1;
222
-
mc->default_cpu_type = SIFIVE_E_CPU;
223
-
}
224
-
225
-
DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
226
245
227
246
static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
228
247
{
+12
-12
hw/riscv/sifive_u.c
+12
-12
hw/riscv/sifive_u.c
···
481
481
482
482
type_init(sifive_u_machine_init_register_types)
483
483
484
-
static void riscv_sifive_u_soc_init(Object *obj)
484
+
static void sifive_u_soc_instance_init(Object *obj)
485
485
{
486
486
MachineState *ms = MACHINE(qdev_get_machine());
487
487
SiFiveUSoCState *s = RISCV_U_SOC(obj);
···
520
520
TYPE_CADENCE_GEM);
521
521
}
522
522
523
-
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
523
+
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
524
524
{
525
525
MachineState *ms = MACHINE(qdev_get_machine());
526
526
SiFiveUSoCState *s = RISCV_U_SOC(dev);
···
635
635
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
636
636
}
637
637
638
-
static Property riscv_sifive_u_soc_props[] = {
638
+
static Property sifive_u_soc_props[] = {
639
639
DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
640
640
DEFINE_PROP_END_OF_LIST()
641
641
};
642
642
643
-
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
643
+
static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
644
644
{
645
645
DeviceClass *dc = DEVICE_CLASS(oc);
646
646
647
-
device_class_set_props(dc, riscv_sifive_u_soc_props);
648
-
dc->realize = riscv_sifive_u_soc_realize;
647
+
device_class_set_props(dc, sifive_u_soc_props);
648
+
dc->realize = sifive_u_soc_realize;
649
649
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
650
650
dc->user_creatable = false;
651
651
}
652
652
653
-
static const TypeInfo riscv_sifive_u_soc_type_info = {
653
+
static const TypeInfo sifive_u_soc_type_info = {
654
654
.name = TYPE_RISCV_U_SOC,
655
655
.parent = TYPE_DEVICE,
656
656
.instance_size = sizeof(SiFiveUSoCState),
657
-
.instance_init = riscv_sifive_u_soc_init,
658
-
.class_init = riscv_sifive_u_soc_class_init,
657
+
.instance_init = sifive_u_soc_instance_init,
658
+
.class_init = sifive_u_soc_class_init,
659
659
};
660
660
661
-
static void riscv_sifive_u_soc_register_types(void)
661
+
static void sifive_u_soc_register_types(void)
662
662
{
663
-
type_register_static(&riscv_sifive_u_soc_type_info);
663
+
type_register_static(&sifive_u_soc_type_info);
664
664
}
665
665
666
-
type_init(riscv_sifive_u_soc_register_types)
666
+
type_init(sifive_u_soc_register_types)
-217
hw/riscv/spike.c
-217
hw/riscv/spike.c
···
257
257
false);
258
258
}
259
259
260
-
static void spike_v1_10_0_board_init(MachineState *machine)
261
-
{
262
-
const struct MemmapEntry *memmap = spike_memmap;
263
-
264
-
SpikeState *s = g_new0(SpikeState, 1);
265
-
MemoryRegion *system_memory = get_system_memory();
266
-
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
267
-
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
268
-
int i;
269
-
unsigned int smp_cpus = machine->smp.cpus;
270
-
271
-
if (!qtest_enabled()) {
272
-
info_report("The Spike v1.10.0 machine has been deprecated. "
273
-
"Please use the generic spike machine and specify the ISA "
274
-
"versions using -cpu.");
275
-
}
276
-
277
-
/* Initialize SOC */
278
-
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
279
-
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
280
-
object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
281
-
&error_abort);
282
-
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
283
-
&error_abort);
284
-
object_property_set_bool(OBJECT(&s->soc), true, "realized",
285
-
&error_abort);
286
-
287
-
/* register system main memory (actual RAM) */
288
-
memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
289
-
machine->ram_size, &error_fatal);
290
-
memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
291
-
main_mem);
292
-
293
-
/* create device tree */
294
-
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
295
-
296
-
/* boot rom */
297
-
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
298
-
memmap[SPIKE_MROM].size, &error_fatal);
299
-
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
300
-
mask_rom);
301
-
302
-
if (machine->kernel_filename) {
303
-
riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
304
-
}
305
-
306
-
/* reset vector */
307
-
uint32_t reset_vec[8] = {
308
-
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
309
-
0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
310
-
0xf1402573, /* csrr a0, mhartid */
311
-
#if defined(TARGET_RISCV32)
312
-
0x0182a283, /* lw t0, 24(t0) */
313
-
#elif defined(TARGET_RISCV64)
314
-
0x0182b283, /* ld t0, 24(t0) */
315
-
#endif
316
-
0x00028067, /* jr t0 */
317
-
0x00000000,
318
-
memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
319
-
0x00000000,
320
-
/* dtb: */
321
-
};
322
-
323
-
/* copy in the reset vector in little_endian byte order */
324
-
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
325
-
reset_vec[i] = cpu_to_le32(reset_vec[i]);
326
-
}
327
-
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
328
-
memmap[SPIKE_MROM].base, &address_space_memory);
329
-
330
-
/* copy in the device tree */
331
-
if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
332
-
memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
333
-
error_report("not enough space to store device-tree");
334
-
exit(1);
335
-
}
336
-
qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
337
-
rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
338
-
memmap[SPIKE_MROM].base + sizeof(reset_vec),
339
-
&address_space_memory);
340
-
341
-
/* initialize HTIF using symbols found in load_kernel */
342
-
htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
343
-
344
-
/* Core Local Interruptor (timer and IPI) */
345
-
sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
346
-
smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
347
-
false);
348
-
}
349
-
350
-
static void spike_v1_09_1_board_init(MachineState *machine)
351
-
{
352
-
const struct MemmapEntry *memmap = spike_memmap;
353
-
354
-
SpikeState *s = g_new0(SpikeState, 1);
355
-
MemoryRegion *system_memory = get_system_memory();
356
-
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
357
-
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
358
-
int i;
359
-
unsigned int smp_cpus = machine->smp.cpus;
360
-
361
-
if (!qtest_enabled()) {
362
-
info_report("The Spike v1.09.1 machine has been deprecated. "
363
-
"Please use the generic spike machine and specify the ISA "
364
-
"versions using -cpu.");
365
-
}
366
-
367
-
/* Initialize SOC */
368
-
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
369
-
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
370
-
object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
371
-
&error_abort);
372
-
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
373
-
&error_abort);
374
-
object_property_set_bool(OBJECT(&s->soc), true, "realized",
375
-
&error_abort);
376
-
377
-
/* register system main memory (actual RAM) */
378
-
memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
379
-
machine->ram_size, &error_fatal);
380
-
memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
381
-
main_mem);
382
-
383
-
/* boot rom */
384
-
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
385
-
memmap[SPIKE_MROM].size, &error_fatal);
386
-
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
387
-
mask_rom);
388
-
389
-
if (machine->kernel_filename) {
390
-
riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
391
-
}
392
-
393
-
/* reset vector */
394
-
uint32_t reset_vec[8] = {
395
-
0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
396
-
0x00028067, /* jump to DRAM_BASE */
397
-
0x00000000, /* reserved */
398
-
memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
399
-
0, 0, 0, 0 /* trap vector */
400
-
};
401
-
402
-
/* part one of config string - before memory size specified */
403
-
const char *config_string_tmpl =
404
-
"platform {\n"
405
-
" vendor ucb;\n"
406
-
" arch spike;\n"
407
-
"};\n"
408
-
"rtc {\n"
409
-
" addr 0x%" PRIx64 "x;\n"
410
-
"};\n"
411
-
"ram {\n"
412
-
" 0 {\n"
413
-
" addr 0x%" PRIx64 "x;\n"
414
-
" size 0x%" PRIx64 "x;\n"
415
-
" };\n"
416
-
"};\n"
417
-
"core {\n"
418
-
" 0" " {\n"
419
-
" " "0 {\n"
420
-
" isa %s;\n"
421
-
" timecmp 0x%" PRIx64 "x;\n"
422
-
" ipi 0x%" PRIx64 "x;\n"
423
-
" };\n"
424
-
" };\n"
425
-
"};\n";
426
-
427
-
/* build config string with supplied memory size */
428
-
char *isa = riscv_isa_string(&s->soc.harts[0]);
429
-
char *config_string = g_strdup_printf(config_string_tmpl,
430
-
(uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
431
-
(uint64_t)memmap[SPIKE_DRAM].base,
432
-
(uint64_t)ram_size, isa,
433
-
(uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
434
-
(uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
435
-
g_free(isa);
436
-
size_t config_string_len = strlen(config_string);
437
-
438
-
/* copy in the reset vector in little_endian byte order */
439
-
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
440
-
reset_vec[i] = cpu_to_le32(reset_vec[i]);
441
-
}
442
-
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
443
-
memmap[SPIKE_MROM].base, &address_space_memory);
444
-
445
-
/* copy in the config string */
446
-
rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
447
-
memmap[SPIKE_MROM].base + sizeof(reset_vec),
448
-
&address_space_memory);
449
-
450
-
/* initialize HTIF using symbols found in load_kernel */
451
-
htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
452
-
453
-
/* Core Local Interruptor (timer and IPI) */
454
-
sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
455
-
smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
456
-
false);
457
-
458
-
g_free(config_string);
459
-
}
460
-
461
-
static void spike_v1_09_1_machine_init(MachineClass *mc)
462
-
{
463
-
mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
464
-
mc->init = spike_v1_09_1_board_init;
465
-
mc->max_cpus = 1;
466
-
}
467
-
468
-
static void spike_v1_10_0_machine_init(MachineClass *mc)
469
-
{
470
-
mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
471
-
mc->init = spike_v1_10_0_board_init;
472
-
mc->max_cpus = 1;
473
-
}
474
-
475
260
static void spike_machine_init(MachineClass *mc)
476
261
{
477
262
mc->desc = "RISC-V Spike Board";
···
481
266
mc->default_cpu_type = SPIKE_V1_10_0_CPU;
482
267
}
483
268
484
-
DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
485
-
DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
486
269
DEFINE_MACHINE("spike", spike_machine_init)
+10
-10
hw/riscv/virt.c
+10
-10
hw/riscv/virt.c
···
471
471
return dev;
472
472
}
473
473
474
-
static void riscv_virt_board_init(MachineState *machine)
474
+
static void virt_machine_init(MachineState *machine)
475
475
{
476
476
const struct MemmapEntry *memmap = virt_memmap;
477
477
RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
···
632
632
g_free(plic_hart_config);
633
633
}
634
634
635
-
static void riscv_virt_machine_instance_init(Object *obj)
635
+
static void virt_machine_instance_init(Object *obj)
636
636
{
637
637
}
638
638
639
-
static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
639
+
static void virt_machine_class_init(ObjectClass *oc, void *data)
640
640
{
641
641
MachineClass *mc = MACHINE_CLASS(oc);
642
642
643
643
mc->desc = "RISC-V VirtIO board";
644
-
mc->init = riscv_virt_board_init;
644
+
mc->init = virt_machine_init;
645
645
mc->max_cpus = 8;
646
646
mc->default_cpu_type = VIRT_CPU;
647
647
mc->pci_allow_0_address = true;
648
648
}
649
649
650
-
static const TypeInfo riscv_virt_machine_typeinfo = {
650
+
static const TypeInfo virt_machine_typeinfo = {
651
651
.name = MACHINE_TYPE_NAME("virt"),
652
652
.parent = TYPE_MACHINE,
653
-
.class_init = riscv_virt_machine_class_init,
654
-
.instance_init = riscv_virt_machine_instance_init,
653
+
.class_init = virt_machine_class_init,
654
+
.instance_init = virt_machine_instance_init,
655
655
.instance_size = sizeof(RISCVVirtState),
656
656
};
657
657
658
-
static void riscv_virt_machine_init_register_types(void)
658
+
static void virt_machine_init_register_types(void)
659
659
{
660
-
type_register_static(&riscv_virt_machine_typeinfo);
660
+
type_register_static(&virt_machine_typeinfo);
661
661
}
662
662
663
-
type_init(riscv_virt_machine_init_register_types)
663
+
type_init(virt_machine_init_register_types)
+1
include/hw/riscv/boot.h
+1
include/hw/riscv/boot.h
+68
include/hw/riscv/opentitan.h
+68
include/hw/riscv/opentitan.h
···
1
+
/*
2
+
* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3
+
*
4
+
* Copyright (c) 2020 Western Digital
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify it
7
+
* under the terms and conditions of the GNU General Public License,
8
+
* version 2 or later, as published by the Free Software Foundation.
9
+
*
10
+
* This program is distributed in the hope it will be useful, but WITHOUT
11
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
+
* more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License along with
16
+
* this program. If not, see <http://www.gnu.org/licenses/>.
17
+
*/
18
+
19
+
#ifndef HW_OPENTITAN_H
20
+
#define HW_OPENTITAN_H
21
+
22
+
#include "hw/riscv/riscv_hart.h"
23
+
24
+
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
25
+
#define RISCV_IBEX_SOC(obj) \
26
+
OBJECT_CHECK(LowRISCIbexSoCState, (obj), TYPE_RISCV_IBEX_SOC)
27
+
28
+
typedef struct LowRISCIbexSoCState {
29
+
/*< private >*/
30
+
SysBusDevice parent_obj;
31
+
32
+
/*< public >*/
33
+
RISCVHartArrayState cpus;
34
+
MemoryRegion flash_mem;
35
+
MemoryRegion rom;
36
+
} LowRISCIbexSoCState;
37
+
38
+
typedef struct OpenTitanState {
39
+
/*< private >*/
40
+
SysBusDevice parent_obj;
41
+
42
+
/*< public >*/
43
+
LowRISCIbexSoCState soc;
44
+
} OpenTitanState;
45
+
46
+
enum {
47
+
IBEX_ROM,
48
+
IBEX_RAM,
49
+
IBEX_FLASH,
50
+
IBEX_UART,
51
+
IBEX_GPIO,
52
+
IBEX_SPI,
53
+
IBEX_FLASH_CTRL,
54
+
IBEX_RV_TIMER,
55
+
IBEX_AES,
56
+
IBEX_HMAC,
57
+
IBEX_PLIC,
58
+
IBEX_PWRMGR,
59
+
IBEX_RSTMGR,
60
+
IBEX_CLKMGR,
61
+
IBEX_PINMUX,
62
+
IBEX_ALERT_HANDLER,
63
+
IBEX_NMI_GEN,
64
+
IBEX_USBDEV,
65
+
IBEX_PADCTRL,
66
+
};
67
+
68
+
#endif
+4
include/hw/riscv/sifive_e.h
+4
include/hw/riscv/sifive_e.h
+2
-4
include/hw/riscv/spike.h
+2
-4
include/hw/riscv/spike.h
···
39
39
};
40
40
41
41
#if defined(TARGET_RISCV32)
42
-
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
43
-
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
42
+
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
44
43
#elif defined(TARGET_RISCV64)
45
-
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
46
-
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
44
+
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
47
45
#endif
48
46
49
47
#endif
+11
-34
target/riscv/cpu.c
+11
-34
target/riscv/cpu.c
···
133
133
CPURISCVState *env = &RISCV_CPU(obj)->env;
134
134
/* We set this in the realise function */
135
135
set_misa(env, 0);
136
+
set_resetvec(env, DEFAULT_RSTVEC);
136
137
}
137
138
138
-
static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
139
+
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
139
140
{
140
141
CPURISCVState *env = &RISCV_CPU(obj)->env;
141
142
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
142
-
set_priv_version(env, PRIV_VERSION_1_09_1);
143
+
set_priv_version(env, PRIV_VERSION_1_10_0);
143
144
set_resetvec(env, DEFAULT_RSTVEC);
144
-
set_feature(env, RISCV_FEATURE_MMU);
145
-
set_feature(env, RISCV_FEATURE_PMP);
146
145
}
147
146
148
-
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
147
+
static void rv32imcu_nommu_cpu_init(Object *obj)
149
148
{
150
149
CPURISCVState *env = &RISCV_CPU(obj)->env;
151
-
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
150
+
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
152
151
set_priv_version(env, PRIV_VERSION_1_10_0);
153
-
set_resetvec(env, DEFAULT_RSTVEC);
154
-
set_feature(env, RISCV_FEATURE_MMU);
155
-
set_feature(env, RISCV_FEATURE_PMP);
152
+
set_resetvec(env, 0x8090);
153
+
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
156
154
}
157
155
158
156
static void rv32imacu_nommu_cpu_init(Object *obj)
···
161
159
set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
162
160
set_priv_version(env, PRIV_VERSION_1_10_0);
163
161
set_resetvec(env, DEFAULT_RSTVEC);
164
-
set_feature(env, RISCV_FEATURE_PMP);
162
+
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
165
163
}
166
164
167
165
static void rv32imafcu_nommu_cpu_init(Object *obj)
···
170
168
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
171
169
set_priv_version(env, PRIV_VERSION_1_10_0);
172
170
set_resetvec(env, DEFAULT_RSTVEC);
173
-
set_feature(env, RISCV_FEATURE_PMP);
171
+
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
174
172
}
175
173
176
174
#elif defined(TARGET_RISCV64)
···
180
178
CPURISCVState *env = &RISCV_CPU(obj)->env;
181
179
/* We set this in the realise function */
182
180
set_misa(env, 0);
183
-
}
184
-
185
-
static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
186
-
{
187
-
CPURISCVState *env = &RISCV_CPU(obj)->env;
188
-
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
189
-
set_priv_version(env, PRIV_VERSION_1_09_1);
190
181
set_resetvec(env, DEFAULT_RSTVEC);
191
-
set_feature(env, RISCV_FEATURE_MMU);
192
-
set_feature(env, RISCV_FEATURE_PMP);
193
182
}
194
183
195
184
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
···
198
187
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
199
188
set_priv_version(env, PRIV_VERSION_1_10_0);
200
189
set_resetvec(env, DEFAULT_RSTVEC);
201
-
set_feature(env, RISCV_FEATURE_MMU);
202
-
set_feature(env, RISCV_FEATURE_PMP);
203
190
}
204
191
205
192
static void rv64imacu_nommu_cpu_init(Object *obj)
···
208
195
set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
209
196
set_priv_version(env, PRIV_VERSION_1_10_0);
210
197
set_resetvec(env, DEFAULT_RSTVEC);
211
-
set_feature(env, RISCV_FEATURE_PMP);
198
+
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
212
199
}
213
200
214
201
#endif
···
388
375
priv_version = PRIV_VERSION_1_11_0;
389
376
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
390
377
priv_version = PRIV_VERSION_1_10_0;
391
-
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
392
-
priv_version = PRIV_VERSION_1_09_1;
393
378
} else {
394
379
error_setg(errp,
395
380
"Unsupported privilege spec version '%s'",
···
399
384
}
400
385
401
386
set_priv_version(env, priv_version);
402
-
set_resetvec(env, DEFAULT_RSTVEC);
403
387
404
388
if (cpu->cfg.mmu) {
405
389
set_feature(env, RISCV_FEATURE_MMU);
···
618
602
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
619
603
#if defined(TARGET_RISCV32)
620
604
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
605
+
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
621
606
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
622
607
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
623
608
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
624
-
/* Depreacted */
625
-
DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
626
-
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
627
-
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
628
609
#elif defined(TARGET_RISCV64)
629
610
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
630
611
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
631
612
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
632
-
/* Deprecated */
633
-
DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
634
-
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
635
-
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
636
613
#endif
637
614
};
638
615
+1
-8
target/riscv/cpu.h
+1
-8
target/riscv/cpu.h
···
35
35
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
36
36
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
37
37
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
38
+
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
38
39
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
39
40
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
40
41
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
41
42
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
42
43
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
43
-
/* Deprecated */
44
-
#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
45
-
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
46
-
#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
47
-
#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
48
-
#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
49
-
#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
50
44
51
45
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
52
46
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
···
80
74
RISCV_FEATURE_MISA
81
75
};
82
76
83
-
#define PRIV_VERSION_1_09_1 0x00010901
84
77
#define PRIV_VERSION_1_10_0 0x00011000
85
78
#define PRIV_VERSION_1_11_0 0x00011100
86
79
+29
-53
target/riscv/cpu_helper.c
+29
-53
target/riscv/cpu_helper.c
···
364
364
mxr = get_field(env->vsstatus, MSTATUS_MXR);
365
365
}
366
366
367
-
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
368
-
if (first_stage == true) {
369
-
if (use_background) {
370
-
base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
371
-
vm = get_field(env->vsatp, SATP_MODE);
372
-
} else {
373
-
base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
374
-
vm = get_field(env->satp, SATP_MODE);
375
-
}
376
-
widened = 0;
367
+
if (first_stage == true) {
368
+
if (use_background) {
369
+
base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
370
+
vm = get_field(env->vsatp, SATP_MODE);
377
371
} else {
378
-
base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
379
-
vm = get_field(env->hgatp, HGATP_MODE);
380
-
widened = 2;
381
-
}
382
-
sum = get_field(env->mstatus, MSTATUS_SUM);
383
-
switch (vm) {
384
-
case VM_1_10_SV32:
385
-
levels = 2; ptidxbits = 10; ptesize = 4; break;
386
-
case VM_1_10_SV39:
387
-
levels = 3; ptidxbits = 9; ptesize = 8; break;
388
-
case VM_1_10_SV48:
389
-
levels = 4; ptidxbits = 9; ptesize = 8; break;
390
-
case VM_1_10_SV57:
391
-
levels = 5; ptidxbits = 9; ptesize = 8; break;
392
-
case VM_1_10_MBARE:
393
-
*physical = addr;
394
-
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
395
-
return TRANSLATE_SUCCESS;
396
-
default:
397
-
g_assert_not_reached();
372
+
base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
373
+
vm = get_field(env->satp, SATP_MODE);
398
374
}
375
+
widened = 0;
399
376
} else {
400
-
widened = 0;
401
-
base = (hwaddr)(env->sptbr) << PGSHIFT;
402
-
sum = !get_field(env->mstatus, MSTATUS_PUM);
403
-
vm = get_field(env->mstatus, MSTATUS_VM);
404
-
switch (vm) {
405
-
case VM_1_09_SV32:
406
-
levels = 2; ptidxbits = 10; ptesize = 4; break;
407
-
case VM_1_09_SV39:
408
-
levels = 3; ptidxbits = 9; ptesize = 8; break;
409
-
case VM_1_09_SV48:
410
-
levels = 4; ptidxbits = 9; ptesize = 8; break;
411
-
case VM_1_09_MBARE:
412
-
*physical = addr;
413
-
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
414
-
return TRANSLATE_SUCCESS;
415
-
default:
416
-
g_assert_not_reached();
417
-
}
377
+
base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
378
+
vm = get_field(env->hgatp, HGATP_MODE);
379
+
widened = 2;
380
+
}
381
+
sum = get_field(env->mstatus, MSTATUS_SUM);
382
+
switch (vm) {
383
+
case VM_1_10_SV32:
384
+
levels = 2; ptidxbits = 10; ptesize = 4; break;
385
+
case VM_1_10_SV39:
386
+
levels = 3; ptidxbits = 9; ptesize = 8; break;
387
+
case VM_1_10_SV48:
388
+
levels = 4; ptidxbits = 9; ptesize = 8; break;
389
+
case VM_1_10_SV57:
390
+
levels = 5; ptidxbits = 9; ptesize = 8; break;
391
+
case VM_1_10_MBARE:
392
+
*physical = addr;
393
+
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
394
+
return TRANSLATE_SUCCESS;
395
+
default:
396
+
g_assert_not_reached();
418
397
}
419
398
420
399
CPUState *cs = env_cpu(env);
···
588
567
int page_fault_exceptions;
589
568
if (first_stage) {
590
569
page_fault_exceptions =
591
-
(env->priv_ver >= PRIV_VERSION_1_10_0) &&
592
570
get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
593
571
!pmp_violation;
594
572
} else {
···
941
919
}
942
920
943
921
s = env->mstatus;
944
-
s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
945
-
get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
922
+
s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
946
923
s = set_field(s, MSTATUS_SPP, env->priv);
947
924
s = set_field(s, MSTATUS_SIE, 0);
948
925
env->mstatus = s;
···
979
956
}
980
957
981
958
s = env->mstatus;
982
-
s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
983
-
get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
959
+
s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
984
960
s = set_field(s, MSTATUS_MPP, env->priv);
985
961
s = set_field(s, MSTATUS_MIE, 0);
986
962
env->mstatus = s;
+25
-113
target/riscv/csr.c
+25
-113
target/riscv/csr.c
···
58
58
#if !defined(CONFIG_USER_ONLY)
59
59
CPUState *cs = env_cpu(env);
60
60
RISCVCPU *cpu = RISCV_CPU(cs);
61
-
uint32_t ctr_en = ~0u;
62
61
63
62
if (!cpu->cfg.ext_counters) {
64
63
/* The Counters extensions is not enabled */
65
-
return -1;
66
-
}
67
-
68
-
/*
69
-
* The counters are always enabled at run time on newer priv specs, as the
70
-
* CSR has changed from controlling that the counters can be read to
71
-
* controlling that the counters increment.
72
-
*/
73
-
if (env->priv_ver > PRIV_VERSION_1_09_1) {
74
-
return 0;
75
-
}
76
-
77
-
if (env->priv < PRV_M) {
78
-
ctr_en &= env->mcounteren;
79
-
}
80
-
if (env->priv < PRV_S) {
81
-
ctr_en &= env->scounteren;
82
-
}
83
-
if (!(ctr_en & (1u << (csrno & 31)))) {
84
64
return -1;
85
65
}
86
66
#endif
···
293
273
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
294
274
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
295
275
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
296
-
static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE |
297
-
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
298
-
SSTATUS_SUM | SSTATUS_SD;
299
276
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
300
277
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
301
278
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
···
304
281
static const target_ulong vsip_writable_mask = MIP_VSSIP;
305
282
306
283
#if defined(TARGET_RISCV32)
307
-
static const char valid_vm_1_09[16] = {
308
-
[VM_1_09_MBARE] = 1,
309
-
[VM_1_09_SV32] = 1,
310
-
};
311
284
static const char valid_vm_1_10[16] = {
312
285
[VM_1_10_MBARE] = 1,
313
286
[VM_1_10_SV32] = 1
314
287
};
315
288
#elif defined(TARGET_RISCV64)
316
-
static const char valid_vm_1_09[16] = {
317
-
[VM_1_09_MBARE] = 1,
318
-
[VM_1_09_SV39] = 1,
319
-
[VM_1_09_SV48] = 1,
320
-
};
321
289
static const char valid_vm_1_10[16] = {
322
290
[VM_1_10_MBARE] = 1,
323
291
[VM_1_10_SV39] = 1,
···
347
315
348
316
static int validate_vm(CPURISCVState *env, target_ulong vm)
349
317
{
350
-
return (env->priv_ver >= PRIV_VERSION_1_10_0) ?
351
-
valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf];
318
+
return valid_vm_1_10[vm & 0xf];
352
319
}
353
320
354
321
static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
···
358
325
int dirty;
359
326
360
327
/* flush tlb on mstatus fields that affect VM */
361
-
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
362
-
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
363
-
MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
364
-
tlb_flush(env_cpu(env));
365
-
}
366
-
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
367
-
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
368
-
MSTATUS_MPP | MSTATUS_MXR |
369
-
(validate_vm(env, get_field(val, MSTATUS_VM)) ?
370
-
MSTATUS_VM : 0);
328
+
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
329
+
MSTATUS_MPRV | MSTATUS_SUM)) {
330
+
tlb_flush(env_cpu(env));
371
331
}
372
-
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
373
-
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
374
-
MSTATUS_MPRV | MSTATUS_SUM)) {
375
-
tlb_flush(env_cpu(env));
376
-
}
377
-
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
378
-
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
379
-
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
380
-
MSTATUS_TW;
332
+
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
333
+
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
334
+
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
335
+
MSTATUS_TW;
381
336
#if defined(TARGET_RISCV64)
382
-
/*
383
-
* RV32: MPV and MTL are not in mstatus. The current plan is to
384
-
* add them to mstatush. For now, we just don't support it.
385
-
*/
386
-
mask |= MSTATUS_MTL | MSTATUS_MPV;
337
+
/*
338
+
* RV32: MPV and MTL are not in mstatus. The current plan is to
339
+
* add them to mstatush. For now, we just don't support it.
340
+
*/
341
+
mask |= MSTATUS_MTL | MSTATUS_MPV;
387
342
#endif
388
-
}
389
343
390
344
mstatus = (mstatus & ~mask) | (val & mask);
391
345
···
534
488
535
489
static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
536
490
{
537
-
if (env->priv_ver < PRIV_VERSION_1_10_0) {
538
-
return -1;
539
-
}
540
491
*val = env->mcounteren;
541
492
return 0;
542
493
}
543
494
544
495
static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
545
496
{
546
-
if (env->priv_ver < PRIV_VERSION_1_10_0) {
547
-
return -1;
548
-
}
549
497
env->mcounteren = val;
550
498
return 0;
551
499
}
···
553
501
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
554
502
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
555
503
{
556
-
if (env->priv_ver > PRIV_VERSION_1_09_1
557
-
&& env->priv_ver < PRIV_VERSION_1_11_0) {
504
+
if (env->priv_ver < PRIV_VERSION_1_11_0) {
558
505
return -1;
559
506
}
560
507
*val = env->mcounteren;
···
564
511
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
565
512
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
566
513
{
567
-
if (env->priv_ver > PRIV_VERSION_1_09_1
568
-
&& env->priv_ver < PRIV_VERSION_1_11_0) {
514
+
if (env->priv_ver < PRIV_VERSION_1_11_0) {
569
515
return -1;
570
516
}
571
517
env->mcounteren = val;
572
-
return 0;
573
-
}
574
-
575
-
static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val)
576
-
{
577
-
if (env->priv_ver > PRIV_VERSION_1_09_1) {
578
-
return -1;
579
-
}
580
-
*val = env->scounteren;
581
-
return 0;
582
-
}
583
-
584
-
static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val)
585
-
{
586
-
if (env->priv_ver > PRIV_VERSION_1_09_1) {
587
-
return -1;
588
-
}
589
-
env->scounteren = val;
590
518
return 0;
591
519
}
592
520
···
663
591
/* Supervisor Trap Setup */
664
592
static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
665
593
{
666
-
target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
667
-
sstatus_v1_10_mask : sstatus_v1_9_mask);
594
+
target_ulong mask = (sstatus_v1_10_mask);
668
595
*val = env->mstatus & mask;
669
596
return 0;
670
597
}
671
598
672
599
static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
673
600
{
674
-
target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
675
-
sstatus_v1_10_mask : sstatus_v1_9_mask);
601
+
target_ulong mask = (sstatus_v1_10_mask);
676
602
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
677
603
return write_mstatus(env, CSR_MSTATUS, newval);
678
604
}
···
722
648
723
649
static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
724
650
{
725
-
if (env->priv_ver < PRIV_VERSION_1_10_0) {
726
-
return -1;
727
-
}
728
651
*val = env->scounteren;
729
652
return 0;
730
653
}
731
654
732
655
static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
733
656
{
734
-
if (env->priv_ver < PRIV_VERSION_1_10_0) {
735
-
return -1;
736
-
}
737
657
env->scounteren = val;
738
658
return 0;
739
659
}
···
812
732
{
813
733
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
814
734
*val = 0;
815
-
} else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
816
-
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
817
-
return -1;
818
-
} else {
819
-
*val = env->satp;
820
-
}
735
+
return 0;
736
+
}
737
+
738
+
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
739
+
return -1;
821
740
} else {
822
-
*val = env->sptbr;
741
+
*val = env->satp;
823
742
}
743
+
824
744
return 0;
825
745
}
826
746
···
829
749
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
830
750
return 0;
831
751
}
832
-
if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) {
833
-
tlb_flush(env_cpu(env));
834
-
env->sptbr = val & (((target_ulong)
835
-
1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1);
836
-
}
837
-
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
838
-
validate_vm(env, get_field(val, SATP_MODE)) &&
752
+
if (validate_vm(env, get_field(val, SATP_MODE)) &&
839
753
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
840
754
{
841
755
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
···
1313
1227
[CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
1314
1228
#endif
1315
1229
1316
-
/* Legacy Counter Setup (priv v1.9.1) */
1317
-
[CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren },
1318
1230
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
1319
1231
1320
1232
/* Machine Trap Handling */
+4
-14
target/riscv/insn_trans/trans_privileged.inc.c
+4
-14
target/riscv/insn_trans/trans_privileged.inc.c
···
85
85
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
86
86
{
87
87
#ifndef CONFIG_USER_ONLY
88
-
if (ctx->priv_ver >= PRIV_VERSION_1_10_0) {
89
-
gen_helper_tlb_flush(cpu_env);
90
-
return true;
91
-
}
88
+
gen_helper_tlb_flush(cpu_env);
89
+
return true;
92
90
#endif
93
91
return false;
94
92
}
95
93
96
94
static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
97
95
{
98
-
#ifndef CONFIG_USER_ONLY
99
-
if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
100
-
gen_helper_tlb_flush(cpu_env);
101
-
return true;
102
-
}
103
-
#endif
104
96
return false;
105
97
}
106
98
107
99
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
108
100
{
109
101
#ifndef CONFIG_USER_ONLY
110
-
if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
111
-
has_ext(ctx, RVH)) {
102
+
if (has_ext(ctx, RVH)) {
112
103
/* Hpervisor extensions exist */
113
104
/*
114
105
* if (env->priv == PRV_M ||
···
127
118
static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
128
119
{
129
120
#ifndef CONFIG_USER_ONLY
130
-
if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
131
-
has_ext(ctx, RVH)) {
121
+
if (has_ext(ctx, RVH)) {
132
122
/* Hpervisor extensions exist */
133
123
/*
134
124
* if (env->priv == PRV_M ||
-5
target/riscv/monitor.c
-5
target/riscv/monitor.c
···
215
215
return;
216
216
}
217
217
218
-
if (env->priv_ver < PRIV_VERSION_1_10_0) {
219
-
monitor_printf(mon, "Privileged mode < 1.10 unsupported\n");
220
-
return;
221
-
}
222
-
223
218
if (!(env->satp & SATP_MODE)) {
224
219
monitor_printf(mon, "No translation or protection\n");
225
220
return;
+5
-12
target/riscv/op_helper.c
+5
-12
target/riscv/op_helper.c
···
84
84
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
85
85
}
86
86
87
-
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
88
-
get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
87
+
if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
89
88
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
90
89
}
91
90
···
119
118
} else {
120
119
prev_priv = get_field(mstatus, MSTATUS_SPP);
121
120
122
-
mstatus = set_field(mstatus,
123
-
env->priv_ver >= PRIV_VERSION_1_10_0 ?
124
-
MSTATUS_SIE : MSTATUS_UIE << prev_priv,
125
-
get_field(mstatus, MSTATUS_SPIE));
121
+
mstatus = set_field(mstatus, MSTATUS_SIE,
122
+
get_field(mstatus, MSTATUS_SPIE));
126
123
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
127
124
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
128
125
env->mstatus = mstatus;
···
147
144
target_ulong mstatus = env->mstatus;
148
145
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
149
146
target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
150
-
mstatus = set_field(mstatus,
151
-
env->priv_ver >= PRIV_VERSION_1_10_0 ?
152
-
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
153
-
get_field(mstatus, MSTATUS_MPIE));
147
+
mstatus = set_field(mstatus, MSTATUS_MIE,
148
+
get_field(mstatus, MSTATUS_MPIE));
154
149
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
155
150
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
156
151
#ifdef TARGET_RISCV32
···
177
172
CPUState *cs = env_cpu(env);
178
173
179
174
if ((env->priv == PRV_S &&
180
-
env->priv_ver >= PRIV_VERSION_1_10_0 &&
181
175
get_field(env->mstatus, MSTATUS_TW)) ||
182
176
riscv_cpu_virt_enabled(env)) {
183
177
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
···
193
187
CPUState *cs = env_cpu(env);
194
188
if (!(env->priv >= PRV_S) ||
195
189
(env->priv == PRV_S &&
196
-
env->priv_ver >= PRIV_VERSION_1_10_0 &&
197
190
get_field(env->mstatus, MSTATUS_TVM))) {
198
191
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
199
192
} else {
+2
-2
tests/qtest/machine-none-test.c
+2
-2
tests/qtest/machine-none-test.c