jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
Use the always-compiled trace events, remove the now unused
RISCV_DEBUG_PMP definition.
Note pmpaddr_csr_read() could previously do out-of-bound accesses
passing addr_index >= MAX_RISCV_PMPS.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
authored by
Philippe Mathieu-Daudé
and committed by
Palmer Dabbelt
6591efb5
0b84b662
+16
-21
+10
-21
target/riscv/pmp.c
+10
-21
target/riscv/pmp.c
···
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "cpu.h"
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-
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#define RISCV_DEBUG_PMP 0
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#define PMP_DEBUG(fmt, ...) \
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do { \
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if (RISCV_DEBUG_PMP) { \
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qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\
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} \
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} while (0)
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#include "trace.h"
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static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
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uint8_t val);
···
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int i;
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uint8_t cfg_val;
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PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,
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env->mhartid, reg_index, val);
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trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
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if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
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qemu_log_mask(LOG_GUEST_ERROR,
···
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val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
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cfg_val |= (val << (i * 8));
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}
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PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,
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env->mhartid, reg_index, cfg_val);
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trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
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return cfg_val;
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}
···
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void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
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target_ulong val)
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{
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PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,
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env->mhartid, addr_index, val);
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-
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trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
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if (addr_index < MAX_RISCV_PMPS) {
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if (!pmp_is_locked(env, addr_index)) {
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env->pmp_state.pmp[addr_index].addr_reg = val;
···
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*/
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target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
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{
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PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,
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env->mhartid, addr_index,
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env->pmp_state.pmp[addr_index].addr_reg);
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target_ulong val = 0;
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if (addr_index < MAX_RISCV_PMPS) {
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return env->pmp_state.pmp[addr_index].addr_reg;
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val = env->pmp_state.pmp[addr_index].addr_reg;
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trace_pmpaddr_csr_read(env->mhartid, addr_index, val);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ignoring pmpaddr read - out of bounds\n");
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return 0;
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}
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return val;
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}
+6
target/riscv/trace-events
+6
target/riscv/trace-events
···
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1
# target/riscv/cpu_helper.c
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riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"
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# pmp.c
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pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64
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pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
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pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
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pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64