jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
arm_gicv3: Fix ICC_BPR1 reset value when EL3 not implemented
If EL3 is not implemented (ie only one security state) then the
one and only ICC_BPR1 register behaves like the Non-secure
ICC_BPR1 in an EL3-present configuration. In particular, its
reset value is GIC_MIN_BPR_NS, not GIC_MIN_BPR.
Correct the erroneous reset value; this fixes a problem where
we might hit the assert added in commit a89ff39ee901.
Reported-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1496849369-30282-1-git-send-email-peter.maydell@linaro.org
+1
-5
+1
-5
hw/intc/arm_gicv3_cpuif.c
+1
-5
hw/intc/arm_gicv3_cpuif.c
···
2039
2039
cs->icc_pmr_el1 = 0;
2040
2040
cs->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
2041
2041
cs->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
2042
-
if (arm_feature(env, ARM_FEATURE_EL3)) {
2043
-
cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
2044
-
} else {
2045
-
cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
2046
-
}
2042
+
cs->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR_NS;
2047
2043
memset(cs->icc_apr, 0, sizeof(cs->icc_apr));
2048
2044
memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen));
2049
2045
cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V |