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jcs.org/2018/11/12/vfio
linux-user/ppc: Fix padding in mcontext_t for ppc64
The padding that was added in 95cda4c44ee was added to a union,
and so it had no effect. This fixes misalignment errors detected
by clang sanitizers for ppc64 and ppc64le.
In addition, only ppc64 allocates space for VSX registers, so do
not save them for ppc32. The kernel only has references to
CONFIG_SPE in signal_32.c, so do not attempt to save them for ppc64.
Fixes: 95cda4c44ee
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200407032105.26711-1-richard.henderson@linaro.org>
Acked-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
authored by
Richard Henderson
and committed by
David Gibson
5da5f47e
20038cd7
+29
-40
+29
-40
linux-user/ppc/signal.c
+29
-40
linux-user/ppc/signal.c
···
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target_ulong mc_gregs[48];
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/* Includes fpscr. */
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uint64_t mc_fregs[33];
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+
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#if defined(TARGET_PPC64)
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/* Pointer to the vector regs */
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target_ulong v_regs;
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/*
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* On ppc64, this mcontext structure is naturally *unaligned*,
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* or rather it is aligned on a 8 bytes boundary but not on
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* a 16 byte boundary. This pad fixes it up. This is why we
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* cannot use ppc_avr_t, which would force alignment. This is
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* also why the vector regs are referenced in the ABI by the
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* v_regs pointer above so any amount of padding can be added here.
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*/
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target_ulong pad;
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/* VSCR and VRSAVE are saved separately. Also reserve space for VSX. */
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struct {
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uint64_t altivec[34 + 16][2];
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} mc_vregs;
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#else
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target_ulong mc_pad[2];
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-
#endif
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+
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/* We need to handle Altivec and SPE at the same time, which no
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kernel needs to do. Fortunately, the kernel defines this bit to
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be Altivec-register-large all the time, rather than trying to
···
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union {
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/* SPE vector registers. One extra for SPEFSCR. */
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uint32_t spe[33];
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/* Altivec vector registers. The packing of VSCR and VRSAVE
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varies depending on whether we're PPC64 or not: PPC64 splits
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-
them apart; PPC32 stuffs them together.
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We also need to account for the VSX registers on PPC64
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*/
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-
#if defined(TARGET_PPC64)
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-
#define QEMU_NVRREG (34 + 16)
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/* On ppc64, this mcontext structure is naturally *unaligned*,
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* or rather it is aligned on a 8 bytes boundary but not on
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* a 16 bytes one. This pad fixes it up. This is also why the
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* vector regs are referenced by the v_regs pointer above so
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* any amount of padding can be added here
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/*
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* Altivec vector registers. One extra for VRSAVE.
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* On ppc32, we are already aligned to 16 bytes. We could
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* use ppc_avr_t, but choose to share the same type as ppc64.
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*/
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-
target_ulong pad;
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-
#else
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-
/* On ppc32, we are already aligned to 16 bytes */
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-
#define QEMU_NVRREG 33
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uint64_t altivec[33][2];
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} mc_vregs;
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#endif
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/* We cannot use ppc_avr_t here as we do *not* want the implied
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* 16-bytes alignment that would result from it. This would have
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* the effect of making the whole struct target_mcontext aligned
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* which breaks the layout of struct target_ucontext on ppc64.
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*/
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uint64_t altivec[QEMU_NVRREG][2];
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-
#undef QEMU_NVRREG
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-
} mc_vregs;
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};
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/* See arch/powerpc/include/asm/sigcontext.h. */
···
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__put_user((uint32_t)env->spr[SPR_VRSAVE], vrsave);
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}
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+
#if defined(TARGET_PPC64)
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/* Save VSX second halves */
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if (env->insns_flags2 & PPC2_VSX) {
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uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
···
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__put_user(*vsrl, &vsregs[i]);
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}
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}
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+
#endif
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/* Save floating point registers. */
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if (env->insns_flags & PPC_FLOAT) {
···
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__put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]);
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}
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+
#if !defined(TARGET_PPC64)
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/* Save SPE registers. The kernel only saves the high half. */
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if (env->insns_flags & PPC_SPE) {
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-
#if defined(TARGET_PPC64)
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-
for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
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-
__put_user(env->gpr[i] >> 32, &frame->mc_vregs.spe[i]);
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-
}
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-
#else
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for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
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__put_user(env->gprh[i], &frame->mc_vregs.spe[i]);
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}
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-
#endif
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/* Set MSR_SPE in the saved MSR value to indicate that
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frame->mc_vregs contains valid data. */
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msr |= MSR_SPE;
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__put_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
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}
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+
#endif
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/* Store MSR. */
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__put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]);
···
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__get_user(env->spr[SPR_VRSAVE], vrsave);
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}
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+
#if defined(TARGET_PPC64)
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/* Restore VSX second halves */
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if (env->insns_flags2 & PPC2_VSX) {
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uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
···
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__get_user(*vsrl, &vsregs[i]);
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}
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}
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+
#endif
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/* Restore floating point registers. */
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if (env->insns_flags & PPC_FLOAT) {
···
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env->fpscr = (uint32_t) fpscr;
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}
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#if !defined(TARGET_PPC64)
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/* Save SPE registers. The kernel only saves the high half. */
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if (env->insns_flags & PPC_SPE) {
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-
#if defined(TARGET_PPC64)
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-
for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
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uint32_t hi;
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__get_user(hi, &frame->mc_vregs.spe[i]);
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env->gpr[i] = ((uint64_t)hi << 32) | ((uint32_t) env->gpr[i]);
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}
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#else
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for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
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__get_user(env->gprh[i], &frame->mc_vregs.spe[i]);
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}
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-
#endif
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__get_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
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}
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+
#endif
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}
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#if !defined(TARGET_PPC64)