jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
s390x/gdb: support reading/writing of control registers
Let's support reading and writing of control registers for kvm and tcg.
We have to take care of flushing the tlb (tcg) and pushing the changed
registers into kvm.
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
authored by
David Hildenbrand
and committed by
Cornelia Huck
5b9f6345
c0194a00
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-1
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configure
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configure
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echo "TARGET_ABI32=y" >> $config_target_mak
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;;
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s390x)
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-
gdb_xml_files="s390x-core64.xml s390-acr.xml s390-fpr.xml s390-vx.xml"
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gdb_xml_files="s390x-core64.xml s390-acr.xml s390-fpr.xml s390-vx.xml s390-cr.xml"
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;;
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tricore)
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;;
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gdb-xml/s390-cr.xml
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gdb-xml/s390-cr.xml
···
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<?xml version="1.0"?>
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<!-- Copyright 2015 IBM Corp.
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This work is licensed under the terms of the GNU GPL, version 2 or
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(at your option) any later version. See the COPYING file in the
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top-level directory. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.s390.cr">
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<reg name="cr0" bitsize="64" type="uint64" group="control"/>
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<reg name="cr1" bitsize="64" type="uint64" group="control"/>
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<reg name="cr2" bitsize="64" type="uint64" group="control"/>
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<reg name="cr3" bitsize="64" type="uint64" group="control"/>
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<reg name="cr4" bitsize="64" type="uint64" group="control"/>
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<reg name="cr5" bitsize="64" type="uint64" group="control"/>
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<reg name="cr6" bitsize="64" type="uint64" group="control"/>
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<reg name="cr7" bitsize="64" type="uint64" group="control"/>
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<reg name="cr8" bitsize="64" type="uint64" group="control"/>
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<reg name="cr9" bitsize="64" type="uint64" group="control"/>
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<reg name="cr10" bitsize="64" type="uint64" group="control"/>
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<reg name="cr11" bitsize="64" type="uint64" group="control"/>
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<reg name="cr12" bitsize="64" type="uint64" group="control"/>
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<reg name="cr13" bitsize="64" type="uint64" group="control"/>
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<reg name="cr14" bitsize="64" type="uint64" group="control"/>
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<reg name="cr15" bitsize="64" type="uint64" group="control"/>
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</feature>
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target-s390x/gdbstub.c
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target-s390x/gdbstub.c
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}
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}
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/* the values represent the positions in s390-cr.xml */
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#define S390_C0_REGNUM 0
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#define S390_C15_REGNUM 15
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/* total number of registers in s390-cr.xml */
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#define S390_NUM_C_REGS 16
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#ifndef CONFIG_USER_ONLY
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static int cpu_read_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
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{
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switch (n) {
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case S390_C0_REGNUM ... S390_C15_REGNUM:
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return gdb_get_regl(mem_buf, env->cregs[n]);
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default:
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return 0;
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}
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}
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static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
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{
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switch (n) {
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case S390_C0_REGNUM ... S390_C15_REGNUM:
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env->cregs[n] = ldtul_p(mem_buf);
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if (tcg_enabled()) {
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tlb_flush(ENV_GET_CPU(env), 1);
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}
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cpu_synchronize_post_init(ENV_GET_CPU(env));
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return 8;
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default:
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return 0;
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}
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}
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#endif
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void s390_cpu_gdb_init(CPUState *cs)
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{
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gdb_register_coprocessor(cs, cpu_read_ac_reg,
···
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gdb_register_coprocessor(cs, cpu_read_vreg,
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cpu_write_vreg,
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S390_NUM_VREGS, "s390-vx.xml", 0);
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#ifndef CONFIG_USER_ONLY
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gdb_register_coprocessor(cs, cpu_read_c_reg,
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cpu_write_c_reg,
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S390_NUM_C_REGS, "s390-cr.xml", 0);
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#endif
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}