jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging
target/xtensa fixes for 5.1:
- fix access to special registers missing in the core configuration;
- fix simcall opcode behavior for new hardware;
- drop gen_io_end call from xtensa translator.
# gpg: Signature made Thu 25 Jun 2020 09:08:58 BST
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044
* remotes/xtensa/tags/20200625-xtensa:
target/xtensa: drop gen_io_end call
target/xtensa: fix simcall for newer hardware
target/xtensa: fetch HW version from configuration overlay
target/xtensa: work around missing SR definitions
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+46
-23
+1
target/xtensa/cpu.h
+1
target/xtensa/cpu.h
+5
-3
target/xtensa/overlay_tool.h
+5
-3
target/xtensa/overlay_tool.h
···
60
60
#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
61
61
#endif
62
62
63
-
#ifndef XCHAL_HW_MIN_VERSION
64
-
#define XCHAL_HW_MIN_VERSION 0
63
+
#ifndef XCHAL_HW_VERSION
64
+
#define XCHAL_HW_VERSION (XCHAL_HW_VERSION_MAJOR * 100 \
65
+
+ XCHAL_HW_VERSION_MINOR)
65
66
#endif
66
67
67
68
#ifndef XCHAL_LOOP_BUFFER_SIZE
···
100
101
XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
101
102
XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
102
103
XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
103
-
XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000) || \
104
+
XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
104
105
XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \
105
106
XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
106
107
/* Interrupts and exceptions */ \
···
498
499
}
499
500
500
501
#define CONFIG_SECTION \
502
+
.hw_version = XCHAL_HW_VERSION, \
501
503
.configid = { \
502
504
XCHAL_HW_CONFIGID0, \
503
505
XCHAL_HW_CONFIGID1, \
+40
-20
target/xtensa/translate.c
+40
-20
target/xtensa/translate.c
···
595
595
gen_io_start();
596
596
}
597
597
gen_helper_check_interrupts(cpu_env);
598
-
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
599
-
gen_io_end();
600
-
}
601
598
}
602
599
#endif
603
600
if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
···
2191
2188
static void translate_rsr(DisasContext *dc, const OpcodeArg arg[],
2192
2189
const uint32_t par[])
2193
2190
{
2194
-
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2191
+
if (sr_name[par[0]]) {
2192
+
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2193
+
} else {
2194
+
tcg_gen_movi_i32(arg[0].out, 0);
2195
+
}
2195
2196
}
2196
2197
2197
2198
static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
···
2363
2364
#ifdef CONFIG_USER_ONLY
2364
2365
bool ill = true;
2365
2366
#else
2366
-
bool ill = !semihosting_enabled();
2367
+
/* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
2368
+
bool ill = dc->config->hw_version <= 250002 && !semihosting_enabled();
2367
2369
#endif
2368
-
if (ill) {
2370
+
if (ill || !semihosting_enabled()) {
2369
2371
qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
2370
2372
}
2371
2373
return ill;
···
2375
2377
const uint32_t par[])
2376
2378
{
2377
2379
#ifndef CONFIG_USER_ONLY
2378
-
gen_helper_simcall(cpu_env);
2380
+
if (semihosting_enabled()) {
2381
+
gen_helper_simcall(cpu_env);
2382
+
}
2379
2383
#endif
2380
2384
}
2381
2385
···
2563
2567
static void translate_wsr(DisasContext *dc, const OpcodeArg arg[],
2564
2568
const uint32_t par[])
2565
2569
{
2566
-
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2570
+
if (sr_name[par[0]]) {
2571
+
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2572
+
}
2567
2573
}
2568
2574
2569
2575
static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[],
2570
2576
const uint32_t par[])
2571
2577
{
2572
-
tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
2578
+
if (sr_name[par[0]]) {
2579
+
tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
2580
+
}
2573
2581
}
2574
2582
2575
2583
static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[],
···
2775
2783
static void translate_xsr(DisasContext *dc, const OpcodeArg arg[],
2776
2784
const uint32_t par[])
2777
2785
{
2778
-
TCGv_i32 tmp = tcg_temp_new_i32();
2786
+
if (sr_name[par[0]]) {
2787
+
TCGv_i32 tmp = tcg_temp_new_i32();
2779
2788
2780
-
tcg_gen_mov_i32(tmp, arg[0].in);
2781
-
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2782
-
tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
2783
-
tcg_temp_free(tmp);
2789
+
tcg_gen_mov_i32(tmp, arg[0].in);
2790
+
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2791
+
tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
2792
+
tcg_temp_free(tmp);
2793
+
} else {
2794
+
tcg_gen_movi_i32(arg[0].out, 0);
2795
+
}
2784
2796
}
2785
2797
2786
2798
static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[],
2787
2799
const uint32_t par[])
2788
2800
{
2789
-
TCGv_i32 tmp = tcg_temp_new_i32();
2801
+
if (sr_name[par[0]]) {
2802
+
TCGv_i32 tmp = tcg_temp_new_i32();
2790
2803
2791
-
tcg_gen_mov_i32(tmp, arg[0].in);
2792
-
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2793
-
tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
2794
-
tcg_temp_free(tmp);
2804
+
tcg_gen_mov_i32(tmp, arg[0].in);
2805
+
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2806
+
tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
2807
+
tcg_temp_free(tmp);
2808
+
} else {
2809
+
tcg_gen_movi_i32(arg[0].out, 0);
2810
+
}
2795
2811
}
2796
2812
2797
2813
static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
···
2819
2835
{ \
2820
2836
TCGv_i32 tmp = tcg_temp_new_i32(); \
2821
2837
\
2822
-
tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
2838
+
if (sr_name[par[0]]) { \
2839
+
tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
2840
+
} else { \
2841
+
tcg_gen_movi_i32(tmp, 0); \
2842
+
} \
2823
2843
translate_wsr_##name(dc, arg, par); \
2824
2844
tcg_gen_mov_i32(arg[0].out, tmp); \
2825
2845
tcg_temp_free(tmp); \