hw/arm/stellaris: Implement watchdog timer

qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

Implement the watchdog timer for the stellaris boards.
This device is a close variant of the CMSDK APB watchdog
device, so we can model it by subclassing that device and
tweaking the behaviour of some of its registers.

Signed-off-by: Michel Heily <michelheily@gmail.com>
Reviewed-by: Peter Maydell <petser.maydell@linaro.org>
[PMM: rewrote commit message, fixed a few checkpatch nits,
added comment giving the URL of the spec for the Stellaris
variant of the watchdog device]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

authored by

Michel Heily and committed by

Peter Maydell 7 years ago 566528f8 50a17297

+100 -4

3 changed files

expand all

arm

stellaris.c

watchdog

cmsdk-apb-watchdog.c

include

watchdog

cmsdk-apb-watchdog.h

+20 -2

hw/arm/stellaris.c

··· 22 22 #include "sysemu/sysemu.h" 23 23 #include "hw/arm/armv7m.h" 24 24 #include "hw/char/pl011.h" 25 + #include "hw/watchdog/cmsdk-apb-watchdog.h" 25 26 #include "hw/misc/unimp.h" 26 27 #include "cpu.h" 27 28 ··· 1243 1244 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) 1244 1245 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 1245 1246 * 1246 - * 40000000 wdtimer (unimplemented) 1247 + * 40000000 wdtimer 1247 1248 * 40002000 i2c (unimplemented) 1248 1249 * 40004000 GPIO 1249 1250 * 40005000 GPIO ··· 1338 1339 stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), 1339 1340 board, nd_table[0].macaddr.a); 1340 1341 1342 + 1343 + if (board->dc1 & (1 << 3)) { /* watchdog present */ 1344 + dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG); 1345 + 1346 + /* system_clock_scale is valid now */ 1347 + uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; 1348 + qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); 1349 + 1350 + qdev_init_nofail(dev); 1351 + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1352 + 0, 1353 + 0x40000000u); 1354 + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1355 + 0, 1356 + qdev_get_gpio_in(nvic, 18)); 1357 + } 1358 + 1359 + 1341 1360 for (i = 0; i < 7; i++) { 1342 1361 if (board->dc4 & (1 << i)) { 1343 1362 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], ··· 1431 1450 /* Add dummy regions for the devices we don't implement yet, 1432 1451 * so guest accesses don't cause unlogged crashes. 1433 1452 */ 1434 - create_unimplemented_device("wdtimer", 0x40000000, 0x1000); 1435 1453 create_unimplemented_device("i2c-0", 0x40002000, 0x1000); 1436 1454 create_unimplemented_device("i2c-2", 0x40021000, 0x1000); 1437 1455 create_unimplemented_device("PWM", 0x40028000, 0x1000);

+72 -2

hw/watchdog/cmsdk-apb-watchdog.c

··· 14 14 * System Design Kit (CMSDK) and documented in the Cortex-M System 15 15 * Design Kit Technical Reference Manual (ARM DDI0479C): 16 16 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit 17 + * 18 + * We also support the variant of this device found in the TI 19 + * Stellaris/Luminary boards and documented in: 20 + * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf 17 21 */ 18 22 19 23 #include "qemu/osdep.h" ··· 37 41 REG32(WDOGRIS, 0x10) 38 42 FIELD(WDOGRIS, INT, 0, 1) 39 43 REG32(WDOGMIS, 0x14) 44 + REG32(WDOGTEST, 0x418) /* only in Stellaris/Luminary version of the device */ 40 45 REG32(WDOGLOCK, 0xc00) 41 46 #define WDOG_UNLOCK_VALUE 0x1ACCE551 42 47 REG32(WDOGITCR, 0xf00) ··· 61 66 REG32(CID3, 0xffc) 62 67 63 68 /* PID/CID values */ 64 - static const int watchdog_id[] = { 69 + static const uint32_t cmsdk_apb_watchdog_id[] = { 65 70 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ 66 71 0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ 67 72 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 68 73 }; 69 74 75 + static const uint32_t luminary_watchdog_id[] = { 76 + 0x00, 0x00, 0x00, 0x00, /* PID4..PID7 */ 77 + 0x05, 0x18, 0x18, 0x01, /* PID0..PID3 */ 78 + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ 79 + }; 80 + 70 81 static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s) 71 82 { 72 83 /* Return masked interrupt status */ ··· 85 96 bool wdogres; 86 97 87 98 if (s->itcr) { 99 + /* 100 + * Not checking that !s->is_luminary since s->itcr can't be written 101 + * when s->is_luminary in the first place. 102 + */ 88 103 wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK; 89 104 wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK; 90 105 } else { ··· 124 139 r = s->lock; 125 140 break; 126 141 case A_WDOGITCR: 142 + if (s->is_luminary) { 143 + goto bad_offset; 144 + } 127 145 r = s->itcr; 128 146 break; 129 147 case A_PID4 ... A_CID3: 130 - r = watchdog_id[(offset - A_PID4) / 4]; 148 + r = s->id[(offset - A_PID4) / 4]; 131 149 break; 132 150 case A_WDOGINTCLR: 133 151 case A_WDOGITOP: 152 + if (s->is_luminary) { 153 + goto bad_offset; 154 + } 134 155 qemu_log_mask(LOG_GUEST_ERROR, 135 156 "CMSDK APB watchdog read: read of WO offset %x\n", 136 157 (int)offset); 137 158 r = 0; 138 159 break; 160 + case A_WDOGTEST: 161 + if (!s->is_luminary) { 162 + goto bad_offset; 163 + } 164 + qemu_log_mask(LOG_UNIMP, 165 + "Luminary watchdog read: stall not implemented\n"); 166 + r = 0; 167 + break; 139 168 default: 169 + bad_offset: 140 170 qemu_log_mask(LOG_GUEST_ERROR, 141 171 "CMSDK APB watchdog read: bad offset %x\n", (int)offset); 142 172 r = 0; ··· 170 200 ptimer_run(s->timer, 0); 171 201 break; 172 202 case A_WDOGCONTROL: 203 + if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) { 204 + /* 205 + * The Luminary version of this device ignores writes to 206 + * this register after the guest has enabled interrupts 207 + * (so they can only be disabled again via reset). 208 + */ 209 + break; 210 + } 173 211 s->control = value & R_WDOGCONTROL_VALID_MASK; 174 212 cmsdk_apb_watchdog_update(s); 175 213 break; ··· 182 220 s->lock = (value != WDOG_UNLOCK_VALUE); 183 221 break; 184 222 case A_WDOGITCR: 223 + if (s->is_luminary) { 224 + goto bad_offset; 225 + } 185 226 s->itcr = value & R_WDOGITCR_VALID_MASK; 186 227 cmsdk_apb_watchdog_update(s); 187 228 break; 188 229 case A_WDOGITOP: 230 + if (s->is_luminary) { 231 + goto bad_offset; 232 + } 189 233 s->itop = value & R_WDOGITOP_VALID_MASK; 190 234 cmsdk_apb_watchdog_update(s); 191 235 break; ··· 197 241 "CMSDK APB watchdog write: write to RO offset 0x%x\n", 198 242 (int)offset); 199 243 break; 244 + case A_WDOGTEST: 245 + if (!s->is_luminary) { 246 + goto bad_offset; 247 + } 248 + qemu_log_mask(LOG_UNIMP, 249 + "Luminary watchdog write: stall not implemented\n"); 250 + break; 200 251 default: 252 + bad_offset: 201 253 qemu_log_mask(LOG_GUEST_ERROR, 202 254 "CMSDK APB watchdog write: bad offset 0x%x\n", 203 255 (int)offset); ··· 256 308 s, "cmsdk-apb-watchdog", 0x1000); 257 309 sysbus_init_mmio(sbd, &s->iomem); 258 310 sysbus_init_irq(sbd, &s->wdogint); 311 + 312 + s->is_luminary = false; 313 + s->id = cmsdk_apb_watchdog_id; 259 314 } 260 315 261 316 static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) ··· 318 373 .class_init = cmsdk_apb_watchdog_class_init, 319 374 }; 320 375 376 + static void luminary_watchdog_init(Object *obj) 377 + { 378 + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj); 379 + 380 + s->is_luminary = true; 381 + s->id = luminary_watchdog_id; 382 + } 383 + 384 + static const TypeInfo luminary_watchdog_info = { 385 + .name = TYPE_LUMINARY_WATCHDOG, 386 + .parent = TYPE_CMSDK_APB_WATCHDOG, 387 + .instance_init = luminary_watchdog_init 388 + }; 389 + 321 390 static void cmsdk_apb_watchdog_register_types(void) 322 391 { 323 392 type_register_static(&cmsdk_apb_watchdog_info); 393 + type_register_static(&luminary_watchdog_info); 324 394 } 325 395 326 396 type_init(cmsdk_apb_watchdog_register_types);

include/hw/watchdog/cmsdk-apb-watchdog.h

··· 38 38 #define CMSDK_APB_WATCHDOG(obj) OBJECT_CHECK(CMSDKAPBWatchdog, (obj), \ 39 39 TYPE_CMSDK_APB_WATCHDOG) 40 40 41 + /* 42 + * This shares the same struct (and cast macro) as the base 43 + * cmsdk-apb-watchdog device. 44 + */ 45 + #define TYPE_LUMINARY_WATCHDOG "luminary-watchdog" 46 + 41 47 typedef struct CMSDKAPBWatchdog { 42 48 /*< private >*/ 43 49 SysBusDevice parent_obj; ··· 46 52 MemoryRegion iomem; 47 53 qemu_irq wdogint; 48 54 uint32_t wdogclk_frq; 55 + bool is_luminary; 49 56 struct ptimer_state *timer; 50 57 51 58 uint32_t control; ··· 54 61 uint32_t itcr; 55 62 uint32_t itop; 56 63 uint32_t resetstatus; 64 + const uint32_t *id; 57 65 } CMSDKAPBWatchdog; 58 66 59 67 #endif