+1 -1

backends/cryptodev.c

··· 214 214 cryptodev_backend_set_queues, 215 215 NULL, NULL); 216 216 /* Initialize devices' queues property to 1 */ 217 217 - object_property_set_int(obj, 1, "queues", NULL); 217 217 + object_property_set_int(obj, "queues", 1, NULL); 218 218 } 219 219 220 220 static void cryptodev_backend_finalize(Object *obj)

+1 -1

backends/rng.c

··· 48 48 49 49 static void rng_backend_complete(UserCreatable *uc, Error **errp) 50 50 { 51 51 - object_property_set_bool(OBJECT(uc), true, "opened", errp); 51 51 + object_property_set_bool(OBJECT(uc), "opened", true, errp); 52 52 } 53 53 54 54 static void rng_backend_prop_set_opened(Object *obj, bool value, Error **errp)

+1 -1

bootdevice.c

··· 341 341 prop); 342 342 343 343 /* initialize devices' bootindex property to -1 */ 344 344 - object_property_set_int(obj, -1, name, NULL); 344 344 + object_property_set_int(obj, name, -1, NULL); 345 345 } 346 346 347 347 typedef struct FWLCHSEntry FWLCHSEntry;

+1 -1

crypto/secret.c

··· 110 110 static void 111 111 qcrypto_secret_complete(UserCreatable *uc, Error **errp) 112 112 { 113 113 - object_property_set_bool(OBJECT(uc), true, "loaded", errp); 113 113 + object_property_set_bool(OBJECT(uc), "loaded", true, errp); 114 114 } 115 115 116 116

+1 -1

crypto/secret_keyring.c

··· 105 105 static void 106 106 qcrypto_secret_keyring_complete(UserCreatable *uc, Error **errp) 107 107 { 108 108 - object_property_set_bool(OBJECT(uc), true, "loaded", errp); 108 108 + object_property_set_bool(OBJECT(uc), "loaded", true, errp); 109 109 } 110 110 111 111

+1 -1

crypto/tlscredsanon.c

··· 165 165 static void 166 166 qcrypto_tls_creds_anon_complete(UserCreatable *uc, Error **errp) 167 167 { 168 168 - object_property_set_bool(OBJECT(uc), true, "loaded", errp); 168 168 + object_property_set_bool(OBJECT(uc), "loaded", true, errp); 169 169 } 170 170 171 171

+1 -1

crypto/tlscredspsk.c

··· 234 234 static void 235 235 qcrypto_tls_creds_psk_complete(UserCreatable *uc, Error **errp) 236 236 { 237 237 - object_property_set_bool(OBJECT(uc), true, "loaded", errp); 237 237 + object_property_set_bool(OBJECT(uc), "loaded", true, errp); 238 238 } 239 239 240 240

+1 -1

crypto/tlscredsx509.c

··· 774 774 static void 775 775 qcrypto_tls_creds_x509_complete(UserCreatable *uc, Error **errp) 776 776 { 777 777 - object_property_set_bool(OBJECT(uc), true, "loaded", errp); 777 777 + object_property_set_bool(OBJECT(uc), "loaded", true, errp); 778 778 } 779 779 780 780

+2 -2

hw/acpi/cpu_hotplug.c

··· 41 41 */ 42 42 if (addr == 0 && data == 0) { 43 43 AcpiCpuHotplug *cpus = opaque; 44 44 - object_property_set_bool(cpus->device, false, "cpu-hotplug-legacy", 44 44 + object_property_set_bool(cpus->device, "cpu-hotplug-legacy", false, 45 45 &error_abort); 46 46 } 47 47 } ··· 63 63 64 64 cpu_id = k->get_arch_id(cpu); 65 65 if ((cpu_id / 8) >= ACPI_GPE_PROC_LEN) { 66 66 - object_property_set_bool(g->device, false, "cpu-hotplug-legacy", 66 66 + object_property_set_bool(g->device, "cpu-hotplug-legacy", false, 67 67 &error_abort); 68 68 return; 69 69 }

+1 -1

hw/acpi/ich9.c

··· 201 201 { 202 202 ICH9LPCPMRegs *s = opaque; 203 203 Object *obj = OBJECT(s->gpe_cpu.device); 204 204 - object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); 204 204 + object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); 205 205 return 0; 206 206 } 207 207

+1 -1

hw/acpi/piix4.c

··· 244 244 static int vmstate_cpuhp_pre_load(void *opaque) 245 245 { 246 246 Object *obj = OBJECT(opaque); 247 247 - object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort); 247 247 + object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); 248 248 return 0; 249 249 } 250 250

+3 -3

hw/arm/allwinner-a10.c

··· 142 142 143 143 sprintf(bus, "usb-bus.%d", i); 144 144 145 145 - object_property_set_bool(OBJECT(&s->ehci[i]), true, 146 146 - "companion-enable", &error_fatal); 145 145 + object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", 146 146 + true, &error_fatal); 147 147 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal); 148 148 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 149 149 AW_A10_EHCI_BASE + i * 0x8000); 150 150 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 151 151 qdev_get_gpio_in(dev, 39 + i)); 152 152 153 153 - object_property_set_str(OBJECT(&s->ohci[i]), bus, "masterbus", 153 153 + object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus, 154 154 &error_fatal); 155 155 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal); 156 156 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,

+37 -39

hw/arm/armsse.c

··· 534 534 * later if necessary. 535 535 */ 536 536 if (extract32(info->cpuwait_rst, i, 1)) { 537 537 - object_property_set_bool(cpuobj, true, "start-powered-off", &err); 537 537 + object_property_set_bool(cpuobj, "start-powered-off", true, &err); 538 538 if (err) { 539 539 error_propagate(errp, err); 540 540 return; 541 541 } 542 542 } 543 543 if (!s->cpu_fpu[i]) { 544 544 - object_property_set_bool(cpuobj, false, "vfp", &err); 544 544 + object_property_set_bool(cpuobj, "vfp", false, &err); 545 545 if (err) { 546 546 error_propagate(errp, err); 547 547 return; 548 548 } 549 549 } 550 550 if (!s->cpu_dsp[i]) { 551 551 - object_property_set_bool(cpuobj, false, "dsp", &err); 551 551 + object_property_set_bool(cpuobj, "dsp", false, &err); 552 552 if (err) { 553 553 error_propagate(errp, err); 554 554 return; ··· 562 562 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 563 563 &s->container, -1); 564 564 } 565 565 - object_property_set_link(cpuobj, OBJECT(&s->cpu_container[i]), 566 566 - "memory", &error_abort); 567 567 - object_property_set_link(cpuobj, OBJECT(s), "idau", &error_abort); 565 565 + object_property_set_link(cpuobj, "memory", 566 566 + OBJECT(&s->cpu_container[i]), &error_abort); 567 567 + object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort); 568 568 if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), &err)) { 569 569 error_propagate(errp, err); 570 570 return; ··· 604 604 DeviceState *devs = DEVICE(splitter); 605 605 int cpunum; 606 606 607 607 - object_property_set_int(splitter, info->num_cpus, 608 608 - "num-lines", &err); 607 607 + object_property_set_int(splitter, "num-lines", info->num_cpus, 608 608 + &err); 609 609 if (err) { 610 610 error_propagate(errp, err); 611 611 return; ··· 658 658 * multiple lines, one for each of the PPCs within the ARMSSE and one 659 659 * that will be an output from the ARMSSE to the system. 660 660 */ 661 661 - object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, 662 662 - "num-lines", &err); 661 661 + object_property_set_int(OBJECT(&s->sec_resp_splitter), "num-lines", 3, 662 662 + &err); 663 663 if (err) { 664 664 error_propagate(errp, err); 665 665 return; ··· 685 685 error_propagate(errp, err); 686 686 return; 687 687 } 688 688 - object_property_set_link(OBJECT(&s->mpc[i]), OBJECT(&s->sram[i]), 689 689 - "downstream", &error_abort); 688 688 + object_property_set_link(OBJECT(&s->mpc[i]), "downstream", 689 689 + OBJECT(&s->sram[i]), &error_abort); 690 690 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), &err)) { 691 691 error_propagate(errp, err); 692 692 return; ··· 702 702 } 703 703 704 704 /* We must OR together lines from the MPC splitters to go to the NVIC */ 705 705 - object_property_set_int(OBJECT(&s->mpc_irq_orgate), 706 706 - IOTS_NUM_EXP_MPC + info->sram_banks, 707 707 - "num-lines", &err); 705 705 + object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines", 706 706 + IOTS_NUM_EXP_MPC + info->sram_banks, &err); 708 707 if (err) { 709 708 error_propagate(errp, err); 710 709 return; ··· 734 733 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 735 734 armsse_get_common_irq_in(s, 3)); 736 735 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 737 737 - object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", 736 736 + object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr), 738 737 &error_abort); 739 738 740 739 qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); ··· 745 744 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 746 745 armsse_get_common_irq_in(s, 4)); 747 746 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 748 748 - object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", 747 747 + object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr), 749 748 &error_abort); 750 749 751 750 qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); ··· 756 755 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 757 756 armsse_get_common_irq_in(s, 5)); 758 757 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 759 759 - object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", 758 758 + object_property_set_link(OBJECT(&s->apb_ppc0), "port[2]", OBJECT(mr), 760 759 &error_abort); 761 760 762 761 if (info->has_mhus) { ··· 780 779 } 781 780 port = g_strdup_printf("port[%d]", i + 3); 782 781 mr = sysbus_mmio_get_region(mhu_sbd, 0); 783 783 - object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), 784 784 - port, &error_abort); 782 782 + object_property_set_link(OBJECT(&s->apb_ppc0), port, OBJECT(mr), 783 783 + &error_abort); 785 784 g_free(port); 786 785 787 786 /* ··· 842 841 * ones) are sent individually to the security controller, and also 843 842 * ORed together to give a single combined PPC interrupt to the NVIC. 844 843 */ 845 845 - object_property_set_int(OBJECT(&s->ppc_irq_orgate), 846 846 - NUM_PPCS, "num-lines", &err); 844 844 + object_property_set_int(OBJECT(&s->ppc_irq_orgate), "num-lines", NUM_PPCS, 845 845 + &err); 847 846 if (err) { 848 847 error_propagate(errp, err); 849 848 return; ··· 923 922 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 924 923 armsse_get_common_irq_in(s, 2)); 925 924 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 926 926 - object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", 925 925 + object_property_set_link(OBJECT(&s->apb_ppc1), "port[0]", OBJECT(mr), 927 926 &error_abort); 928 927 929 928 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc1), &err)) { ··· 950 949 qdev_get_gpio_in_named(dev_apb_ppc1, 951 950 "cfg_sec_resp", 0)); 952 951 953 953 - object_property_set_int(OBJECT(&s->sysinfo), info->sys_version, 954 954 - "SYS_VERSION", &err); 952 952 + object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", 953 953 + info->sys_version, &err); 955 954 if (err) { 956 955 error_propagate(errp, err); 957 956 return; 958 957 } 959 959 - object_property_set_int(OBJECT(&s->sysinfo), 960 960 - armsse_sys_config_value(s, info), 961 961 - "SYS_CONFIG", &err); 958 958 + object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG", 959 959 + armsse_sys_config_value(s, info), &err); 962 960 if (err) { 963 961 error_propagate(errp, err); 964 962 return; ··· 970 968 /* System information registers */ 971 969 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 972 970 /* System control registers */ 973 973 - object_property_set_int(OBJECT(&s->sysctl), info->sys_version, 974 974 - "SYS_VERSION", &error_abort); 975 975 - object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst, 976 976 - "CPUWAIT_RST", &error_abort); 977 977 - object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, 978 978 - "INITSVTOR0_RST", &error_abort); 979 979 - object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, 980 980 - "INITSVTOR1_RST", &error_abort); 971 971 + object_property_set_int(OBJECT(&s->sysctl), "SYS_VERSION", 972 972 + info->sys_version, &error_abort); 973 973 + object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", 974 974 + info->cpuwait_rst, &error_abort); 975 975 + object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", 976 976 + s->init_svtor, &error_abort); 977 977 + object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", 978 978 + s->init_svtor, &error_abort); 981 979 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), &err)) { 982 980 error_propagate(errp, err); 983 981 return; ··· 1007 1005 } 1008 1006 1009 1007 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 1010 1010 - object_property_set_int(OBJECT(&s->nmi_orgate), 2, "num-lines", &err); 1008 1008 + object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2, &err); 1011 1009 if (err) { 1012 1010 error_propagate(errp, err); 1013 1011 return; ··· 1051 1049 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1052 1050 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1053 1051 1054 1054 - object_property_set_int(splitter, 2, "num-lines", &err); 1052 1052 + object_property_set_int(splitter, "num-lines", 2, &err); 1055 1053 if (err) { 1056 1054 error_propagate(errp, err); 1057 1055 return; ··· 1097 1095 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1098 1096 DeviceState *dev_splitter = DEVICE(splitter); 1099 1097 1100 1100 - object_property_set_int(OBJECT(splitter), 2, "num-lines", &err); 1098 1098 + object_property_set_int(OBJECT(splitter), "num-lines", 2, &err); 1101 1099 if (err) { 1102 1100 error_propagate(errp, err); 1103 1101 return;

+11 -13

hw/arm/armv7m.c

··· 167 167 return; 168 168 } 169 169 170 170 - object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory", 170 170 + object_property_set_link(OBJECT(s->cpu), "memory", OBJECT(&s->container), 171 171 &error_abort); 172 172 if (object_property_find(OBJECT(s->cpu), "idau", NULL)) { 173 173 - object_property_set_link(OBJECT(s->cpu), s->idau, "idau", 173 173 + object_property_set_link(OBJECT(s->cpu), "idau", s->idau, 174 174 &error_abort); 175 175 } 176 176 if (object_property_find(OBJECT(s->cpu), "init-svtor", NULL)) { 177 177 - object_property_set_uint(OBJECT(s->cpu), s->init_svtor, 178 178 - "init-svtor", &err); 177 177 + object_property_set_uint(OBJECT(s->cpu), "init-svtor", s->init_svtor, 178 178 + &err); 179 179 if (err != NULL) { 180 180 error_propagate(errp, err); 181 181 return; 182 182 } 183 183 } 184 184 if (object_property_find(OBJECT(s->cpu), "start-powered-off", NULL)) { 185 185 - object_property_set_bool(OBJECT(s->cpu), s->start_powered_off, 186 186 - "start-powered-off", &err); 185 185 + object_property_set_bool(OBJECT(s->cpu), "start-powered-off", 186 186 + s->start_powered_off, &err); 187 187 if (err != NULL) { 188 188 error_propagate(errp, err); 189 189 return; 190 190 } 191 191 } 192 192 if (object_property_find(OBJECT(s->cpu), "vfp", NULL)) { 193 193 - object_property_set_bool(OBJECT(s->cpu), s->vfp, 194 194 - "vfp", &err); 193 193 + object_property_set_bool(OBJECT(s->cpu), "vfp", s->vfp, &err); 195 194 if (err != NULL) { 196 195 error_propagate(errp, err); 197 196 return; 198 197 } 199 198 } 200 199 if (object_property_find(OBJECT(s->cpu), "dsp", NULL)) { 201 201 - object_property_set_bool(OBJECT(s->cpu), s->dsp, 202 202 - "dsp", &err); 200 200 + object_property_set_bool(OBJECT(s->cpu), "dsp", s->dsp, &err); 203 201 if (err != NULL) { 204 202 error_propagate(errp, err); 205 203 return; ··· 245 243 Object *obj = OBJECT(&s->bitband[i]); 246 244 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]); 247 245 248 248 - object_property_set_int(obj, bitband_input_addr[i], "base", &err); 246 246 + object_property_set_int(obj, "base", bitband_input_addr[i], &err); 249 247 if (err != NULL) { 250 248 error_propagate(errp, err); 251 249 return; 252 250 } 253 253 - object_property_set_link(obj, OBJECT(s->board_memory), 254 254 - "source-memory", &error_abort); 251 251 + object_property_set_link(obj, "source-memory", 252 252 + OBJECT(s->board_memory), &error_abort); 255 253 if (!sysbus_realize(SYS_BUS_DEVICE(obj), &err)) { 256 254 error_propagate(errp, err); 257 255 return;

+12 -12

hw/arm/aspeed.c

··· 277 277 /* 278 278 * This will error out if isize is not supported by memory controller. 279 279 */ 280 280 - object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", 280 280 + object_property_set_uint(OBJECT(&bmc->soc), "ram-size", ram_size, 281 281 &error_fatal); 282 282 283 283 for (i = 0; i < sc->macs_num; i++) { ··· 288 288 } 289 289 } 290 290 291 291 - object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1", 291 291 + object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, 292 292 &error_abort); 293 293 - object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2", 293 293 + object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, 294 294 &error_abort); 295 295 - object_property_set_int(OBJECT(&bmc->soc), amc->num_cs, "num-cs", 295 295 + object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, 296 296 &error_abort); 297 297 - object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), 298 298 - "dram", &error_abort); 297 297 + object_property_set_link(OBJECT(&bmc->soc), "dram", 298 298 + OBJECT(&bmc->ram_container), &error_abort); 299 299 if (machine->kernel_filename) { 300 300 /* 301 301 * When booting with a -kernel command line there is no u-boot 302 302 * that runs to unlock the SCU. In this case set the default to 303 303 * be unlocked as the kernel expects 304 304 */ 305 305 - object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, 306 306 - "hw-prot-key", &error_abort); 305 305 + object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", 306 306 + ASPEED_SCU_PROT_KEY, &error_abort); 307 307 } 308 308 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); 309 309 ··· 393 393 /* add a TMP423 temperature sensor */ 394 394 dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), 395 395 "tmp423", 0x4c); 396 396 - object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); 397 397 - object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); 398 398 - object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); 399 399 - object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); 396 396 + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 397 397 + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 398 398 + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 399 399 + object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 400 400 } 401 401 402 402 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)

+26 -28

hw/arm/aspeed_ast2600.c

··· 196 196 object_initialize_child(obj, "sd-controller", &s->sdhci, 197 197 TYPE_ASPEED_SDHCI); 198 198 199 199 - object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); 199 199 + object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 200 200 201 201 /* Init sd card slot class here so that they're under the correct parent */ 202 202 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { ··· 207 207 object_initialize_child(obj, "emmc-controller", &s->emmc, 208 208 TYPE_ASPEED_SDHCI); 209 209 210 210 - object_property_set_int(OBJECT(&s->emmc), 1, "num-slots", &error_abort); 210 210 + object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); 211 211 212 212 object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], 213 213 TYPE_SYSBUS_SDHCI); ··· 241 241 242 242 /* CPU */ 243 243 for (i = 0; i < sc->num_cpus; i++) { 244 244 - object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, 245 245 - "psci-conduit", &error_abort); 244 244 + object_property_set_int(OBJECT(&s->cpu[i]), "psci-conduit", 245 245 + QEMU_PSCI_CONDUIT_SMC, &error_abort); 246 246 if (sc->num_cpus > 1) { 247 247 - object_property_set_int(OBJECT(&s->cpu[i]), 248 248 - ASPEED_A7MPCORE_ADDR, 249 249 - "reset-cbar", &error_abort); 247 247 + object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 248 248 + ASPEED_A7MPCORE_ADDR, &error_abort); 250 249 } 251 251 - object_property_set_int(OBJECT(&s->cpu[i]), aspeed_calc_affinity(i), 252 252 - "mp-affinity", &error_abort); 250 250 + object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", 251 251 + aspeed_calc_affinity(i), &error_abort); 253 252 254 254 - object_property_set_int(OBJECT(&s->cpu[i]), 1125000000, "cntfrq", 253 253 + object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, 255 254 &error_abort); 256 255 257 256 /* ··· 266 265 } 267 266 268 267 /* A7MPCORE */ 269 269 - object_property_set_int(OBJECT(&s->a7mpcore), sc->num_cpus, "num-cpu", 268 268 + object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, 270 269 &error_abort); 271 271 - object_property_set_int(OBJECT(&s->a7mpcore), 270 270 + object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 272 271 ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, 273 273 - "num-irq", &error_abort); 272 272 + &error_abort); 274 273 275 274 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 276 275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); ··· 316 315 aspeed_soc_get_irq(s, ASPEED_RTC)); 317 316 318 317 /* Timer */ 319 319 - object_property_set_link(OBJECT(&s->timerctrl), 320 320 - OBJECT(&s->scu), "scu", &error_abort); 318 318 + object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 319 319 + &error_abort); 321 320 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err)) { 322 321 error_propagate(errp, err); 323 322 return; ··· 337 336 } 338 337 339 338 /* I2C */ 340 340 - object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", 339 339 + object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 341 340 &error_abort); 342 341 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err)) { 343 342 error_propagate(errp, err); ··· 355 354 } 356 355 357 356 /* FMC, The number of CS is set at the board level */ 358 358 - object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", 357 357 + object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 359 358 &error_abort); 360 360 - object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 361 361 - "sdram-base", &err); 359 359 + object_property_set_int(OBJECT(&s->fmc), "sdram-base", 360 360 + sc->memmap[ASPEED_SDRAM], &err); 362 361 if (err) { 363 362 error_propagate(errp, err); 364 363 return; ··· 375 374 376 375 /* SPI */ 377 376 for (i = 0; i < sc->spis_num; i++) { 378 378 - object_property_set_link(OBJECT(&s->spi[i]), OBJECT(s->dram_mr), 379 379 - "dram", &error_abort); 380 380 - object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", 381 381 - &error_abort); 377 377 + object_property_set_link(OBJECT(&s->spi[i]), "dram", 378 378 + OBJECT(s->dram_mr), &error_abort); 379 379 + object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 382 380 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) { 383 381 error_propagate(errp, err); 384 382 return; ··· 412 410 for (i = 0; i < sc->wdts_num; i++) { 413 411 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 414 412 415 415 - object_property_set_link(OBJECT(&s->wdt[i]), 416 416 - OBJECT(&s->scu), "scu", &error_abort); 413 413 + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 414 414 + &error_abort); 417 415 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err)) { 418 416 error_propagate(errp, err); 419 417 return; ··· 424 422 425 423 /* Net */ 426 424 for (i = 0; i < sc->macs_num; i++) { 427 427 - object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 425 425 + object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 428 426 &error_abort); 429 427 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &err)) { 430 428 error_propagate(errp, err); ··· 435 433 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 436 434 aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); 437 435 438 438 - object_property_set_link(OBJECT(&s->mii[i]), OBJECT(&s->ftgmac100[i]), 439 439 - "nic", &error_abort); 436 436 + object_property_set_link(OBJECT(&s->mii[i]), "nic", 437 437 + OBJECT(&s->ftgmac100[i]), &error_abort); 440 438 if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), &err)) { 441 439 error_propagate(errp, err); 442 440 return;

+11 -12

hw/arm/aspeed_soc.c

··· 204 204 205 205 object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); 206 206 207 207 - object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort); 207 207 + object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 208 208 209 209 /* Init sd card slot class here so that they're under the correct parent */ 210 210 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { ··· 274 274 aspeed_soc_get_irq(s, ASPEED_RTC)); 275 275 276 276 /* Timer */ 277 277 - object_property_set_link(OBJECT(&s->timerctrl), 278 278 - OBJECT(&s->scu), "scu", &error_abort); 277 277 + object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 278 278 + &error_abort); 279 279 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err)) { 280 280 error_propagate(errp, err); 281 281 return; ··· 295 295 } 296 296 297 297 /* I2C */ 298 298 - object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", 298 298 + object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 299 299 &error_abort); 300 300 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err)) { 301 301 error_propagate(errp, err); ··· 306 306 aspeed_soc_get_irq(s, ASPEED_I2C)); 307 307 308 308 /* FMC, The number of CS is set at the board level */ 309 309 - object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", 309 309 + object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 310 310 &error_abort); 311 311 - object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM], 312 312 - "sdram-base", &err); 311 311 + object_property_set_int(OBJECT(&s->fmc), "sdram-base", 312 312 + sc->memmap[ASPEED_SDRAM], &err); 313 313 if (err) { 314 314 error_propagate(errp, err); 315 315 return; ··· 326 326 327 327 /* SPI */ 328 328 for (i = 0; i < sc->spis_num; i++) { 329 329 - object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", 330 330 - &error_abort); 329 329 + object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); 331 330 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) { 332 331 error_propagate(errp, err); 333 332 return; ··· 361 360 for (i = 0; i < sc->wdts_num; i++) { 362 361 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 363 362 364 364 - object_property_set_link(OBJECT(&s->wdt[i]), 365 365 - OBJECT(&s->scu), "scu", &error_abort); 363 363 + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 364 364 + &error_abort); 366 365 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err)) { 367 366 error_propagate(errp, err); 368 367 return; ··· 373 372 374 373 /* Net */ 375 374 for (i = 0; i < sc->macs_num; i++) { 376 376 - object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed", 375 375 + object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 377 376 &error_abort); 378 377 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &err)) { 379 378 error_propagate(errp, err);

+6 -6

hw/arm/bcm2835_peripherals.c

··· 222 222 return; 223 223 } 224 224 225 225 - object_property_set_uint(OBJECT(&s->fb), ram_size - vcram_size, 226 226 - "vcram-base", &err); 225 225 + object_property_set_uint(OBJECT(&s->fb), "vcram-base", 226 226 + ram_size - vcram_size, &err); 227 227 if (err) { 228 228 error_propagate(errp, err); 229 229 return; ··· 270 270 * For the exact details please refer to the Arasan documentation: 271 271 * SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf 272 272 */ 273 273 - object_property_set_uint(OBJECT(&s->sdhci), 3, "sd-spec-version", 274 274 - &error_abort); 275 275 - object_property_set_uint(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg", 273 273 + object_property_set_uint(OBJECT(&s->sdhci), "sd-spec-version", 3, 276 274 &error_abort); 277 277 - object_property_set_bool(OBJECT(&s->sdhci), true, "pending-insert-quirk", 275 275 + object_property_set_uint(OBJECT(&s->sdhci), "capareg", 276 276 + BCM2835_SDHC_CAPAREG, &error_abort); 277 277 + object_property_set_bool(OBJECT(&s->sdhci), "pending-insert-quirk", true, 278 278 &error_abort); 279 279 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err)) { 280 280 error_propagate(errp, err);

+4 -5

hw/arm/bcm2836.c

··· 110 110 s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n; 111 111 112 112 /* set periphbase/CBAR value for CPU-local registers */ 113 113 - object_property_set_int(OBJECT(&s->cpu[n].core), 114 114 - info->peri_base, 115 115 - "reset-cbar", &err); 113 113 + object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", 114 114 + info->peri_base, &err); 116 115 if (err) { 117 116 error_propagate(errp, err); 118 117 return; 119 118 } 120 119 121 120 /* start powered off if not enabled */ 122 122 - object_property_set_bool(OBJECT(&s->cpu[n].core), n >= s->enabled_cpus, 123 123 - "start-powered-off", &err); 121 121 + object_property_set_bool(OBJECT(&s->cpu[n].core), "start-powered-off", 122 122 + n >= s->enabled_cpus, &err); 124 123 if (err) { 125 124 error_propagate(errp, err); 126 125 return;

+3 -3

hw/arm/cubieboard.c

··· 62 62 object_property_add_child(OBJECT(machine), "soc", OBJECT(a10)); 63 63 object_unref(OBJECT(a10)); 64 64 65 65 - object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err); 65 65 + object_property_set_int(OBJECT(&a10->emac), "phy-addr", 1, &err); 66 66 if (err != NULL) { 67 67 error_reportf_err(err, "Couldn't set phy address: "); 68 68 exit(1); 69 69 } 70 70 71 71 - object_property_set_int(OBJECT(&a10->timer), 32768, "clk0-freq", &err); 71 71 + object_property_set_int(OBJECT(&a10->timer), "clk0-freq", 32768, &err); 72 72 if (err != NULL) { 73 73 error_reportf_err(err, "Couldn't set clk0 frequency: "); 74 74 exit(1); 75 75 } 76 76 77 77 - object_property_set_int(OBJECT(&a10->timer), 24000000, "clk1-freq", &err); 77 77 + object_property_set_int(OBJECT(&a10->timer), "clk1-freq", 24000000, &err); 78 78 if (err != NULL) { 79 79 error_reportf_err(err, "Couldn't set clk1 frequency: "); 80 80 exit(1);

+1 -1

hw/arm/digic.c

··· 56 56 SysBusDevice *sbd; 57 57 int i; 58 58 59 59 - object_property_set_bool(OBJECT(&s->cpu), true, "reset-hivecs", &err); 59 59 + object_property_set_bool(OBJECT(&s->cpu), "reset-hivecs", true, &err); 60 60 if (err != NULL) { 61 61 error_propagate(errp, err); 62 62 return;

+7 -6

hw/arm/exynos4210.c

··· 188 188 sysbus_realize_and_unref(busdev, &error_fatal); 189 189 sysbus_mmio_map(busdev, 0, base); 190 190 191 191 - object_property_set_int(OBJECT(orgate), nevents + 1, "num-lines", 191 191 + object_property_set_int(OBJECT(orgate), "num-lines", nevents + 1, 192 192 &error_abort); 193 193 qdev_realize(DEVICE(orgate), NULL, &error_abort); 194 194 ··· 215 215 * support EL3 so the CPU EL3 property is disabled before realization. 216 216 */ 217 217 if (object_property_find(cpuobj, "has_el3", NULL)) { 218 218 - object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 218 218 + object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 219 219 } 220 220 221 221 s->cpu[n] = ARM_CPU(cpuobj); 222 222 - object_property_set_int(cpuobj, exynos4210_calc_affinity(n), 223 223 - "mp-affinity", &error_abort); 224 224 - object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 225 225 - "reset-cbar", &error_abort); 222 222 + object_property_set_int(cpuobj, "mp-affinity", 223 223 + exynos4210_calc_affinity(n), &error_abort); 224 224 + object_property_set_int(cpuobj, "reset-cbar", 225 225 + EXYNOS4210_SMP_PRIVATE_BASE_ADDR, 226 226 + &error_abort); 226 227 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 227 228 } 228 229

+6 -8

hw/arm/fsl-imx25.c

··· 249 249 { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ }, 250 250 }; 251 251 252 252 - object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version", 253 253 - &error_abort); 254 254 - object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES, 255 255 - "capareg", 256 256 - &error_abort); 257 257 - object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX, 258 258 - "vendor", 252 252 + object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 2, 259 253 &error_abort); 254 254 + object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", 255 255 + IMX25_ESDHC_CAPABILITIES, &error_abort); 256 256 + object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", 257 257 + SDHCI_VENDOR_IMX, &error_abort); 260 258 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err)) { 261 259 error_propagate(errp, err); 262 260 return; ··· 285 283 } 286 284 287 285 /* Watchdog */ 288 288 - object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support", 286 286 + object_property_set_bool(OBJECT(&s->wdt), "pretimeout-support", true, 289 287 &error_abort); 290 288 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort); 291 289 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);

+1 -1

hw/arm/fsl-imx31.c

··· 179 179 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } 180 180 }; 181 181 182 182 - object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel", 182 182 + object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", false, 183 183 &error_abort); 184 184 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err)) { 185 185 error_propagate(errp, err);

+17 -20

hw/arm/fsl-imx6.c

··· 120 120 121 121 /* On uniprocessor, the CBAR is set to 0 */ 122 122 if (smp_cpus > 1) { 123 123 - object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR, 124 124 - "reset-cbar", &error_abort); 123 123 + object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", 124 124 + FSL_IMX6_A9MPCORE_ADDR, &error_abort); 125 125 } 126 126 127 127 /* All CPU but CPU 0 start in power off mode */ 128 128 if (i) { 129 129 - object_property_set_bool(OBJECT(&s->cpu[i]), true, 130 130 - "start-powered-off", &error_abort); 129 129 + object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", 130 130 + true, &error_abort); 131 131 } 132 132 133 133 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, &err)) { ··· 136 136 } 137 137 } 138 138 139 139 - object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu", 139 139 + object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus, 140 140 &error_abort); 141 141 142 142 - object_property_set_int(OBJECT(&s->a9mpcore), 143 143 - FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq", 144 144 - &error_abort); 142 142 + object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", 143 143 + FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); 145 144 146 145 if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &err)) { 147 146 error_propagate(errp, err); ··· 295 294 }, 296 295 }; 297 296 298 298 - object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel", 299 299 - &error_abort); 300 300 - object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq", 297 297 + object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, 301 298 &error_abort); 299 299 + object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", 300 300 + true, &error_abort); 302 301 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err)) { 303 302 error_propagate(errp, err); 304 303 return; ··· 326 325 }; 327 326 328 327 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 329 329 - object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version", 330 330 - &error_abort); 331 331 - object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES, 332 332 - "capareg", 333 333 - &error_abort); 334 334 - object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX, 335 335 - "vendor", 328 328 + object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3, 336 329 &error_abort); 330 330 + object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg", 331 331 + IMX6_ESDHC_CAPABILITIES, &error_abort); 332 332 + object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor", 333 333 + SDHCI_VENDOR_IMX, &error_abort); 337 334 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err)) { 338 335 error_propagate(errp, err); 339 336 return; ··· 417 414 FSL_IMX6_WDOG2_IRQ, 418 415 }; 419 416 420 420 - object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", 421 421 - &error_abort); 417 417 + object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 418 418 + true, &error_abort); 422 419 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 423 420 424 421 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);

+13 -16

hw/arm/fsl-imx6ul.c

··· 166 166 return; 167 167 } 168 168 169 169 - object_property_set_int(OBJECT(&s->cpu), QEMU_PSCI_CONDUIT_SMC, 170 170 - "psci-conduit", &error_abort); 169 169 + object_property_set_int(OBJECT(&s->cpu), "psci-conduit", 170 170 + QEMU_PSCI_CONDUIT_SMC, &error_abort); 171 171 qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); 172 172 173 173 /* 174 174 * A7MPCORE 175 175 */ 176 176 - object_property_set_int(OBJECT(&s->a7mpcore), 1, "num-cpu", &error_abort); 177 177 - object_property_set_int(OBJECT(&s->a7mpcore), 178 178 - FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, 179 179 - "num-irq", &error_abort); 176 176 + object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort); 177 177 + object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 178 178 + FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort); 180 179 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 181 180 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); 182 181 ··· 427 426 FSL_IMX6UL_ENET2_TIMER_IRQ, 428 427 }; 429 428 430 430 - object_property_set_uint(OBJECT(&s->eth[i]), 431 431 - s->phy_num[i], 432 432 - "phy-num", &error_abort); 433 433 - object_property_set_uint(OBJECT(&s->eth[i]), 434 434 - FSL_IMX6UL_ETH_NUM_TX_RINGS, 435 435 - "tx-ring-num", &error_abort); 429 429 + object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", 430 430 + s->phy_num[i], &error_abort); 431 431 + object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", 432 432 + FSL_IMX6UL_ETH_NUM_TX_RINGS, &error_abort); 436 433 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); 437 434 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort); 438 435 ··· 482 479 FSL_IMX6UL_USDHC2_IRQ, 483 480 }; 484 481 485 485 - object_property_set_uint(OBJECT(&s->usdhc[i]), SDHCI_VENDOR_IMX, 486 486 - "vendor", &error_abort); 482 482 + object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", 483 483 + SDHCI_VENDOR_IMX, &error_abort); 487 484 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); 488 485 489 486 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, ··· 515 512 FSL_IMX6UL_WDOG3_IRQ, 516 513 }; 517 514 518 518 - object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", 519 519 - &error_abort); 515 515 + object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 516 516 + true, &error_abort); 520 517 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 521 518 522 519 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,

+15 -16

hw/arm/fsl-imx7.c

··· 159 159 for (i = 0; i < smp_cpus; i++) { 160 160 o = OBJECT(&s->cpu[i]); 161 161 162 162 - object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC, 163 163 - "psci-conduit", &error_abort); 162 162 + object_property_set_int(o, "psci-conduit", QEMU_PSCI_CONDUIT_SMC, 163 163 + &error_abort); 164 164 165 165 /* On uniprocessor, the CBAR is set to 0 */ 166 166 if (smp_cpus > 1) { 167 167 - object_property_set_int(o, FSL_IMX7_A7MPCORE_ADDR, 168 168 - "reset-cbar", &error_abort); 167 167 + object_property_set_int(o, "reset-cbar", FSL_IMX7_A7MPCORE_ADDR, 168 168 + &error_abort); 169 169 } 170 170 171 171 if (i) { 172 172 /* Secondary CPUs start in PSCI powered-down state */ 173 173 - object_property_set_bool(o, true, 174 174 - "start-powered-off", &error_abort); 173 173 + object_property_set_bool(o, "start-powered-off", true, 174 174 + &error_abort); 175 175 } 176 176 177 177 qdev_realize(DEVICE(o), NULL, &error_abort); ··· 180 180 /* 181 181 * A7MPCORE 182 182 */ 183 183 - object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu", 183 183 + object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", smp_cpus, 184 184 &error_abort); 185 185 - object_property_set_int(OBJECT(&s->a7mpcore), 186 186 - FSL_IMX7_MAX_IRQ + GIC_INTERNAL, 187 187 - "num-irq", &error_abort); 185 185 + object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 186 186 + FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort); 188 187 189 188 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 190 189 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR); ··· 364 363 FSL_IMX7_ENET2_ADDR, 365 364 }; 366 365 367 367 - object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS, 368 368 - "tx-ring-num", &error_abort); 366 366 + object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", 367 367 + FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort); 369 368 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); 370 369 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort); 371 370 ··· 393 392 FSL_IMX7_USDHC3_IRQ, 394 393 }; 395 394 396 396 - object_property_set_uint(OBJECT(&s->usdhc[i]), SDHCI_VENDOR_IMX, 397 397 - "vendor", &error_abort); 395 395 + object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", 396 396 + SDHCI_VENDOR_IMX, &error_abort); 398 397 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); 399 398 400 399 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, ··· 432 431 FSL_IMX7_WDOG4_IRQ, 433 432 }; 434 433 435 435 - object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", 436 436 - &error_abort); 434 434 + object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 435 435 + true, &error_abort); 437 436 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 438 437 439 438 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);

+6 -6

hw/arm/highbank.c

··· 267 267 cpuobj = object_new(machine->cpu_type); 268 268 cpu = ARM_CPU(cpuobj); 269 269 270 270 - object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC, 271 271 - "psci-conduit", &error_abort); 270 270 + object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC, 271 271 + &error_abort); 272 272 273 273 if (n) { 274 274 /* Secondary CPUs start in PSCI powered-down state */ 275 275 - object_property_set_bool(cpuobj, true, 276 276 - "start-powered-off", &error_abort); 275 275 + object_property_set_bool(cpuobj, "start-powered-off", true, 276 276 + &error_abort); 277 277 } 278 278 279 279 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 280 280 - object_property_set_int(cpuobj, MPCORE_PERIPHBASE, 281 281 - "reset-cbar", &error_abort); 280 280 + object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE, 281 281 + &error_abort); 282 282 } 283 283 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 284 284 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);

+1 -1

hw/arm/integratorcp.c

··· 604 604 * realization. 605 605 */ 606 606 if (object_property_find(cpuobj, "has_el3", NULL)) { 607 607 - object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 607 607 + object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 608 608 } 609 609 610 610 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);

+2 -2

hw/arm/mcimx6ul-evk.c

··· 40 40 41 41 s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL)); 42 42 object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); 43 43 - object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal); 44 44 - object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal); 43 43 + object_property_set_uint(OBJECT(s), "fec1-phy-num", 2, &error_fatal); 44 44 + object_property_set_uint(OBJECT(s), "fec2-phy-num", 1, &error_fatal); 45 45 qdev_realize(DEVICE(s), NULL, &error_fatal); 46 46 47 47 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,

+2 -2

hw/arm/microbit.c

··· 40 40 object_initialize_child(OBJECT(machine), "nrf51", &s->nrf51, 41 41 TYPE_NRF51_SOC); 42 42 qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0)); 43 43 - object_property_set_link(OBJECT(&s->nrf51), OBJECT(system_memory), 44 44 - "memory", &error_fatal); 43 43 + object_property_set_link(OBJECT(&s->nrf51), "memory", 44 44 + OBJECT(system_memory), &error_fatal); 45 45 sysbus_realize(SYS_BUS_DEVICE(&s->nrf51), &error_fatal); 46 46 47 47 /*

+15 -16

hw/arm/mps2-tz.c

··· 265 265 memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); 266 266 267 267 object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); 268 268 - object_property_set_link(OBJECT(mpc), OBJECT(ssram), 269 269 - "downstream", &error_fatal); 268 268 + object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram), 269 269 + &error_fatal); 270 270 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 271 271 /* Map the upstream end of the MPC into system memory */ 272 272 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); ··· 308 308 */ 309 309 object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 310 310 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 311 311 - object_property_set_link(OBJECT(msc), OBJECT(msc_downstream), 312 312 - "downstream", &error_fatal); 313 313 - object_property_set_link(OBJECT(msc), OBJECT(mms), 314 314 - "idau", &error_fatal); 311 311 + object_property_set_link(OBJECT(msc), "downstream", 312 312 + OBJECT(msc_downstream), &error_fatal); 313 313 + object_property_set_link(OBJECT(msc), "idau", OBJECT(mms), &error_fatal); 315 314 sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 316 315 317 316 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, ··· 330 329 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 331 330 332 331 object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 333 333 - object_property_set_link(OBJECT(dma), OBJECT(msc_upstream), 334 334 - "downstream", &error_fatal); 332 332 + object_property_set_link(OBJECT(dma), "downstream", OBJECT(msc_upstream), 333 333 + &error_fatal); 335 334 sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 336 335 337 336 s = SYS_BUS_DEVICE(dma); ··· 404 403 object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 405 404 mmc->armsse_type); 406 405 iotkitdev = DEVICE(&mms->iotkit); 407 407 - object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), 408 408 - "memory", &error_abort); 406 406 + object_property_set_link(OBJECT(&mms->iotkit), "memory", 407 407 + OBJECT(system_memory), &error_abort); 409 408 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); 410 409 qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); 411 410 sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); ··· 425 424 NULL); 426 425 g_free(name); 427 426 428 428 - object_property_set_int(OBJECT(splitter), 2, "num-lines", 427 427 + object_property_set_int(OBJECT(splitter), "num-lines", 2, 429 428 &error_fatal); 430 429 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 431 430 qdev_connect_gpio_out(DEVICE(splitter), 0, ··· 442 441 */ 443 442 object_initialize_child(OBJECT(machine), "sec-resp-splitter", 444 443 &mms->sec_resp_splitter, TYPE_SPLIT_IRQ); 445 445 - object_property_set_int(OBJECT(&mms->sec_resp_splitter), 444 444 + object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 446 445 ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), 447 447 - "num-lines", &error_fatal); 446 446 + &error_fatal); 448 447 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 449 448 dev_splitter = DEVICE(&mms->sec_resp_splitter); 450 449 qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, ··· 475 474 */ 476 475 object_initialize_child(OBJECT(mms), "uart-irq-orgate", 477 476 &mms->uart_irq_orgate, TYPE_OR_IRQ); 478 478 - object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", 477 477 + object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10, 479 478 &error_fatal); 480 479 qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); 481 480 qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, ··· 568 567 569 568 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 570 569 portname = g_strdup_printf("port[%d]", port); 571 571 - object_property_set_link(OBJECT(ppc), OBJECT(mr), 572 572 - portname, &error_fatal); 570 570 + object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 571 571 + &error_fatal); 573 572 g_free(portname); 574 573 } 575 574

+6 -6

hw/arm/mps2.c

··· 203 203 } 204 204 qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); 205 205 qdev_prop_set_bit(armv7m, "enable-bitband", true); 206 206 - object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory), 207 207 - "memory", &error_abort); 206 206 + object_property_set_link(OBJECT(&mms->armv7m), "memory", 207 207 + OBJECT(system_memory), &error_abort); 208 208 sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal); 209 209 210 210 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000); ··· 237 237 DeviceState *orgate_dev; 238 238 239 239 orgate = object_new(TYPE_OR_IRQ); 240 240 - object_property_set_int(orgate, 6, "num-lines", &error_fatal); 240 240 + object_property_set_int(orgate, "num-lines", 6, &error_fatal); 241 241 qdev_realize(DEVICE(orgate), NULL, &error_fatal); 242 242 orgate_dev = DEVICE(orgate); 243 243 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); ··· 273 273 DeviceState *orgate_dev; 274 274 275 275 orgate = object_new(TYPE_OR_IRQ); 276 276 - object_property_set_int(orgate, 10, "num-lines", &error_fatal); 276 276 + object_property_set_int(orgate, "num-lines", 10, &error_fatal); 277 277 qdev_realize(DEVICE(orgate), NULL, &error_fatal); 278 278 orgate_dev = DEVICE(orgate); 279 279 qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); ··· 288 288 DeviceState *txrx_orgate_dev; 289 289 290 290 txrx_orgate = object_new(TYPE_OR_IRQ); 291 291 - object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal); 291 291 + object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal); 292 292 qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal); 293 293 txrx_orgate_dev = DEVICE(txrx_orgate); 294 294 qdev_connect_gpio_out(txrx_orgate_dev, 0, ··· 356 356 int j; 357 357 358 358 orgate = object_new(TYPE_OR_IRQ); 359 359 - object_property_set_int(orgate, 2, "num-lines", &error_fatal); 359 359 + object_property_set_int(orgate, "num-lines", 2, &error_fatal); 360 360 orgate_dev = DEVICE(orgate); 361 361 qdev_realize(orgate_dev, NULL, &error_fatal); 362 362 qdev_connect_gpio_out(orgate_dev, 0,

+4 -4

hw/arm/msf2-soc.c

··· 123 123 qdev_prop_set_uint32(armv7m, "num-irq", 81); 124 124 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 125 125 qdev_prop_set_bit(armv7m, "enable-bitband", true); 126 126 - object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), 127 127 - "memory", &error_abort); 126 126 + object_property_set_link(OBJECT(&s->armv7m), "memory", 127 127 + OBJECT(get_system_memory()), &error_abort); 128 128 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err)) { 129 129 error_propagate(errp, err); 130 130 return; ··· 193 193 } 194 194 195 195 dev = DEVICE(&s->emac); 196 196 - object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()), 197 197 - "ahb-bus", &error_abort); 196 196 + object_property_set_link(OBJECT(&s->emac), "ahb-bus", 197 197 + OBJECT(get_system_memory()), &error_abort); 198 198 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), &err)) { 199 199 error_propagate(errp, err); 200 200 return;

+9 -9

hw/arm/musca.c

··· 256 256 } 257 257 258 258 object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); 259 259 - object_property_set_link(OBJECT(mpc), OBJECT(downstream), 260 260 - "downstream", &error_fatal); 259 259 + object_property_set_link(OBJECT(mpc), "downstream", OBJECT(downstream), 260 260 + &error_fatal); 261 261 sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 262 262 /* Map the upstream end of the MPC into system memory */ 263 263 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); ··· 374 374 object_initialize_child(OBJECT(machine), "sse-200", &mms->sse, 375 375 TYPE_SSE200); 376 376 ssedev = DEVICE(&mms->sse); 377 377 - object_property_set_link(OBJECT(&mms->sse), OBJECT(system_memory), 378 378 - "memory", &error_fatal); 377 377 + object_property_set_link(OBJECT(&mms->sse), "memory", 378 378 + OBJECT(system_memory), &error_fatal); 379 379 qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); 380 380 qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); 381 381 qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); ··· 403 403 &error_fatal, NULL); 404 404 g_free(name); 405 405 406 406 - object_property_set_int(OBJECT(splitter), 2, "num-lines", 406 406 + object_property_set_int(OBJECT(splitter), "num-lines", 2, 407 407 &error_fatal); 408 408 qdev_realize(DEVICE(splitter), NULL, &error_fatal); 409 409 qdev_connect_gpio_out(DEVICE(splitter), 0, ··· 422 422 sizeof(mms->sec_resp_splitter), 423 423 TYPE_SPLIT_IRQ, &error_fatal, NULL); 424 424 425 425 - object_property_set_int(OBJECT(&mms->sec_resp_splitter), 426 426 - ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal); 425 425 + object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines", 426 426 + ARRAY_SIZE(mms->ppc), &error_fatal); 427 427 qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal); 428 428 dev_splitter = DEVICE(&mms->sec_resp_splitter); 429 429 qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0, ··· 541 541 542 542 mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); 543 543 portname = g_strdup_printf("port[%d]", port); 544 544 - object_property_set_link(OBJECT(ppc), OBJECT(mr), 545 545 - portname, &error_fatal); 544 544 + object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), 545 545 + &error_fatal); 546 546 g_free(portname); 547 547 } 548 548

+2 -2

hw/arm/musicpal.c

··· 1690 1690 wm8750_dev = i2c_create_slave(i2c, TYPE_WM8750, MP_WM_ADDR); 1691 1691 dev = qdev_new(TYPE_MV88W8618_AUDIO); 1692 1692 s = SYS_BUS_DEVICE(dev); 1693 1693 - object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev), 1694 1694 - "wm8750", NULL); 1693 1693 + object_property_set_link(OBJECT(dev), "wm8750", OBJECT(wm8750_dev), 1694 1694 + NULL); 1695 1695 sysbus_realize_and_unref(s, &error_fatal); 1696 1696 sysbus_mmio_map(s, 0, MP_AUDIO_BASE); 1697 1697 sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);

+3 -3

hw/arm/nrf51_soc.c

··· 65 65 return; 66 66 } 67 67 68 68 - object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", 68 68 + object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container), 69 69 &error_abort); 70 70 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), &err)) { 71 71 error_propagate(errp, err); ··· 106 106 BASE_TO_IRQ(NRF51_RNG_BASE))); 107 107 108 108 /* UICR, FICR, NVMC, FLASH */ 109 109 - object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size", 109 109 + object_property_set_uint(OBJECT(&s->nvm), "flash-size", s->flash_size, 110 110 &err); 111 111 if (err) { 112 112 error_propagate(errp, err); ··· 141 141 142 142 /* TIMER */ 143 143 for (i = 0; i < NRF51_NUM_TIMERS; i++) { 144 144 - object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err); 144 144 + object_property_set_uint(OBJECT(&s->timer[i]), "id", i, &err); 145 145 if (err) { 146 146 error_propagate(errp, err); 147 147 return;

+6 -7

hw/arm/orangepi.c

··· 63 63 object_unref(OBJECT(h3)); 64 64 65 65 /* Setup timer properties */ 66 66 - object_property_set_int(OBJECT(h3), 32768, "clk0-freq", 67 67 - &error_abort); 68 68 - object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq", 66 66 + object_property_set_int(OBJECT(h3), "clk0-freq", 32768, &error_abort); 67 67 + object_property_set_int(OBJECT(h3), "clk1-freq", 24 * 1000 * 1000, 69 68 &error_abort); 70 69 71 70 /* Setup SID properties. Currently using a default fixed SID identifier. */ ··· 77 76 } 78 77 79 78 /* Setup EMAC properties */ 80 80 - object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort); 79 79 + object_property_set_int(OBJECT(&h3->emac), "phy-addr", 1, &error_abort); 81 80 82 81 /* DRAMC */ 83 83 - object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM], 84 84 - "ram-addr", &error_abort); 85 85 - object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size", 82 82 + object_property_set_uint(OBJECT(h3), "ram-addr", h3->memmap[AW_H3_SDRAM], 83 83 + &error_abort); 84 84 + object_property_set_int(OBJECT(h3), "ram-size", machine->ram_size / MiB, 86 85 &error_abort); 87 86 88 87 /* Mark H3 object realized */

+1 -1

hw/arm/raspi.c

··· 285 285 object_initialize_child(OBJECT(machine), "soc", &s->soc, 286 286 board_soc_type(board_rev)); 287 287 object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram)); 288 288 - object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", 288 288 + object_property_set_int(OBJECT(&s->soc), "board-rev", board_rev, 289 289 &error_abort); 290 290 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 291 291

+3 -3

hw/arm/realview.c

··· 107 107 * before realization. 108 108 */ 109 109 if (object_property_find(cpuobj, "has_el3", NULL)) { 110 110 - object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 110 110 + object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 111 111 } 112 112 113 113 if (is_pb && is_mpcore) { 114 114 - object_property_set_int(cpuobj, periphbase, "reset-cbar", 114 114 + object_property_set_int(cpuobj, "reset-cbar", periphbase, 115 115 &error_fatal); 116 116 } 117 117 ··· 205 205 206 206 /* DMA controller is optional, apparently. */ 207 207 dev = qdev_new("pl081"); 208 208 - object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", 208 208 + object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem), 209 209 &error_fatal); 210 210 busdev = SYS_BUS_DEVICE(dev); 211 211 sysbus_realize_and_unref(busdev, &error_fatal);

+8 -8

hw/arm/sbsa-ref.c

··· 499 499 500 500 dev = qdev_new("arm-smmuv3"); 501 501 502 502 - object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 502 502 + object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 503 503 &error_abort); 504 504 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 505 505 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); ··· 659 659 } 660 660 661 661 cpuobj = object_new(possible_cpus->cpus[n].type); 662 662 - object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 663 663 - "mp-affinity", NULL); 662 662 + object_property_set_int(cpuobj, "mp-affinity", 663 663 + possible_cpus->cpus[n].arch_id, NULL); 664 664 665 665 cs = CPU(cpuobj); 666 666 cs->cpu_index = n; ··· 669 669 &error_fatal); 670 670 671 671 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 672 672 - object_property_set_int(cpuobj, 672 672 + object_property_set_int(cpuobj, "reset-cbar", 673 673 sbsa_ref_memmap[SBSA_CPUPERIPHS].base, 674 674 - "reset-cbar", &error_abort); 674 674 + &error_abort); 675 675 } 676 676 677 677 - object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 677 677 + object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 678 678 &error_abort); 679 679 680 680 - object_property_set_link(cpuobj, OBJECT(secure_sysmem), 681 681 - "secure-memory", &error_abort); 680 680 + object_property_set_link(cpuobj, "secure-memory", 681 681 + OBJECT(secure_sysmem), &error_abort); 682 682 683 683 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 684 684 object_unref(cpuobj);

+2 -2

hw/arm/stellaris.c

··· 1312 1312 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1313 1313 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1314 1314 qdev_prop_set_bit(nvic, "enable-bitband", true); 1315 1315 - object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), 1316 1316 - "memory", &error_abort); 1315 1315 + object_property_set_link(OBJECT(nvic), "memory", 1316 1316 + OBJECT(get_system_memory()), &error_abort); 1317 1317 /* This will exit with an error if the user passed us a bad cpu_type */ 1318 1318 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1319 1319

+4 -4

hw/arm/stm32f205_soc.c

··· 105 105 qdev_prop_set_uint32(armv7m, "num-irq", 96); 106 106 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 107 107 qdev_prop_set_bit(armv7m, "enable-bitband", true); 108 108 - object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), 109 109 - "memory", &error_abort); 108 108 + object_property_set_link(OBJECT(&s->armv7m), "memory", 109 109 + OBJECT(get_system_memory()), &error_abort); 110 110 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err)) { 111 111 error_propagate(errp, err); 112 112 return; ··· 149 149 } 150 150 151 151 /* ADC 1 to 3 */ 152 152 - object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, 153 153 - "num-lines", &error_abort); 152 152 + object_property_set_int(OBJECT(s->adc_irqs), "num-lines", STM_NUM_ADCS, 153 153 + &error_abort); 154 154 if (!qdev_realize(DEVICE(s->adc_irqs), NULL, &err)) { 155 155 error_propagate(errp, err); 156 156 return;

+4 -4

hw/arm/stm32f405_soc.c

··· 116 116 qdev_prop_set_uint32(armv7m, "num-irq", 96); 117 117 qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); 118 118 qdev_prop_set_bit(armv7m, "enable-bitband", true); 119 119 - object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory), 120 120 - "memory", &error_abort); 119 119 + object_property_set_link(OBJECT(&s->armv7m), "memory", 120 120 + OBJECT(system_memory), &error_abort); 121 121 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err)) { 122 122 error_propagate(errp, err); 123 123 return; ··· 167 167 error_propagate(errp, err); 168 168 return; 169 169 } 170 170 - object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS, 171 171 - "num-lines", &error_abort); 170 170 + object_property_set_int(OBJECT(&s->adc_irqs), "num-lines", STM_NUM_ADCS, 171 171 + &error_abort); 172 172 if (!qdev_realize(DEVICE(&s->adc_irqs), NULL, &err)) { 173 173 error_propagate(errp, err); 174 174 return;

+2 -2

hw/arm/versatilepb.c

··· 213 213 * realization. 214 214 */ 215 215 if (object_property_find(cpuobj, "has_el3", NULL)) { 216 216 - object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 216 216 + object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); 217 217 } 218 218 219 219 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); ··· 288 288 pl011_create(0x10009000, sic[6], serial_hd(3)); 289 289 290 290 dev = qdev_new("pl080"); 291 291 - object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", 291 291 + object_property_set_link(OBJECT(dev), "downstream", OBJECT(sysmem), 292 292 &error_fatal); 293 293 busdev = SYS_BUS_DEVICE(dev); 294 294 sysbus_realize_and_unref(busdev, &error_fatal);

+4 -4

hw/arm/vexpress.c

··· 218 218 Object *cpuobj = object_new(cpu_type); 219 219 220 220 if (!secure) { 221 221 - object_property_set_bool(cpuobj, false, "has_el3", NULL); 221 221 + object_property_set_bool(cpuobj, "has_el3", false, NULL); 222 222 } 223 223 if (!virt) { 224 224 if (object_property_find(cpuobj, "has_el2", NULL)) { 225 225 - object_property_set_bool(cpuobj, false, "has_el2", NULL); 225 225 + object_property_set_bool(cpuobj, "has_el2", false, NULL); 226 226 } 227 227 } 228 228 229 229 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 230 230 - object_property_set_int(cpuobj, periphbase, 231 231 - "reset-cbar", &error_abort); 230 230 + object_property_set_int(cpuobj, "reset-cbar", periphbase, 231 231 + &error_abort); 232 232 } 233 233 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 234 234 }

+23 -21

hw/arm/virt.c

··· 594 594 595 595 dev = qdev_new(itsclass); 596 596 597 597 - object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", 597 597 + object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 598 598 &error_abort); 599 599 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 600 600 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); ··· 1175 1175 1176 1176 dev = qdev_new("arm-smmuv3"); 1177 1177 1178 1178 - object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1178 1178 + object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1179 1179 &error_abort); 1180 1180 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1181 1181 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); ··· 1785 1785 } 1786 1786 1787 1787 cpuobj = object_new(possible_cpus->cpus[n].type); 1788 1788 - object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, 1789 1789 - "mp-affinity", NULL); 1788 1788 + object_property_set_int(cpuobj, "mp-affinity", 1789 1789 + possible_cpus->cpus[n].arch_id, NULL); 1790 1790 1791 1791 cs = CPU(cpuobj); 1792 1792 cs->cpu_index = n; ··· 1797 1797 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 1798 1798 1799 1799 if (!vms->secure) { 1800 1800 - object_property_set_bool(cpuobj, false, "has_el3", NULL); 1800 1800 + object_property_set_bool(cpuobj, "has_el3", false, NULL); 1801 1801 } 1802 1802 1803 1803 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { 1804 1804 - object_property_set_bool(cpuobj, false, "has_el2", NULL); 1804 1804 + object_property_set_bool(cpuobj, "has_el2", false, NULL); 1805 1805 } 1806 1806 1807 1807 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 1808 1808 - object_property_set_int(cpuobj, vms->psci_conduit, 1809 1809 - "psci-conduit", NULL); 1808 1808 + object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit, 1809 1809 + NULL); 1810 1810 1811 1811 /* Secondary CPUs start in PSCI powered-down state */ 1812 1812 if (n > 0) { 1813 1813 - object_property_set_bool(cpuobj, true, 1814 1814 - "start-powered-off", NULL); 1813 1813 + object_property_set_bool(cpuobj, "start-powered-off", true, 1814 1814 + NULL); 1815 1815 } 1816 1816 } 1817 1817 1818 1818 if (vmc->kvm_no_adjvtime && 1819 1819 object_property_find(cpuobj, "kvm-no-adjvtime", NULL)) { 1820 1820 - object_property_set_bool(cpuobj, true, "kvm-no-adjvtime", NULL); 1820 1820 + object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 1821 1821 } 1822 1822 1823 1823 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { 1824 1824 - object_property_set_bool(cpuobj, false, "pmu", NULL); 1824 1824 + object_property_set_bool(cpuobj, "pmu", false, NULL); 1825 1825 } 1826 1826 1827 1827 if (object_property_find(cpuobj, "reset-cbar", NULL)) { 1828 1828 - object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, 1829 1829 - "reset-cbar", &error_abort); 1828 1828 + object_property_set_int(cpuobj, "reset-cbar", 1829 1829 + vms->memmap[VIRT_CPUPERIPHS].base, 1830 1830 + &error_abort); 1830 1831 } 1831 1832 1832 1832 - object_property_set_link(cpuobj, OBJECT(sysmem), "memory", 1833 1833 + object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 1833 1834 &error_abort); 1834 1835 if (vms->secure) { 1835 1835 - object_property_set_link(cpuobj, OBJECT(secure_sysmem), 1836 1836 - "secure-memory", &error_abort); 1836 1836 + object_property_set_link(cpuobj, "secure-memory", 1837 1837 + OBJECT(secure_sysmem), &error_abort); 1837 1838 } 1838 1839 1839 1840 /* ··· 1857 1858 } 1858 1859 } 1859 1860 1860 1860 - object_property_set_link(cpuobj, OBJECT(tag_sysmem), 1861 1861 - "tag-memory", &error_abort); 1861 1861 + object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 1862 1862 + &error_abort); 1862 1863 if (vms->secure) { 1863 1863 - object_property_set_link(cpuobj, OBJECT(secure_tag_sysmem), 1864 1864 - "secure-tag-memory", &error_abort); 1864 1864 + object_property_set_link(cpuobj, "secure-tag-memory", 1865 1865 + OBJECT(secure_tag_sysmem), 1866 1866 + &error_abort); 1865 1867 } 1866 1868 } 1867 1869

+3 -3

hw/arm/xilinx_zynq.c

··· 196 196 * realization. 197 197 */ 198 198 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { 199 199 - object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal); 199 199 + object_property_set_bool(OBJECT(cpu), "has_el3", false, &error_fatal); 200 200 } 201 201 202 202 - object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", 202 202 + object_property_set_int(OBJECT(cpu), "midr", ZYNQ_BOARD_MIDR, 203 203 &error_fatal); 204 204 - object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", 204 204 + object_property_set_int(OBJECT(cpu), "reset-cbar", MPCORE_PERIPHBASE, 205 205 &error_fatal); 206 206 qdev_realize(DEVICE(cpu), NULL, &error_fatal); 207 207

+4 -4

hw/arm/xlnx-versal-virt.c

··· 502 502 503 503 object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc, 504 504 TYPE_XLNX_VERSAL); 505 505 - object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram), 506 506 - "ddr", &error_abort); 507 507 - object_property_set_int(OBJECT(&s->soc), psci_conduit, 508 508 - "psci-conduit", &error_abort); 505 505 + object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram), 506 506 + &error_abort); 507 507 + object_property_set_int(OBJECT(&s->soc), "psci-conduit", psci_conduit, 508 508 + &error_abort); 509 509 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 510 510 511 511 fdt_create(s);

+14 -16

hw/arm/xlnx-versal.c

··· 35 35 object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i], 36 36 XLNX_VERSAL_ACPU_TYPE); 37 37 obj = OBJECT(&s->fpd.apu.cpu[i]); 38 38 - object_property_set_int(obj, s->cfg.psci_conduit, 39 39 - "psci-conduit", &error_abort); 38 38 + object_property_set_int(obj, "psci-conduit", s->cfg.psci_conduit, 39 39 + &error_abort); 40 40 if (i) { 41 41 /* Secondary CPUs start in PSCI powered-down state */ 42 42 - object_property_set_bool(obj, true, 43 43 - "start-powered-off", &error_abort); 42 42 + object_property_set_bool(obj, "start-powered-off", true, 43 43 + &error_abort); 44 44 } 45 45 46 46 - object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu), 47 47 - "core-count", &error_abort); 48 48 - object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory", 46 46 + object_property_set_int(obj, "core-count", ARRAY_SIZE(s->fpd.apu.cpu), 47 47 + &error_abort); 48 48 + object_property_set_link(obj, "memory", OBJECT(&s->fpd.apu.mr), 49 49 &error_abort); 50 50 qdev_realize(DEVICE(obj), NULL, &error_fatal); 51 51 } ··· 164 164 qemu_check_nic_model(nd, "cadence_gem"); 165 165 qdev_set_nic_properties(dev, nd); 166 166 } 167 167 - object_property_set_int(OBJECT(dev), 168 168 - 2, "num-priority-queues", 167 167 + object_property_set_int(OBJECT(dev), "num-priority-queues", 2, 169 168 &error_abort); 170 170 - object_property_set_link(OBJECT(dev), 171 171 - OBJECT(&s->mr_ps), "dma", 169 169 + object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), 172 170 &error_abort); 173 171 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 174 172 ··· 192 190 object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i], 193 191 TYPE_XLNX_ZDMA); 194 192 dev = DEVICE(&s->lpd.iou.adma[i]); 195 195 - object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort); 193 193 + object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort); 196 194 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 197 195 198 196 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); ··· 217 215 TYPE_SYSBUS_SDHCI); 218 216 dev = DEVICE(&s->pmc.iou.sd[i]); 219 217 220 220 - object_property_set_uint(OBJECT(dev), 221 221 - 3, "sd-spec-version", &error_fatal); 222 222 - object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg", 218 218 + object_property_set_uint(OBJECT(dev), "sd-spec-version", 3, 223 219 &error_fatal); 224 224 - object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal); 220 220 + object_property_set_uint(OBJECT(dev), "capareg", SDHCI_CAPABILITIES, 221 221 + &error_fatal); 222 222 + object_property_set_uint(OBJECT(dev), "uhs", UHS_I, &error_fatal); 225 223 sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 226 224 227 225 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

+4 -4

hw/arm/xlnx-zcu102.c

··· 118 118 119 119 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_XLNX_ZYNQMP); 120 120 121 121 - object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram), 122 122 - "ddr-ram", &error_abort); 123 123 - object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", 121 121 + object_property_set_link(OBJECT(&s->soc), "ddr-ram", OBJECT(machine->ram), 122 122 + &error_abort); 123 123 + object_property_set_bool(OBJECT(&s->soc), "secure", s->secure, 124 124 &error_fatal); 125 125 - object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization", 125 125 + object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt, 126 126 &error_fatal); 127 127 128 128 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);

+23 -23

hw/arm/xlnx-zynqmp.c

··· 200 200 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); 201 201 if (strcmp(name, boot_cpu)) { 202 202 /* Secondary CPUs start in PSCI powered-down state */ 203 203 - object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, 204 204 - "start-powered-off", &error_abort); 203 203 + object_property_set_bool(OBJECT(&s->rpu_cpu[i]), 204 204 + "start-powered-off", true, &error_abort); 205 205 } else { 206 206 s->boot_cpu_ptr = &s->rpu_cpu[i]; 207 207 } 208 208 g_free(name); 209 209 210 210 - object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", 210 210 + object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, 211 211 &error_abort); 212 212 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, &err)) { 213 213 error_propagate(errp, err); ··· 345 345 for (i = 0; i < num_apus; i++) { 346 346 char *name; 347 347 348 348 - object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, 349 349 - "psci-conduit", &error_abort); 348 348 + object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit", 349 349 + QEMU_PSCI_CONDUIT_SMC, &error_abort); 350 350 351 351 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); 352 352 if (strcmp(name, boot_cpu)) { 353 353 /* Secondary CPUs start in PSCI powered-down state */ 354 354 - object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, 355 355 - "start-powered-off", &error_abort); 354 354 + object_property_set_bool(OBJECT(&s->apu_cpu[i]), 355 355 + "start-powered-off", true, &error_abort); 356 356 } else { 357 357 s->boot_cpu_ptr = &s->apu_cpu[i]; 358 358 } 359 359 g_free(name); 360 360 361 361 - object_property_set_bool(OBJECT(&s->apu_cpu[i]), 362 362 - s->secure, "has_el3", NULL); 363 363 - object_property_set_bool(OBJECT(&s->apu_cpu[i]), 364 364 - s->virt, "has_el2", NULL); 365 365 - object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, 366 366 - "reset-cbar", &error_abort); 367 367 - object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus, 368 368 - "core-count", &error_abort); 361 361 + object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure, 362 362 + NULL); 363 363 + object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt, 364 364 + NULL); 365 365 + object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar", 366 366 + GIC_BASE_ADDR, &error_abort); 367 367 + object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", 368 368 + num_apus, &error_abort); 369 369 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, &err)) { 370 370 error_propagate(errp, err); 371 371 return; ··· 463 463 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 464 464 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); 465 465 } 466 466 - object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision", 466 466 + object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, 467 467 &error_abort); 468 468 - object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues", 468 468 + object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, 469 469 &error_abort); 470 470 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), &err)) { 471 471 error_propagate(errp, err); ··· 487 487 gic_spi[uart_intr[i]]); 488 488 } 489 489 490 490 - object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", 490 490 + object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, 491 491 &error_abort); 492 492 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err)) { 493 493 error_propagate(errp, err); ··· 507 507 * - SDIO Specification Version 3.0 508 508 * - eMMC Specification Version 4.51 509 509 */ 510 510 - object_property_set_uint(sdhci, 3, "sd-spec-version", &err); 510 510 + object_property_set_uint(sdhci, "sd-spec-version", 3, &err); 511 511 if (err) { 512 512 error_propagate(errp, err); 513 513 return; 514 514 } 515 515 - object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err); 515 515 + object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, &err); 516 516 if (err) { 517 517 error_propagate(errp, err); 518 518 return; 519 519 } 520 520 - object_property_set_uint(sdhci, UHS_I, "uhs", &err); 520 520 + object_property_set_uint(sdhci, "uhs", UHS_I, &err); 521 521 if (err) { 522 522 error_propagate(errp, err); 523 523 return; ··· 586 586 error_propagate(errp, err); 587 587 return; 588 588 } 589 589 - object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma", 589 589 + object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma), 590 590 &error_abort); 591 591 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); 592 592 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); ··· 606 606 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); 607 607 608 608 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { 609 609 - object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err); 609 609 + object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, &err); 610 610 if (err) { 611 611 error_propagate(errp, err); 612 612 return;

+4 -5

hw/block/xen-block.c

··· 935 935 xendev = XEN_DEVICE(qdev_new(type)); 936 936 blockdev = XEN_BLOCK_DEVICE(xendev); 937 937 938 938 - object_property_set_str(OBJECT(xendev), vdev, "vdev", &local_err); 938 938 + object_property_set_str(OBJECT(xendev), "vdev", vdev, &local_err); 939 939 if (local_err) { 940 940 error_propagate_prepend(errp, local_err, "failed to set 'vdev': "); 941 941 goto fail; 942 942 } 943 943 944 944 - object_property_set_str(OBJECT(xendev), 945 945 - xen_block_drive_get_node_name(drive), "drive", 946 946 - &local_err); 944 944 + object_property_set_str(OBJECT(xendev), "drive", 945 945 + xen_block_drive_get_node_name(drive), &local_err); 947 946 if (local_err) { 948 947 error_propagate_prepend(errp, local_err, "failed to set 'drive': "); 949 948 goto fail; 950 949 } 951 950 952 952 - object_property_set_str(OBJECT(xendev), iothread->id, "iothread", 951 951 + object_property_set_str(OBJECT(xendev), "iothread", iothread->id, 953 952 &local_err); 954 953 if (local_err) { 955 954 error_propagate_prepend(errp, local_err,

+4 -4

hw/core/bus.c

··· 25 25 26 26 void qbus_set_hotplug_handler(BusState *bus, Object *handler) 27 27 { 28 28 - object_property_set_link(OBJECT(bus), handler, 29 29 - QDEV_HOTPLUG_HANDLER_PROPERTY, &error_abort); 28 28 + object_property_set_link(OBJECT(bus), QDEV_HOTPLUG_HANDLER_PROPERTY, 29 29 + handler, &error_abort); 30 30 } 31 31 32 32 void qbus_set_bus_hotplug_handler(BusState *bus) ··· 168 168 { 169 169 Error *err = NULL; 170 170 171 171 - object_property_set_bool(OBJECT(bus), true, "realized", &err); 171 171 + object_property_set_bool(OBJECT(bus), "realized", true, &err); 172 172 error_propagate(errp, err); 173 173 return !err; 174 174 } 175 175 176 176 void qbus_unrealize(BusState *bus) 177 177 { 178 178 - object_property_set_bool(OBJECT(bus), false, "realized", &error_abort); 178 178 + object_property_set_bool(OBJECT(bus), "realized", false, &error_abort); 179 179 } 180 180 181 181 static bool bus_get_realized(Object *obj, Error **errp)

+2 -2

hw/core/numa.c

··· 810 810 /* due to bug in libvirt, it doesn't pass node-id from props on 811 811 * device_add as expected, so we have to fix it up here */ 812 812 if (slot->props.has_node_id) { 813 813 - object_property_set_int(OBJECT(dev), slot->props.node_id, 814 814 - "node-id", errp); 813 813 + object_property_set_int(OBJECT(dev), "node-id", 814 814 + slot->props.node_id, errp); 815 815 } 816 816 } else if (node_id != slot->props.node_id) { 817 817 error_setg(errp, "invalid node-id, must be %"PRId64,

+5 -5

hw/core/qdev-properties-system.c

··· 436 436 } 437 437 } 438 438 439 439 - object_property_set_str(OBJECT(dev), ref, name, errp); 439 439 + object_property_set_str(OBJECT(dev), name, ref, errp); 440 440 } 441 441 442 442 void qdev_prop_set_drive(DeviceState *dev, const char *name, ··· 449 449 Chardev *value) 450 450 { 451 451 assert(!value || value->label); 452 452 - object_property_set_str(OBJECT(dev), 453 453 - value ? value->label : "", name, &error_abort); 452 452 + object_property_set_str(OBJECT(dev), name, value ? value->label : "", 453 453 + &error_abort); 454 454 } 455 455 456 456 void qdev_prop_set_netdev(DeviceState *dev, const char *name, 457 457 NetClientState *value) 458 458 { 459 459 assert(!value || value->name); 460 460 - object_property_set_str(OBJECT(dev), 461 461 - value ? value->name : "", name, &error_abort); 460 460 + object_property_set_str(OBJECT(dev), name, value ? value->name : "", 461 461 + &error_abort); 462 462 } 463 463 464 464 void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd)

+10 -10

hw/core/qdev-properties.c

··· 1256 1256 1257 1257 void qdev_prop_set_bit(DeviceState *dev, const char *name, bool value) 1258 1258 { 1259 1259 - object_property_set_bool(OBJECT(dev), value, name, &error_abort); 1259 1259 + object_property_set_bool(OBJECT(dev), name, value, &error_abort); 1260 1260 } 1261 1261 1262 1262 void qdev_prop_set_uint8(DeviceState *dev, const char *name, uint8_t value) 1263 1263 { 1264 1264 - object_property_set_int(OBJECT(dev), value, name, &error_abort); 1264 1264 + object_property_set_int(OBJECT(dev), name, value, &error_abort); 1265 1265 } 1266 1266 1267 1267 void qdev_prop_set_uint16(DeviceState *dev, const char *name, uint16_t value) 1268 1268 { 1269 1269 - object_property_set_int(OBJECT(dev), value, name, &error_abort); 1269 1269 + object_property_set_int(OBJECT(dev), name, value, &error_abort); 1270 1270 } 1271 1271 1272 1272 void qdev_prop_set_uint32(DeviceState *dev, const char *name, uint32_t value) 1273 1273 { 1274 1274 - object_property_set_int(OBJECT(dev), value, name, &error_abort); 1274 1274 + object_property_set_int(OBJECT(dev), name, value, &error_abort); 1275 1275 } 1276 1276 1277 1277 void qdev_prop_set_int32(DeviceState *dev, const char *name, int32_t value) 1278 1278 { 1279 1279 - object_property_set_int(OBJECT(dev), value, name, &error_abort); 1279 1279 + object_property_set_int(OBJECT(dev), name, value, &error_abort); 1280 1280 } 1281 1281 1282 1282 void qdev_prop_set_uint64(DeviceState *dev, const char *name, uint64_t value) 1283 1283 { 1284 1284 - object_property_set_int(OBJECT(dev), value, name, &error_abort); 1284 1284 + object_property_set_int(OBJECT(dev), name, value, &error_abort); 1285 1285 } 1286 1286 1287 1287 void qdev_prop_set_string(DeviceState *dev, const char *name, const char *value) 1288 1288 { 1289 1289 - object_property_set_str(OBJECT(dev), value, name, &error_abort); 1289 1289 + object_property_set_str(OBJECT(dev), name, value, &error_abort); 1290 1290 } 1291 1291 1292 1292 void qdev_prop_set_macaddr(DeviceState *dev, const char *name, ··· 1296 1296 snprintf(str, sizeof(str), "%02x:%02x:%02x:%02x:%02x:%02x", 1297 1297 value[0], value[1], value[2], value[3], value[4], value[5]); 1298 1298 1299 1299 - object_property_set_str(OBJECT(dev), str, name, &error_abort); 1299 1299 + object_property_set_str(OBJECT(dev), name, str, &error_abort); 1300 1300 } 1301 1301 1302 1302 void qdev_prop_set_enum(DeviceState *dev, const char *name, int value) ··· 1304 1304 Property *prop; 1305 1305 1306 1306 prop = qdev_prop_find(dev, name); 1307 1307 - object_property_set_str(OBJECT(dev), 1307 1307 + object_property_set_str(OBJECT(dev), name, 1308 1308 qapi_enum_lookup(prop->info->enum_table, value), 1309 1309 - name, &error_abort); 1309 1309 + &error_abort); 1310 1310 } 1311 1311 1312 1312 static GPtrArray *global_props(void)

+4 -4

hw/core/qdev.c

··· 398 398 assert(!DEVICE_GET_CLASS(dev)->bus_type); 399 399 } 400 400 401 401 - object_property_set_bool(OBJECT(dev), true, "realized", &err); 401 401 + object_property_set_bool(OBJECT(dev), "realized", true, &err); 402 402 if (err) { 403 403 error_propagate(errp, err); 404 404 } ··· 426 426 427 427 void qdev_unrealize(DeviceState *dev) 428 428 { 429 429 - object_property_set_bool(OBJECT(dev), false, "realized", &error_abort); 429 429 + object_property_set_bool(OBJECT(dev), "realized", false, &error_abort); 430 430 } 431 431 432 432 static int qdev_assert_realized_properly(Object *obj, void *opaque) ··· 567 567 "/unattached"), 568 568 "non-qdev-gpio[*]", OBJECT(pin)); 569 569 } 570 570 - object_property_set_link(OBJECT(dev), OBJECT(pin), propname, &error_abort); 570 570 + object_property_set_link(OBJECT(dev), propname, OBJECT(pin), &error_abort); 571 571 g_free(propname); 572 572 } 573 573 ··· 593 593 qemu_irq ret = (qemu_irq)object_property_get_link(OBJECT(dev), propname, 594 594 NULL); 595 595 if (ret) { 596 596 - object_property_set_link(OBJECT(dev), NULL, propname, NULL); 596 596 + object_property_set_link(OBJECT(dev), propname, NULL, NULL); 597 597 } 598 598 g_free(propname); 599 599 return ret;

+2 -3

hw/display/virtio-gpu-pci.c

··· 40 40 } 41 41 42 42 for (i = 0; i < g->conf.max_outputs; i++) { 43 43 - object_property_set_link(OBJECT(g->scanout[i].con), 44 44 - OBJECT(vpci_dev), 45 45 - "device", &error_abort); 43 43 + object_property_set_link(OBJECT(g->scanout[i].con), "device", 44 44 + OBJECT(vpci_dev), &error_abort); 46 45 } 47 46 } 48 47

+2 -3

hw/display/virtio-vga.c

··· 151 151 graphic_console_set_hwops(vga->con, &virtio_vga_base_ops, vvga); 152 152 153 153 for (i = 0; i < g->conf.max_outputs; i++) { 154 154 - object_property_set_link(OBJECT(g->scanout[i].con), 155 155 - OBJECT(vpci_dev), 156 156 - "device", &error_abort); 154 154 + object_property_set_link(OBJECT(g->scanout[i].con), "device", 155 155 + OBJECT(vpci_dev), &error_abort); 157 156 } 158 157 } 159 158

+3 -3

hw/dma/sparc32_dma.c

··· 346 346 d = qdev_new(TYPE_LANCE); 347 347 object_property_add_child(OBJECT(dev), "lance", OBJECT(d)); 348 348 qdev_set_nic_properties(d, nd); 349 349 - object_property_set_link(OBJECT(d), OBJECT(dev), "dma", &error_abort); 349 349 + object_property_set_link(OBJECT(d), "dma", OBJECT(dev), &error_abort); 350 350 sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal); 351 351 } 352 352 ··· 379 379 } 380 380 381 381 espdma = qdev_new(TYPE_SPARC32_ESPDMA_DEVICE); 382 382 - object_property_set_link(OBJECT(espdma), iommu, "iommu", &error_abort); 382 382 + object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort); 383 383 object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma)); 384 384 sysbus_realize_and_unref(SYS_BUS_DEVICE(espdma), &error_fatal); 385 385 ··· 394 394 sysbus_mmio_get_region(sbd, 0)); 395 395 396 396 ledma = qdev_new(TYPE_SPARC32_LEDMA_DEVICE); 397 397 - object_property_set_link(OBJECT(ledma), iommu, "iommu", &error_abort); 397 397 + object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort); 398 398 object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma)); 399 399 sysbus_realize_and_unref(SYS_BUS_DEVICE(ledma), &error_fatal); 400 400

+2 -2

hw/dma/xilinx_axidma.c

··· 547 547 (Object **)&cs->dma, 548 548 object_property_allow_set_link, 549 549 OBJ_PROP_LINK_STRONG); 550 550 - object_property_set_link(OBJECT(ds), OBJECT(s), "dma", &error_abort); 551 551 - object_property_set_link(OBJECT(cs), OBJECT(s), "dma", &error_abort); 550 550 + object_property_set_link(OBJECT(ds), "dma", OBJECT(s), &error_abort); 551 551 + object_property_set_link(OBJECT(cs), "dma", OBJECT(s), &error_abort); 552 552 553 553 for (i = 0; i < 2; i++) { 554 554 struct Stream *st = &s->streams[i];

+4 -4

hw/i386/pc.c

··· 640 640 (Object **)&x86ms->rtc, 641 641 object_property_allow_set_link, 642 642 OBJ_PROP_LINK_STRONG); 643 643 - object_property_set_link(OBJECT(pcms), OBJECT(s), 644 644 - "rtc_state", &error_abort); 643 643 + object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 644 644 + &error_abort); 645 645 646 646 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 647 647 ··· 1143 1143 vmmouse = NULL; 1144 1144 } 1145 1145 if (vmmouse) { 1146 1146 - object_property_set_link(OBJECT(vmmouse), OBJECT(i8042), 1147 1147 - "i8042", &error_abort); 1146 1146 + object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1147 1147 + &error_abort); 1148 1148 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1149 1149 } 1150 1150 port92 = isa_create_simple(isa_bus, TYPE_PORT92);

+2 -2

hw/i386/pc_piix.c

··· 293 293 (Object **)&pcms->acpi_dev, 294 294 object_property_allow_set_link, 295 295 OBJ_PROP_LINK_STRONG); 296 296 - object_property_set_link(OBJECT(machine), OBJECT(piix4_pm), 297 297 - PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 296 296 + object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 297 297 + OBJECT(piix4_pm), &error_abort); 298 298 } 299 299 300 300 if (machine->nvdimms_state->is_enabled) {

+14 -14

hw/i386/pc_q35.c

··· 217 217 q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); 218 218 219 219 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); 220 220 - object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory), 221 221 - MCH_HOST_PROP_RAM_MEM, NULL); 222 222 - object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory), 223 223 - MCH_HOST_PROP_PCI_MEM, NULL); 224 224 - object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()), 225 225 - MCH_HOST_PROP_SYSTEM_MEM, NULL); 226 226 - object_property_set_link(OBJECT(q35_host), OBJECT(system_io), 227 227 - MCH_HOST_PROP_IO_MEM, NULL); 228 228 - object_property_set_int(OBJECT(q35_host), x86ms->below_4g_mem_size, 229 229 - PCI_HOST_BELOW_4G_MEM_SIZE, NULL); 230 230 - object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size, 231 231 - PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); 220 220 + object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, 221 221 + OBJECT(ram_memory), NULL); 222 222 + object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, 223 223 + OBJECT(pci_memory), NULL); 224 224 + object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, 225 225 + OBJECT(get_system_memory()), NULL); 226 226 + object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, 227 227 + OBJECT(system_io), NULL); 228 228 + object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, 229 229 + x86ms->below_4g_mem_size, NULL); 230 230 + object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, 231 231 + x86ms->above_4g_mem_size, NULL); 232 232 /* pci */ 233 233 sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); 234 234 phb = PCI_HOST_BRIDGE(q35_host); ··· 243 243 (Object **)&pcms->acpi_dev, 244 244 object_property_allow_set_link, 245 245 OBJ_PROP_LINK_STRONG); 246 246 - object_property_set_link(OBJECT(machine), OBJECT(lpc), 247 247 - PC_MACHINE_ACPI_DEVICE_PROP, &error_abort); 246 246 + object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP, 247 247 + OBJECT(lpc), &error_abort); 248 248 249 249 /* irq lines */ 250 250 gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);

+1 -1

hw/i386/x86.c

··· 121 121 Error *local_err = NULL; 122 122 Object *cpu = object_new(MACHINE(x86ms)->cpu_type); 123 123 124 124 - object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 124 124 + object_property_set_uint(cpu, "apic-id", apic_id, &local_err); 125 125 if (local_err) { 126 126 goto out; 127 127 }

+1 -1

hw/ide/qdev.c

··· 269 269 object_property_add(obj, "bootindex", "int32", 270 270 ide_dev_get_bootindex, 271 271 ide_dev_set_bootindex, NULL, NULL); 272 272 - object_property_set_int(obj, -1, "bootindex", NULL); 272 272 + object_property_set_int(obj, "bootindex", -1, NULL); 273 273 } 274 274 275 275 static void ide_hd_realize(IDEDevice *dev, Error **errp)

+4 -5

hw/intc/pnv_xive.c

··· 1829 1829 * resized dynamically when the controller is configured by the FW 1830 1830 * to limit accesses to resources not provisioned. 1831 1831 */ 1832 1832 - object_property_set_int(OBJECT(xsrc), PNV_XIVE_NR_IRQS, "nr-irqs", 1832 1832 + object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE_NR_IRQS, 1833 1833 &error_fatal); 1834 1834 - object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive", 1835 1835 - &error_abort); 1834 1834 + object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), &error_abort); 1836 1835 if (!qdev_realize(DEVICE(xsrc), NULL, &local_err)) { 1837 1836 error_propagate(errp, local_err); 1838 1837 return; 1839 1838 } 1840 1839 1841 1841 - object_property_set_int(OBJECT(end_xsrc), PNV_XIVE_NR_ENDS, "nr-ends", 1840 1840 + object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE_NR_ENDS, 1842 1841 &error_fatal); 1843 1843 - object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive", 1842 1842 + object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 1844 1843 &error_abort); 1845 1844 if (!qdev_realize(DEVICE(end_xsrc), NULL, &local_err)) { 1846 1845 error_propagate(errp, local_err);

+4 -5

hw/intc/spapr_xive.c

··· 308 308 /* 309 309 * Initialize the internal sources, for IPIs and virtual devices. 310 310 */ 311 311 - object_property_set_int(OBJECT(xsrc), xive->nr_irqs, "nr-irqs", 311 311 + object_property_set_int(OBJECT(xsrc), "nr-irqs", xive->nr_irqs, 312 312 &error_fatal); 313 313 - object_property_set_link(OBJECT(xsrc), OBJECT(xive), "xive", 314 314 - &error_abort); 313 313 + object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), &error_abort); 315 314 if (!qdev_realize(DEVICE(xsrc), NULL, &local_err)) { 316 315 error_propagate(errp, local_err); 317 316 return; ··· 321 320 /* 322 321 * Initialize the END ESB source 323 322 */ 324 324 - object_property_set_int(OBJECT(end_xsrc), xive->nr_irqs, "nr-ends", 323 323 + object_property_set_int(OBJECT(end_xsrc), "nr-ends", xive->nr_irqs, 325 324 &error_fatal); 326 326 - object_property_set_link(OBJECT(end_xsrc), OBJECT(xive), "xive", 325 325 + object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 327 326 &error_abort); 328 327 if (!qdev_realize(DEVICE(end_xsrc), NULL, &local_err)) { 329 328 error_propagate(errp, local_err);

+2 -2

hw/intc/xics.c

··· 382 382 obj = object_new(type); 383 383 object_property_add_child(cpu, type, obj); 384 384 object_unref(obj); 385 385 - object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort); 386 386 - object_property_set_link(obj, cpu, ICP_PROP_CPU, &error_abort); 385 385 + object_property_set_link(obj, ICP_PROP_XICS, OBJECT(xi), &error_abort); 386 386 + object_property_set_link(obj, ICP_PROP_CPU, cpu, &error_abort); 387 387 if (!qdev_realize(DEVICE(obj), NULL, &local_err)) { 388 388 object_unparent(obj); 389 389 error_propagate(errp, local_err);

+2 -2

hw/intc/xive.c

··· 763 763 obj = object_new(TYPE_XIVE_TCTX); 764 764 object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); 765 765 object_unref(obj); 766 766 - object_property_set_link(obj, cpu, "cpu", &error_abort); 767 767 - object_property_set_link(obj, OBJECT(xptr), "presenter", &error_abort); 766 766 + object_property_set_link(obj, "cpu", cpu, &error_abort); 767 767 + object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); 768 768 if (!qdev_realize(DEVICE(obj), NULL, &local_err)) { 769 769 goto error; 770 770 }

+2 -2

hw/m68k/q800.c

··· 262 262 qdev_set_nic_properties(dev, &nd_table[0]); 263 263 qdev_prop_set_uint8(dev, "it_shift", 2); 264 264 qdev_prop_set_bit(dev, "big_endian", true); 265 265 - object_property_set_link(OBJECT(dev), OBJECT(get_system_memory()), 266 266 - "dma_mr", &error_abort); 265 265 + object_property_set_link(OBJECT(dev), "dma_mr", 266 266 + OBJECT(get_system_memory()), &error_abort); 267 267 sysbus = SYS_BUS_DEVICE(dev); 268 268 sysbus_realize_and_unref(sysbus, &error_fatal); 269 269 sysbus_mmio_map(sysbus, 0, SONIC_BASE);

+2 -2

hw/mem/pc-dimm.c

··· 54 54 if (local_err) { 55 55 goto out; 56 56 } 57 57 - object_property_set_int(OBJECT(dimm), slot, PC_DIMM_SLOT_PROP, 57 57 + object_property_set_int(OBJECT(dimm), PC_DIMM_SLOT_PROP, slot, 58 58 &error_abort); 59 59 trace_mhp_pc_dimm_assigned_slot(slot); 60 60 ··· 225 225 static void pc_dimm_md_set_addr(MemoryDeviceState *md, uint64_t addr, 226 226 Error **errp) 227 227 { 228 228 - object_property_set_uint(OBJECT(md), addr, PC_DIMM_ADDR_PROP, errp); 228 228 + object_property_set_uint(OBJECT(md), PC_DIMM_ADDR_PROP, addr, errp); 229 229 } 230 230 231 231 static MemoryRegion *pc_dimm_md_get_memory_region(MemoryDeviceState *md,

+12 -12

hw/microblaze/petalogix_ml605_mmu.c

··· 83 83 84 84 /* init CPUs */ 85 85 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); 86 86 - object_property_set_str(OBJECT(cpu), "8.10.a", "version", &error_abort); 86 86 + object_property_set_str(OBJECT(cpu), "version", "8.10.a", &error_abort); 87 87 /* Use FPU but don't use floating point conversion and square 88 88 * root instructions 89 89 */ 90 90 - object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort); 91 91 - object_property_set_bool(OBJECT(cpu), true, "dcache-writeback", 90 90 + object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort); 91 91 + object_property_set_bool(OBJECT(cpu), "dcache-writeback", true, 92 92 &error_abort); 93 93 - object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort); 93 93 + object_property_set_bool(OBJECT(cpu), "endianness", true, &error_abort); 94 94 qdev_realize(DEVICE(cpu), NULL, &error_abort); 95 95 96 96 /* Attach emulated BRAM through the LMB. */ ··· 148 148 qdev_set_nic_properties(eth0, &nd_table[0]); 149 149 qdev_prop_set_uint32(eth0, "rxmem", 0x1000); 150 150 qdev_prop_set_uint32(eth0, "txmem", 0x1000); 151 151 - object_property_set_link(OBJECT(eth0), ds, 152 152 - "axistream-connected", &error_abort); 153 153 - object_property_set_link(OBJECT(eth0), cs, 154 154 - "axistream-control-connected", &error_abort); 151 151 + object_property_set_link(OBJECT(eth0), "axistream-connected", ds, 152 152 + &error_abort); 153 153 + object_property_set_link(OBJECT(eth0), "axistream-control-connected", cs, 154 154 + &error_abort); 155 155 sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal); 156 156 sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR); 157 157 sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]); ··· 161 161 cs = object_property_get_link(OBJECT(eth0), 162 162 "axistream-control-connected-target", NULL); 163 163 qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000); 164 164 - object_property_set_link(OBJECT(dma), ds, 165 165 - "axistream-connected", &error_abort); 166 166 - object_property_set_link(OBJECT(dma), cs, 167 167 - "axistream-control-connected", &error_abort); 164 164 + object_property_set_link(OBJECT(dma), "axistream-connected", ds, 165 165 + &error_abort); 166 166 + object_property_set_link(OBJECT(dma), "axistream-control-connected", cs, 167 167 + &error_abort); 168 168 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 169 169 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); 170 170 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);

+1 -1

hw/microblaze/petalogix_s3adsp1800_mmu.c

··· 70 70 MemoryRegion *sysmem = get_system_memory(); 71 71 72 72 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); 73 73 - object_property_set_str(OBJECT(cpu), "7.10.d", "version", &error_abort); 73 73 + object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort); 74 74 qdev_realize(DEVICE(cpu), NULL, &error_abort); 75 75 76 76 /* Attach emulated BRAM through the LMB. */

+15 -15

hw/microblaze/xlnx-zynqmp-pmu.c

··· 78 78 XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev); 79 79 Error *err = NULL; 80 80 81 81 - object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR, 82 82 - "base-vectors", &error_abort); 83 83 - object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection", 81 81 + object_property_set_uint(OBJECT(&s->cpu), "base-vectors", 82 82 + XLNX_ZYNQMP_PMU_ROM_ADDR, &error_abort); 83 83 + object_property_set_bool(OBJECT(&s->cpu), "use-stack-protection", true, 84 84 &error_abort); 85 85 - object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort); 86 86 - object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort); 87 87 - object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel", 85 85 + object_property_set_uint(OBJECT(&s->cpu), "use-fpu", 0, &error_abort); 86 86 + object_property_set_uint(OBJECT(&s->cpu), "use-hw-mul", 0, &error_abort); 87 87 + object_property_set_bool(OBJECT(&s->cpu), "use-barrel", true, 88 88 &error_abort); 89 89 - object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr", 89 89 + object_property_set_bool(OBJECT(&s->cpu), "use-msr-instr", true, 90 90 &error_abort); 91 91 - object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr", 91 91 + object_property_set_bool(OBJECT(&s->cpu), "use-pcmp-instr", true, 92 92 &error_abort); 93 93 - object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort); 94 94 - object_property_set_bool(OBJECT(&s->cpu), true, "endianness", 93 93 + object_property_set_bool(OBJECT(&s->cpu), "use-mmu", false, &error_abort); 94 94 + object_property_set_bool(OBJECT(&s->cpu), "endianness", true, 95 95 &error_abort); 96 96 - object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version", 96 96 + object_property_set_str(OBJECT(&s->cpu), "version", "8.40.b", 97 97 &error_abort); 98 98 - object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort); 98 98 + object_property_set_uint(OBJECT(&s->cpu), "pvr", 0, &error_abort); 99 99 if (!qdev_realize(DEVICE(&s->cpu), NULL, &err)) { 100 100 error_propagate(errp, err); 101 101 return; 102 102 } 103 103 104 104 - object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size", 104 104 + object_property_set_uint(OBJECT(&s->intc), "intc-intr-size", 0x10, 105 105 &error_abort); 106 106 - object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge", 106 106 + object_property_set_uint(OBJECT(&s->intc), "intc-level-edge", 0x0, 107 107 &error_abort); 108 108 - object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive", 108 108 + object_property_set_uint(OBJECT(&s->intc), "intc-positive", 0xffff, 109 109 &error_abort); 110 110 if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), &err)) { 111 111 error_propagate(errp, err);

+2 -2

hw/mips/boston.c

··· 455 455 is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); 456 456 457 457 object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); 458 458 - object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type", 458 458 + object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, 459 459 &error_fatal); 460 460 - object_property_set_int(OBJECT(&s->cps), machine->smp.cpus, "num-vp", 460 460 + object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, 461 461 &error_fatal); 462 462 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 463 463

+12 -12

hw/mips/cps.c

··· 100 100 /* Inter-Thread Communication Unit */ 101 101 if (itu_present) { 102 102 object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); 103 103 - object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", 103 103 + object_property_set_int(OBJECT(&s->itu), "num-fifo", 16, 104 104 &error_abort); 105 105 - object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", 105 105 + object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16, 106 106 &error_abort); 107 107 - object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present", 107 107 + object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present, 108 108 &error_abort); 109 109 if (saar_present) { 110 110 s->itu.saar = &env->CP0_SAAR; ··· 120 120 121 121 /* Cluster Power Controller */ 122 122 object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); 123 123 - object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", 123 123 + object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp, 124 124 &error_abort); 125 125 - object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", 125 125 + object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1, 126 126 &error_abort); 127 127 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), &err)) { 128 128 error_propagate(errp, err); ··· 134 134 135 135 /* Global Interrupt Controller */ 136 136 object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); 137 137 - object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", 137 137 + object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp, 138 138 &error_abort); 139 139 - object_property_set_int(OBJECT(&s->gic), 128, "num-irq", 139 139 + object_property_set_int(OBJECT(&s->gic), "num-irq", 128, 140 140 &error_abort); 141 141 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err)) { 142 142 error_propagate(errp, err); ··· 150 150 gcr_base = env->CP0_CMGCRBase << 4; 151 151 152 152 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); 153 153 - object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", 153 153 + object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp, 154 154 &error_abort); 155 155 - object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", 155 155 + object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, 156 156 &error_abort); 157 157 - object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", 157 157 + object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base, 158 158 &error_abort); 159 159 - object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", 159 159 + object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr), 160 160 &error_abort); 161 161 - object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", 161 161 + object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), 162 162 &error_abort); 163 163 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), &err)) { 164 164 error_propagate(errp, err);

+2 -2

hw/mips/jazz.c

··· 290 290 dev = qdev_new("dp8393x"); 291 291 qdev_set_nic_properties(dev, nd); 292 292 qdev_prop_set_uint8(dev, "it_shift", 2); 293 293 - object_property_set_link(OBJECT(dev), OBJECT(rc4030_dma_mr), 294 294 - "dma_mr", &error_abort); 293 293 + object_property_set_link(OBJECT(dev), "dma_mr", 294 294 + OBJECT(rc4030_dma_mr), &error_abort); 295 295 sysbus = SYS_BUS_DEVICE(dev); 296 296 sysbus_realize_and_unref(sysbus, &error_fatal); 297 297 sysbus_mmio_map(sysbus, 0, 0x80001000);

+2 -2

hw/mips/malta.c

··· 1184 1184 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1185 1185 { 1186 1186 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); 1187 1187 - object_property_set_str(OBJECT(&s->cps), ms->cpu_type, "cpu-type", 1187 1187 + object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, 1188 1188 &error_fatal); 1189 1189 - object_property_set_int(OBJECT(&s->cps), ms->smp.cpus, "num-vp", 1189 1189 + object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, 1190 1190 &error_fatal); 1191 1191 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 1192 1192

+1 -1

hw/misc/iotkit-sysctl.c

··· 84 84 85 85 if (cpuobj) { 86 86 if (object_property_find(cpuobj, "init-svtor", NULL)) { 87 87 - object_property_set_uint(cpuobj, vtor, "init-svtor", &error_abort); 87 87 + object_property_set_uint(cpuobj, "init-svtor", vtor, &error_abort); 88 88 } 89 89 } 90 90 }

+3 -3

hw/misc/macio/macio.c

··· 134 134 sysbus_connect_irq(sysbus_dev, 0, irq0); 135 135 sysbus_connect_irq(sysbus_dev, 1, irq1); 136 136 qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid); 137 137 - object_property_set_link(OBJECT(ide), OBJECT(&s->dbdma), "dbdma", 137 137 + object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma), 138 138 &error_abort); 139 139 macio_ide_register_dma(ide); 140 140 ··· 330 330 if (ns->has_pmu) { 331 331 /* GPIOs */ 332 332 sysbus_dev = SYS_BUS_DEVICE(&ns->gpio); 333 333 - object_property_set_link(OBJECT(&ns->gpio), OBJECT(pic_dev), "pic", 333 333 + object_property_set_link(OBJECT(&ns->gpio), "pic", OBJECT(pic_dev), 334 334 &error_abort); 335 335 memory_region_add_subregion(&s->bar, 0x50, 336 336 sysbus_mmio_get_region(sysbus_dev, 0)); ··· 340 340 341 341 /* PMU */ 342 342 object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU); 343 343 - object_property_set_link(OBJECT(&s->pmu), OBJECT(sysbus_dev), "gpio", 343 343 + object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sysbus_dev), 344 344 &error_abort); 345 345 qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb); 346 346 if (!qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), &err)) {

+1 -1

hw/net/ne2000-isa.c

··· 133 133 object_property_add(obj, "bootindex", "int32", 134 134 isa_ne2000_get_bootindex, 135 135 isa_ne2000_set_bootindex, NULL, NULL); 136 136 - object_property_set_int(obj, -1, "bootindex", NULL); 136 136 + object_property_set_int(obj, "bootindex", -1, NULL); 137 137 } 138 138 static const TypeInfo ne2000_isa_info = { 139 139 .name = TYPE_ISA_NE2000,

+2 -2

hw/net/xilinx_axienet.c

··· 989 989 (Object **) &cs->enet, 990 990 object_property_allow_set_link, 991 991 OBJ_PROP_LINK_STRONG); 992 992 - object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &error_abort); 993 993 - object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &error_abort); 992 992 + object_property_set_link(OBJECT(ds), "enet", OBJECT(s), &error_abort); 993 993 + object_property_set_link(OBJECT(cs), "enet", OBJECT(s), &error_abort); 994 994 995 995 qemu_macaddr_default_if_unset(&s->conf.macaddr); 996 996 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,

+10 -10

hw/pci-host/pnv_phb3.c

··· 999 999 } 1000 1000 1001 1001 /* LSI sources */ 1002 1002 - object_property_set_link(OBJECT(&phb->lsis), OBJECT(pnv), "xics", 1003 1003 - &error_abort); 1004 1004 - object_property_set_int(OBJECT(&phb->lsis), PNV_PHB3_NUM_LSI, "nr-irqs", 1002 1002 + object_property_set_link(OBJECT(&phb->lsis), "xics", OBJECT(pnv), 1003 1003 + &error_abort); 1004 1004 + object_property_set_int(OBJECT(&phb->lsis), "nr-irqs", PNV_PHB3_NUM_LSI, 1005 1005 &error_abort); 1006 1006 if (!qdev_realize(DEVICE(&phb->lsis), NULL, &local_err)) { 1007 1007 error_propagate(errp, local_err); ··· 1015 1015 phb->qirqs = qemu_allocate_irqs(ics_set_irq, &phb->lsis, phb->lsis.nr_irqs); 1016 1016 1017 1017 /* MSI sources */ 1018 1018 - object_property_set_link(OBJECT(&phb->msis), OBJECT(phb), "phb", 1019 1019 - &error_abort); 1020 1020 - object_property_set_link(OBJECT(&phb->msis), OBJECT(pnv), "xics", 1021 1021 - &error_abort); 1022 1022 - object_property_set_int(OBJECT(&phb->msis), PHB3_MAX_MSI, "nr-irqs", 1018 1018 + object_property_set_link(OBJECT(&phb->msis), "phb", OBJECT(phb), 1019 1019 + &error_abort); 1020 1020 + object_property_set_link(OBJECT(&phb->msis), "xics", OBJECT(pnv), 1021 1021 + &error_abort); 1022 1022 + object_property_set_int(OBJECT(&phb->msis), "nr-irqs", PHB3_MAX_MSI, 1023 1023 &error_abort); 1024 1024 if (!qdev_realize(DEVICE(&phb->msis), NULL, &local_err)) { 1025 1025 error_propagate(errp, local_err); ··· 1027 1027 } 1028 1028 1029 1029 /* Power Bus Common Queue */ 1030 1030 - object_property_set_link(OBJECT(&phb->pbcq), OBJECT(phb), "phb", 1031 1031 - &error_abort); 1030 1030 + object_property_set_link(OBJECT(&phb->pbcq), "phb", OBJECT(phb), 1031 1031 + &error_abort); 1032 1032 if (!qdev_realize(DEVICE(&phb->pbcq), NULL, &local_err)) { 1033 1033 error_propagate(errp, local_err); 1034 1034 return;

+2 -2

hw/pci-host/pnv_phb4.c

··· 1216 1216 } else { 1217 1217 nr_irqs = PNV_PHB4_MAX_INTs >> 1; 1218 1218 } 1219 1219 - object_property_set_int(OBJECT(xsrc), nr_irqs, "nr-irqs", &error_fatal); 1220 1220 - object_property_set_link(OBJECT(xsrc), OBJECT(phb), "xive", &error_fatal); 1219 1219 + object_property_set_int(OBJECT(xsrc), "nr-irqs", nr_irqs, &error_fatal); 1220 1220 + object_property_set_link(OBJECT(xsrc), "xive", OBJECT(phb), &error_fatal); 1221 1221 if (!qdev_realize(DEVICE(xsrc), NULL, &local_err)) { 1222 1222 error_propagate(errp, local_err); 1223 1223 return;

+2 -2

hw/pci-host/pnv_phb4_pec.c

··· 388 388 PnvPhb4PecStack *stack = &pec->stacks[i]; 389 389 Object *stk_obj = OBJECT(stack); 390 390 391 391 - object_property_set_int(stk_obj, i, "stack-no", &error_abort); 392 392 - object_property_set_link(stk_obj, OBJECT(pec), "pec", &error_abort); 391 391 + object_property_set_int(stk_obj, "stack-no", i, &error_abort); 392 392 + object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort); 393 393 if (!qdev_realize(DEVICE(stk_obj), NULL, &local_err)) { 394 394 error_propagate(errp, local_err); 395 395 return;

+2 -2

hw/pci-host/prep.c

··· 236 236 /* According to PReP specification section 6.1.6 "System Interrupt 237 237 * Assignments", all PCI interrupts are routed via IRQ 15 */ 238 238 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); 239 239 - object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines", 239 239 + object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS, 240 240 &error_fatal); 241 241 qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal); 242 242 sysbus_init_irq(dev, &s->or_irq->out_irq); ··· 307 307 308 308 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); 309 309 pci_dev = DEVICE(&s->pci_dev); 310 310 - object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr", 310 310 + object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0), 311 311 NULL); 312 312 qdev_prop_set_bit(pci_dev, "multifunction", false); 313 313 }

+5 -5

hw/ppc/mac_newworld.c

··· 304 304 /* 970 gets a U3 bus */ 305 305 /* Uninorth AGP bus */ 306 306 dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); 307 307 - object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 307 307 + object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev), 308 308 &error_abort); 309 309 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 310 310 uninorth_pci = U3_AGP_HOST_BRIDGE(dev); ··· 323 323 /* Use values found on a real PowerMac */ 324 324 /* Uninorth AGP bus */ 325 325 dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 326 326 - object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 326 326 + object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev), 327 327 &error_abort); 328 328 s = SYS_BUS_DEVICE(dev); 329 329 sysbus_realize_and_unref(s, &error_fatal); ··· 332 332 333 333 /* Uninorth internal bus */ 334 334 dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 335 335 - object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 335 335 + object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev), 336 336 &error_abort); 337 337 s = SYS_BUS_DEVICE(dev); 338 338 sysbus_realize_and_unref(s, &error_fatal); ··· 342 342 /* Uninorth main bus */ 343 343 dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 344 344 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000); 345 345 - object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 345 345 + object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev), 346 346 &error_abort); 347 347 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 348 348 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); ··· 380 380 qdev_prop_set_uint64(dev, "frequency", tbfreq); 381 381 qdev_prop_set_bit(dev, "has-pmu", has_pmu); 382 382 qdev_prop_set_bit(dev, "has-adb", has_adb); 383 383 - object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", 383 383 + object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev), 384 384 &error_abort); 385 385 pci_realize_and_unref(macio, pci_bus, &error_fatal); 386 386

+2 -2

hw/ppc/mac_oldworld.c

··· 254 254 /* Grackle PCI host bridge */ 255 255 dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 256 256 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 257 257 - object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 257 257 + object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev), 258 258 &error_abort); 259 259 s = SYS_BUS_DEVICE(dev); 260 260 sysbus_realize_and_unref(s, &error_fatal); ··· 281 281 macio = pci_new(-1, TYPE_OLDWORLD_MACIO); 282 282 dev = DEVICE(macio); 283 283 qdev_prop_set_uint64(dev, "frequency", tbfreq); 284 284 - object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", 284 284 + object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev), 285 285 &error_abort); 286 286 pci_realize_and_unref(macio, pci_bus, &error_fatal); 287 287

+59 -59

hw/ppc/pnv.c

··· 699 699 { 700 700 ISADevice *dev = isa_new("isa-ipmi-bt"); 701 701 702 702 - object_property_set_link(OBJECT(dev), OBJECT(bmc), "bmc", &error_fatal); 703 703 - object_property_set_int(OBJECT(dev), irq, "irq", &error_fatal); 702 702 + object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 703 703 + object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 704 704 isa_realize_and_unref(dev, bus, &error_fatal); 705 705 } 706 706 ··· 828 828 * way to specify different ranges for each chip 829 829 */ 830 830 if (i == 0) { 831 831 - object_property_set_int(chip, machine->ram_size, "ram-size", 831 831 + object_property_set_int(chip, "ram-size", machine->ram_size, 832 832 &error_fatal); 833 833 } 834 834 835 835 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 836 836 object_property_add_child(OBJECT(pnv), chip_name, chip); 837 837 - object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 837 837 + object_property_set_int(chip, "chip-id", PNV_CHIP_HWID(i), 838 838 &error_fatal); 839 839 - object_property_set_int(chip, machine->smp.cores, 840 840 - "nr-cores", &error_fatal); 841 841 - object_property_set_int(chip, machine->smp.threads, 842 842 - "nr-threads", &error_fatal); 839 839 + object_property_set_int(chip, "nr-cores", machine->smp.cores, 840 840 + &error_fatal); 841 841 + object_property_set_int(chip, "nr-threads", machine->smp.threads, 842 842 + &error_fatal); 843 843 /* 844 844 * The POWER8 machine use the XICS interrupt interface. 845 845 * Propagate the XICS fabric to the chip and its controllers. 846 846 */ 847 847 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 848 848 - object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 848 848 + object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 849 849 } 850 850 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 851 851 - object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 851 851 + object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 852 852 &error_abort); 853 853 } 854 854 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); ··· 1136 1136 } 1137 1137 1138 1138 /* Processor Service Interface (PSI) Host Bridge */ 1139 1139 - object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1140 1140 - "bar", &error_fatal); 1141 1141 - object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1142 1142 - ICS_PROP_XICS, &error_abort); 1139 1139 + object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1140 1140 + &error_fatal); 1141 1141 + object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1142 1142 + OBJECT(chip8->xics), &error_abort); 1143 1143 if (!qdev_realize(DEVICE(&chip8->psi), NULL, &local_err)) { 1144 1144 error_propagate(errp, local_err); 1145 1145 return; ··· 1148 1148 &PNV_PSI(psi8)->xscom_regs); 1149 1149 1150 1150 /* Create LPC controller */ 1151 1151 - object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1151 1151 + object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1152 1152 &error_abort); 1153 1153 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1154 1154 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); ··· 1168 1168 } 1169 1169 1170 1170 /* Create the simplified OCC model */ 1171 1171 - object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1171 1171 + object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1172 1172 &error_abort); 1173 1173 if (!qdev_realize(DEVICE(&chip8->occ), NULL, &local_err)) { 1174 1174 error_propagate(errp, local_err); ··· 1181 1181 &chip8->occ.sram_regs); 1182 1182 1183 1183 /* HOMER */ 1184 1184 - object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1184 1184 + object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1185 1185 &error_abort); 1186 1186 if (!qdev_realize(DEVICE(&chip8->homer), NULL, &local_err)) { 1187 1187 error_propagate(errp, local_err); ··· 1199 1199 PnvPHB3 *phb = &chip8->phbs[i]; 1200 1200 PnvPBCQState *pbcq = &phb->pbcq; 1201 1201 1202 1202 - object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1203 1203 - object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1202 1202 + object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1203 1203 + object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1204 1204 &error_fatal); 1205 1205 if (!sysbus_realize(SYS_BUS_DEVICE(phb), &local_err)) { 1206 1206 error_propagate(errp, local_err); ··· 1347 1347 sizeof(*eq), TYPE_PNV_QUAD, 1348 1348 &error_fatal, NULL); 1349 1349 1350 1350 - object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1350 1350 + object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal); 1351 1351 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1352 1352 1353 1353 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), ··· 1368 1368 uint32_t pec_nest_base; 1369 1369 uint32_t pec_pci_base; 1370 1370 1371 1371 - object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1371 1371 + object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1372 1372 /* 1373 1373 * PEC0 -> 1 stack 1374 1374 * PEC1 -> 2 stacks 1375 1375 * PEC2 -> 3 stacks 1376 1376 */ 1377 1377 - object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1377 1377 + object_property_set_int(OBJECT(pec), "num-stacks", i + 1, 1378 1378 + &error_fatal); 1379 1379 + object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1378 1380 &error_fatal); 1379 1379 - object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1380 1380 - &error_fatal); 1381 1381 - object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1382 1382 - "system-memory", &error_abort); 1381 1381 + object_property_set_link(OBJECT(pec), "system-memory", 1382 1382 + OBJECT(get_system_memory()), &error_abort); 1383 1383 if (!qdev_realize(DEVICE(pec), NULL, &local_err)) { 1384 1384 error_propagate(errp, local_err); 1385 1385 return; ··· 1396 1396 PnvPhb4PecStack *stack = &pec->stacks[j]; 1397 1397 Object *obj = OBJECT(&stack->phb); 1398 1398 1399 1399 - object_property_set_int(obj, phb_id, "index", &error_fatal); 1400 1400 - object_property_set_int(obj, chip->chip_id, "chip-id", 1399 1399 + object_property_set_int(obj, "index", phb_id, &error_fatal); 1400 1400 + object_property_set_int(obj, "chip-id", chip->chip_id, 1401 1401 &error_fatal); 1402 1402 - object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1402 1402 + object_property_set_int(obj, "version", PNV_PHB4_VERSION, 1403 1403 &error_fatal); 1404 1404 - object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1404 1404 + object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, 1405 1405 &error_fatal); 1406 1406 - object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1406 1406 + object_property_set_link(obj, "stack", OBJECT(stack), 1407 1407 + &error_abort); 1407 1408 if (!sysbus_realize(SYS_BUS_DEVICE(obj), &local_err)) { 1408 1409 error_propagate(errp, local_err); 1409 1410 return; ··· 1453 1454 } 1454 1455 1455 1456 /* XIVE interrupt controller (POWER9) */ 1456 1456 - object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1457 1457 - "ic-bar", &error_fatal); 1458 1458 - object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1459 1459 - "vc-bar", &error_fatal); 1460 1460 - object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1461 1461 - "pc-bar", &error_fatal); 1462 1462 - object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1463 1463 - "tm-bar", &error_fatal); 1464 1464 - object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1457 1457 + object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1458 1458 + PNV9_XIVE_IC_BASE(chip), &error_fatal); 1459 1459 + object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1460 1460 + PNV9_XIVE_VC_BASE(chip), &error_fatal); 1461 1461 + object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1462 1462 + PNV9_XIVE_PC_BASE(chip), &error_fatal); 1463 1463 + object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1464 1464 + PNV9_XIVE_TM_BASE(chip), &error_fatal); 1465 1465 + object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1465 1466 &error_abort); 1466 1467 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), &local_err)) { 1467 1468 error_propagate(errp, local_err); ··· 1471 1472 &chip9->xive.xscom_regs); 1472 1473 1473 1474 /* Processor Service Interface (PSI) Host Bridge */ 1474 1474 - object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1475 1475 - "bar", &error_fatal); 1475 1475 + object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1476 1476 + &error_fatal); 1476 1477 if (!qdev_realize(DEVICE(&chip9->psi), NULL, &local_err)) { 1477 1478 error_propagate(errp, local_err); 1478 1479 return; ··· 1481 1482 &PNV_PSI(psi9)->xscom_regs); 1482 1483 1483 1484 /* LPC */ 1484 1484 - object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1485 1485 + object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1485 1486 &error_abort); 1486 1487 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, &local_err)) { 1487 1488 error_propagate(errp, local_err); ··· 1494 1495 (uint64_t) PNV9_LPCM_BASE(chip)); 1495 1496 1496 1497 /* Create the simplified OCC model */ 1497 1497 - object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1498 1498 + object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1498 1499 &error_abort); 1499 1500 if (!qdev_realize(DEVICE(&chip9->occ), NULL, &local_err)) { 1500 1501 error_propagate(errp, local_err); ··· 1507 1508 &chip9->occ.sram_regs); 1508 1509 1509 1510 /* HOMER */ 1510 1510 - object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1511 1511 + object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1511 1512 &error_abort); 1512 1513 if (!qdev_realize(DEVICE(&chip9->homer), NULL, &local_err)) { 1513 1514 error_propagate(errp, local_err); ··· 1588 1589 } 1589 1590 1590 1591 /* Processor Service Interface (PSI) Host Bridge */ 1591 1591 - object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1592 1592 - "bar", &error_fatal); 1592 1592 + object_property_set_int(OBJECT(&chip10->psi), "bar", 1593 1593 + PNV10_PSIHB_BASE(chip), &error_fatal); 1593 1594 if (!qdev_realize(DEVICE(&chip10->psi), NULL, &local_err)) { 1594 1595 error_propagate(errp, local_err); 1595 1596 return; ··· 1598 1599 &PNV_PSI(&chip10->psi)->xscom_regs); 1599 1600 1600 1601 /* LPC */ 1601 1601 - object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1602 1602 - &error_abort); 1602 1602 + object_property_set_link(OBJECT(&chip10->lpc), "psi", 1603 1603 + OBJECT(&chip10->psi), &error_abort); 1603 1604 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, &local_err)) { 1604 1605 error_propagate(errp, local_err); 1605 1606 return; ··· 1707 1708 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1708 1709 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1709 1710 chip->cores[i] = pnv_core; 1710 1710 - object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1711 1711 - "nr-threads", &error_fatal); 1712 1712 - object_property_set_int(OBJECT(pnv_core), core_hwid, 1713 1713 - CPU_CORE_PROP_CORE_ID, &error_fatal); 1714 1714 - object_property_set_int(OBJECT(pnv_core), 1715 1715 - pcc->core_pir(chip, core_hwid), 1716 1716 - "pir", &error_fatal); 1717 1717 - object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1718 1718 - "hrmor", &error_fatal); 1719 1719 - object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1711 1711 + object_property_set_int(OBJECT(pnv_core), "nr-threads", 1712 1712 + chip->nr_threads, &error_fatal); 1713 1713 + object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1714 1714 + core_hwid, &error_fatal); 1715 1715 + object_property_set_int(OBJECT(pnv_core), "pir", 1716 1716 + pcc->core_pir(chip, core_hwid), &error_fatal); 1717 1717 + object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1718 1718 + &error_fatal); 1719 1719 + object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1720 1720 &error_abort); 1721 1721 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1722 1722

+4 -5

hw/ppc/pnv_psi.c

··· 505 505 unsigned int i; 506 506 507 507 /* Create PSI interrupt control source */ 508 508 - object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err); 508 508 + object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS, &err); 509 509 if (err) { 510 510 error_propagate(errp, err); 511 511 return; ··· 845 845 int i; 846 846 847 847 /* This is the only device with 4k ESB pages */ 848 848 - object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift", 848 848 + object_property_set_int(OBJECT(xsrc), "shift", XIVE_ESB_4K, &error_fatal); 849 849 + object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS, 849 850 &error_fatal); 850 850 - object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs", 851 851 - &error_fatal); 852 852 - object_property_set_link(OBJECT(xsrc), OBJECT(psi), "xive", &error_abort); 851 851 + object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort); 853 852 if (!qdev_realize(DEVICE(xsrc), NULL, &local_err)) { 854 853 error_propagate(errp, local_err); 855 854 return;

+2 -2

hw/ppc/spapr.c

··· 2624 2624 nr_threads = smp_cpus - i * smp_threads; 2625 2625 } 2626 2626 2627 2627 - object_property_set_int(core, nr_threads, "nr-threads", 2627 2627 + object_property_set_int(core, "nr-threads", nr_threads, 2628 2628 &error_fatal); 2629 2629 - object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2629 2629 + object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2630 2630 &error_fatal); 2631 2631 qdev_realize(DEVICE(core), NULL, &error_fatal); 2632 2632

+3 -3

hw/ppc/spapr_irq.c

··· 308 308 obj = object_new(TYPE_ICS_SPAPR); 309 309 310 310 object_property_add_child(OBJECT(spapr), "ics", obj); 311 311 - object_property_set_link(obj, OBJECT(spapr), ICS_PROP_XICS, 311 311 + object_property_set_link(obj, ICS_PROP_XICS, OBJECT(spapr), 312 312 &error_abort); 313 313 - object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &error_abort); 313 313 + object_property_set_int(obj, "nr-irqs", smc->nr_xirqs, &error_abort); 314 314 if (!qdev_realize(DEVICE(obj), NULL, &local_err)) { 315 315 error_propagate(errp, local_err); 316 316 return; ··· 331 331 * priority 332 332 */ 333 333 qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); 334 334 - object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric", 334 334 + object_property_set_link(OBJECT(dev), "xive-fabric", OBJECT(spapr), 335 335 &error_abort); 336 336 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 337 337

+1 -1

hw/ppc/spapr_pci.c

··· 2418 2418 2419 2419 if (object_dynamic_cast(OBJECT(dev), "VGA") 2420 2420 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 2421 2421 - object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 2421 2421 + object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be, 2422 2422 &error_abort); 2423 2423 } 2424 2424 return 0;

+2 -2

hw/riscv/opentitan.c

··· 108 108 MemoryRegion *sys_mem = get_system_memory(); 109 109 Error *err = NULL; 110 110 111 111 - object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", 111 111 + object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 112 112 &error_abort); 113 113 - object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", 113 113 + object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 114 114 &error_abort); 115 115 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 116 116

+2 -2

hw/riscv/sifive_e.c

··· 175 175 SiFiveESoCState *s = RISCV_E_SOC(obj); 176 176 177 177 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 178 178 - object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", 178 178 + object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 179 179 &error_abort); 180 180 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, 181 181 TYPE_SIFIVE_GPIO); ··· 190 190 SiFiveESoCState *s = RISCV_E_SOC(dev); 191 191 MemoryRegion *sys_mem = get_system_memory(); 192 192 193 193 - object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", 193 193 + object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 194 194 &error_abort); 195 195 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 196 196

+3 -3

hw/riscv/sifive_u.c

··· 383 383 384 384 /* Initialize SoC */ 385 385 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 386 386 - object_property_set_uint(OBJECT(&s->soc), s->serial, "serial", 387 387 - &error_abort); 386 386 + object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 387 387 + &error_abort); 388 388 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 389 389 390 390 /* register RAM */ ··· 708 708 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 709 709 qdev_set_nic_properties(DEVICE(&s->gem), nd); 710 710 } 711 711 - object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 711 711 + object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 712 712 &error_abort); 713 713 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), &err)) { 714 714 error_propagate(errp, err);

+2 -2

hw/riscv/spike.c

··· 171 171 /* Initialize SOC */ 172 172 object_initialize_child(OBJECT(machine), "soc", &s->soc, 173 173 TYPE_RISCV_HART_ARRAY); 174 174 - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", 174 174 + object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 175 175 &error_abort); 176 176 - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 176 176 + object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus, 177 177 &error_abort); 178 178 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort); 179 179

+2 -2

hw/riscv/virt.c

··· 487 487 /* Initialize SOC */ 488 488 object_initialize_child(OBJECT(machine), "soc", &s->soc, 489 489 TYPE_RISCV_HART_ARRAY); 490 490 - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", 490 490 + object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 491 491 &error_abort); 492 492 - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 492 492 + object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus, 493 493 &error_abort); 494 494 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort); 495 495

+6 -6

hw/rx/rx-gdbsim.c

··· 101 101 102 102 /* Initialize MCU */ 103 103 object_initialize_child(OBJECT(machine), "mcu", &s->mcu, rxc->mcu_name); 104 104 - object_property_set_link(OBJECT(&s->mcu), OBJECT(sysmem), 105 105 - "main-bus", &error_abort); 106 106 - object_property_set_uint(OBJECT(&s->mcu), rxc->xtal_freq_hz, 107 107 - "xtal-frequency-hz", &error_abort); 108 108 - object_property_set_bool(OBJECT(&s->mcu), kernel_filename != NULL, 109 109 - "load-kernel", &error_abort); 104 104 + object_property_set_link(OBJECT(&s->mcu), "main-bus", OBJECT(sysmem), 105 105 + &error_abort); 106 106 + object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz", 107 107 + rxc->xtal_freq_hz, &error_abort); 108 108 + object_property_set_bool(OBJECT(&s->mcu), "load-kernel", 109 109 + kernel_filename != NULL, &error_abort); 110 110 qdev_realize(DEVICE(&s->mcu), NULL, &error_abort); 111 111 112 112 /* Load kernel and dtb */

+2 -2

hw/s390x/ipl.c

··· 555 555 ascii_loadparm[i] = ebcdic2ascii[(uint8_t) ebcdic_loadparm[i]]; 556 556 } 557 557 ascii_loadparm[i] = 0; 558 558 - object_property_set_str(machine, ascii_loadparm, "loadparm", &err); 558 558 + object_property_set_str(machine, "loadparm", ascii_loadparm, &err); 559 559 } else { 560 560 - object_property_set_str(machine, "", "loadparm", &err); 560 560 + object_property_set_str(machine, "loadparm", "", &err); 561 561 } 562 562 if (err) { 563 563 warn_report_err(err);

+1 -1

hw/s390x/s390-pci-bus.c

··· 824 824 return NULL; 825 825 } 826 826 827 827 - object_property_set_str(OBJECT(dev), target, "target", &local_err); 827 827 + object_property_set_str(OBJECT(dev), "target", target, &local_err); 828 828 if (local_err) { 829 829 object_unparent(OBJECT(dev)); 830 830 error_propagate_prepend(errp, local_err,

+1 -1

hw/s390x/s390-skeys.c

··· 401 401 object_property_add_bool(obj, "migration-enabled", 402 402 s390_skeys_get_migration_enabled, 403 403 s390_skeys_set_migration_enabled); 404 404 - object_property_set_bool(obj, true, "migration-enabled", NULL); 404 404 + object_property_set_bool(obj, "migration-enabled", true, NULL); 405 405 } 406 406 407 407 static void s390_skeys_class_init(ObjectClass *oc, void *data)

+1 -1

hw/s390x/s390-stattrib.c

··· 388 388 object_property_add_bool(obj, "migration-enabled", 389 389 s390_stattrib_get_migration_enabled, 390 390 s390_stattrib_set_migration_enabled); 391 391 - object_property_set_bool(obj, true, "migration-enabled", NULL); 391 391 + object_property_set_bool(obj, "migration-enabled", true, NULL); 392 392 sas->migration_cur_gfn = 0; 393 393 } 394 394

+3 -3

hw/s390x/s390-virtio-ccw.c

··· 70 70 S390CPU *cpu = S390_CPU(object_new(typename)); 71 71 Error *err = NULL; 72 72 73 73 - object_property_set_int(OBJECT(cpu), core_id, "core-id", &err); 73 73 + object_property_set_int(OBJECT(cpu), "core-id", core_id, &err); 74 74 if (err != NULL) { 75 75 goto out; 76 76 } ··· 736 736 machine_set_aes_key_wrap); 737 737 object_property_set_description(obj, "aes-key-wrap", 738 738 "enable/disable AES key wrapping using the CPACF wrapping key"); 739 739 - object_property_set_bool(obj, true, "aes-key-wrap", NULL); 739 739 + object_property_set_bool(obj, "aes-key-wrap", true, NULL); 740 740 741 741 object_property_add_bool(obj, "dea-key-wrap", 742 742 machine_get_dea_key_wrap, 743 743 machine_set_dea_key_wrap); 744 744 object_property_set_description(obj, "dea-key-wrap", 745 745 "enable/disable DEA key wrapping using the CPACF wrapping key"); 746 746 - object_property_set_bool(obj, true, "dea-key-wrap", NULL); 746 746 + object_property_set_bool(obj, "dea-key-wrap", true, NULL); 747 747 object_property_add_str(obj, "loadparm", 748 748 machine_get_loadparm, machine_set_loadparm); 749 749 object_property_set_description(obj, "loadparm",

+2 -3

hw/s390x/virtio-ccw-crypto.c

··· 26 26 return; 27 27 } 28 28 29 29 - object_property_set_link(OBJECT(vdev), 30 30 - OBJECT(dev->vdev.conf.cryptodev), "cryptodev", 31 31 - NULL); 29 29 + object_property_set_link(OBJECT(vdev), "cryptodev", 30 30 + OBJECT(dev->vdev.conf.cryptodev), NULL); 32 31 } 33 32 34 33 static void virtio_ccw_crypto_instance_init(Object *obj)

+1 -2

hw/s390x/virtio-ccw-rng.c

··· 27 27 return; 28 28 } 29 29 30 30 - object_property_set_link(OBJECT(dev), 31 31 - OBJECT(dev->vdev.conf.rng), "rng", 30 30 + object_property_set_link(OBJECT(dev), "rng", OBJECT(dev->vdev.conf.rng), 32 31 NULL); 33 32 } 34 33

+2 -2

hw/scsi/scsi-bus.c

··· 268 268 269 269 qdev_prop_set_uint32(dev, "scsi-id", unit); 270 270 if (bootindex >= 0) { 271 271 - object_property_set_int(OBJECT(dev), bootindex, "bootindex", 271 271 + object_property_set_int(OBJECT(dev), "bootindex", bootindex, 272 272 &error_abort); 273 273 } 274 274 if (object_property_find(OBJECT(dev), "removable", NULL)) { ··· 283 283 object_unparent(OBJECT(dev)); 284 284 return NULL; 285 285 } 286 286 - object_property_set_bool(OBJECT(dev), share_rw, "share-rw", &err); 286 286 + object_property_set_bool(OBJECT(dev), "share-rw", share_rw, &err); 287 287 if (err != NULL) { 288 288 error_propagate(errp, err); 289 289 object_unparent(OBJECT(dev));

+3 -3

hw/sd/aspeed_sdhci.c

··· 132 132 Object *sdhci_slot = OBJECT(&sdhci->slots[i]); 133 133 SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]); 134 134 135 135 - object_property_set_int(sdhci_slot, 2, "sd-spec-version", &err); 135 135 + object_property_set_int(sdhci_slot, "sd-spec-version", 2, &err); 136 136 if (err) { 137 137 error_propagate(errp, err); 138 138 return; 139 139 } 140 140 141 141 - object_property_set_uint(sdhci_slot, ASPEED_SDHCI_CAPABILITIES, 142 142 - "capareg", &err); 141 141 + object_property_set_uint(sdhci_slot, "capareg", 142 142 + ASPEED_SDHCI_CAPABILITIES, &err); 143 143 if (err) { 144 144 error_propagate(errp, err); 145 145 return;

+1 -1

hw/sd/ssi-sd.c

··· 261 261 } 262 262 } 263 263 264 264 - object_property_set_bool(OBJECT(carddev), true, "spi", &err); 264 264 + object_property_set_bool(OBJECT(carddev), "spi", true, &err); 265 265 if (err) { 266 266 goto fail; 267 267 }

+1 -1

hw/sparc/sun4m.c

··· 878 878 879 879 /* Create and map RAM frontend */ 880 880 dev = qdev_new("memory"); 881 881 - object_property_set_link(OBJECT(dev), ram_memdev, "memdev", &error_fatal); 881 881 + object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal); 882 882 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 883 883 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 884 884

+1 -1

hw/sparc64/sun4u.c

··· 579 579 sabre = SABRE_DEVICE(qdev_new(TYPE_SABRE)); 580 580 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); 581 581 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); 582 582 - object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", 582 582 + object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu), 583 583 &error_abort); 584 584 sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal); 585 585

+2 -2

hw/usb/dev-storage.c

··· 748 748 s->conf.bootindex = boot_index; 749 749 750 750 if (s->scsi_dev) { 751 751 - object_property_set_int(OBJECT(s->scsi_dev), boot_index, "bootindex", 751 751 + object_property_set_int(OBJECT(s->scsi_dev), "bootindex", boot_index, 752 752 &error_abort); 753 753 } 754 754 ··· 769 769 object_property_add(obj, "bootindex", "int32", 770 770 usb_msd_get_bootindex, 771 771 usb_msd_set_bootindex, NULL, NULL); 772 772 - object_property_set_int(obj, -1, "bootindex", NULL); 772 772 + object_property_set_int(obj, "bootindex", -1, NULL); 773 773 } 774 774 775 775 static void usb_msd_class_bot_initfn(ObjectClass *klass, void *data)

+2 -3

hw/virtio/virtio-crypto-pci.c

··· 57 57 if (!qdev_realize(vdev, BUS(&vpci_dev->bus), errp)) { 58 58 return; 59 59 } 60 60 - object_property_set_link(OBJECT(vcrypto), 61 61 - OBJECT(vcrypto->vdev.conf.cryptodev), "cryptodev", 62 62 - NULL); 60 60 + object_property_set_link(OBJECT(vcrypto), "cryptodev", 61 61 + OBJECT(vcrypto->vdev.conf.cryptodev), NULL); 63 62 } 64 63 65 64 static void virtio_crypto_pci_class_init(ObjectClass *klass, void *data)

+2 -2

hw/virtio/virtio-iommu-pci.c

··· 65 65 error_append_hint(errp, "Valid values are 0 and 1\n"); 66 66 } 67 67 } 68 68 - object_property_set_link(OBJECT(dev), 68 68 + object_property_set_link(OBJECT(dev), "primary-bus", 69 69 OBJECT(pci_get_bus(&vpci_dev->pci_dev)), 70 70 - "primary-bus", &error_abort); 70 70 + &error_abort); 71 71 qdev_realize(vdev, BUS(&vpci_dev->bus), errp); 72 72 } 73 73

+2 -2

hw/virtio/virtio-mem-pci.c

··· 22 22 DeviceState *vdev = DEVICE(&mem_pci->vdev); 23 23 24 24 qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus)); 25 25 - object_property_set_bool(OBJECT(vdev), true, "realized", errp); 25 25 + object_property_set_bool(OBJECT(vdev), "realized", true, errp); 26 26 } 27 27 28 28 static void virtio_mem_pci_set_addr(MemoryDeviceState *md, uint64_t addr, 29 29 Error **errp) 30 30 { 31 31 - object_property_set_uint(OBJECT(md), addr, VIRTIO_MEM_ADDR_PROP, errp); 31 31 + object_property_set_uint(OBJECT(md), VIRTIO_MEM_ADDR_PROP, addr, errp); 32 32 } 33 33 34 34 static uint64_t virtio_mem_pci_get_addr(const MemoryDeviceState *md)

+1 -1

hw/virtio/virtio-pmem-pci.c

··· 28 28 static void virtio_pmem_pci_set_addr(MemoryDeviceState *md, uint64_t addr, 29 29 Error **errp) 30 30 { 31 31 - object_property_set_uint(OBJECT(md), addr, VIRTIO_PMEM_ADDR_PROP, errp); 31 31 + object_property_set_uint(OBJECT(md), VIRTIO_PMEM_ADDR_PROP, addr, errp); 32 32 } 33 33 34 34 static uint64_t virtio_pmem_pci_get_addr(const MemoryDeviceState *md)

+1 -2

hw/virtio/virtio-rng-pci.c

··· 41 41 return; 42 42 } 43 43 44 44 - object_property_set_link(OBJECT(vrng), 45 45 - OBJECT(vrng->vdev.conf.rng), "rng", 44 44 + object_property_set_link(OBJECT(vrng), "rng", OBJECT(vrng->vdev.conf.rng), 46 45 NULL); 47 46 } 48 47

+2 -2

hw/virtio/virtio-rng.c

··· 208 208 /* The child property took a reference, we can safely drop ours now */ 209 209 object_unref(default_backend); 210 210 211 211 - object_property_set_link(OBJECT(dev), default_backend, 212 212 - "rng", &error_abort); 211 211 + object_property_set_link(OBJECT(dev), "rng", default_backend, 212 212 + &error_abort); 213 213 } 214 214 215 215 vrng->rng = vrng->conf.rng;

+1 -1

include/hw/audio/pcspk.h

··· 33 33 34 34 static inline void pcspk_init(ISADevice *isadev, ISABus *bus, ISADevice *pit) 35 35 { 36 36 - object_property_set_link(OBJECT(isadev), OBJECT(pit), "pit", NULL); 36 36 + object_property_set_link(OBJECT(isadev), "pit", OBJECT(pit), NULL); 37 37 isa_realize_and_unref(isadev, bus, &error_fatal); 38 38 } 39 39

+22 -22

include/qom/object.h

··· 1203 1203 /** 1204 1204 * object_property_get: 1205 1205 * @obj: the object 1206 1206 + * @name: the name of the property 1206 1207 * @v: the visitor that will receive the property value. This should be an 1207 1208 * Output visitor and the data will be written with @name as the name. 1208 1208 - * @name: the name of the property 1209 1209 * @errp: returns an error if this function fails 1210 1210 * 1211 1211 * Reads a property from a object. 1212 1212 */ 1213 1213 - void object_property_get(Object *obj, Visitor *v, const char *name, 1213 1213 + void object_property_get(Object *obj, const char *name, Visitor *v, 1214 1214 Error **errp); 1215 1215 1216 1216 /** 1217 1217 * object_property_set_str: 1218 1218 - * @value: the value to be written to the property 1219 1218 * @name: the name of the property 1219 1219 + * @value: the value to be written to the property 1220 1220 * @errp: returns an error if this function fails 1221 1221 * 1222 1222 * Writes a string value to a property. 1223 1223 */ 1224 1224 - void object_property_set_str(Object *obj, const char *value, 1225 1225 - const char *name, Error **errp); 1224 1224 + void object_property_set_str(Object *obj, const char *name, 1225 1225 + const char *value, Error **errp); 1226 1226 1227 1227 /** 1228 1228 * object_property_get_str: ··· 1239 1239 1240 1240 /** 1241 1241 * object_property_set_link: 1242 1242 - * @value: the value to be written to the property 1243 1242 * @name: the name of the property 1243 1243 + * @value: the value to be written to the property 1244 1244 * @errp: returns an error if this function fails 1245 1245 * 1246 1246 * Writes an object's canonical path to a property. ··· 1250 1250 * unreferenced, and a reference is added to the new target object. 1251 1251 * 1252 1252 */ 1253 1253 - void object_property_set_link(Object *obj, Object *value, 1254 1254 - const char *name, Error **errp); 1253 1253 + void object_property_set_link(Object *obj, const char *name, 1254 1254 + Object *value, Error **errp); 1255 1255 1256 1256 /** 1257 1257 * object_property_get_link: ··· 1268 1268 1269 1269 /** 1270 1270 * object_property_set_bool: 1271 1271 + * @name: the name of the property 1271 1272 * @value: the value to be written to the property 1272 1272 - * @name: the name of the property 1273 1273 * @errp: returns an error if this function fails 1274 1274 * 1275 1275 * Writes a bool value to a property. 1276 1276 */ 1277 1277 - void object_property_set_bool(Object *obj, bool value, 1278 1278 - const char *name, Error **errp); 1277 1277 + void object_property_set_bool(Object *obj, const char *name, 1278 1278 + bool value, Error **errp); 1279 1279 1280 1280 /** 1281 1281 * object_property_get_bool: ··· 1291 1291 1292 1292 /** 1293 1293 * object_property_set_int: 1294 1294 - * @value: the value to be written to the property 1295 1294 * @name: the name of the property 1295 1295 + * @value: the value to be written to the property 1296 1296 * @errp: returns an error if this function fails 1297 1297 * 1298 1298 * Writes an integer value to a property. 1299 1299 */ 1300 1300 - void object_property_set_int(Object *obj, int64_t value, 1301 1301 - const char *name, Error **errp); 1300 1300 + void object_property_set_int(Object *obj, const char *name, 1301 1301 + int64_t value, Error **errp); 1302 1302 1303 1303 /** 1304 1304 * object_property_get_int: ··· 1314 1314 1315 1315 /** 1316 1316 * object_property_set_uint: 1317 1317 - * @value: the value to be written to the property 1318 1317 * @name: the name of the property 1318 1318 + * @value: the value to be written to the property 1319 1319 * @errp: returns an error if this function fails 1320 1320 * 1321 1321 * Writes an unsigned integer value to a property. 1322 1322 */ 1323 1323 - void object_property_set_uint(Object *obj, uint64_t value, 1324 1324 - const char *name, Error **errp); 1323 1323 + void object_property_set_uint(Object *obj, const char *name, 1324 1324 + uint64_t value, Error **errp); 1325 1325 1326 1326 /** 1327 1327 * object_property_get_uint: ··· 1352 1352 /** 1353 1353 * object_property_set: 1354 1354 * @obj: the object 1355 1355 + * @name: the name of the property 1355 1356 * @v: the visitor that will be used to write the property value. This should 1356 1357 * be an Input visitor and the data will be first read with @name as the 1357 1358 * name and then written as the property value. 1358 1358 - * @name: the name of the property 1359 1359 * @errp: returns an error if this function fails 1360 1360 * 1361 1361 * Writes a property to a object. 1362 1362 */ 1363 1363 - void object_property_set(Object *obj, Visitor *v, const char *name, 1363 1363 + void object_property_set(Object *obj, const char *name, Visitor *v, 1364 1364 Error **errp); 1365 1365 1366 1366 /** 1367 1367 * object_property_parse: 1368 1368 * @obj: the object 1369 1369 - * @string: the string that will be used to parse the property value. 1370 1369 * @name: the name of the property 1370 1370 + * @string: the string that will be used to parse the property value. 1371 1371 * @errp: returns an error if this function fails 1372 1372 * 1373 1373 * Parses a string and writes the result into a property of an object. 1374 1374 */ 1375 1375 - void object_property_parse(Object *obj, const char *string, 1376 1376 - const char *name, Error **errp); 1375 1375 + void object_property_parse(Object *obj, const char *name, 1376 1376 + const char *string, Error **errp); 1377 1377 1378 1378 /** 1379 1379 * object_property_print:

+4 -3

include/qom/qom-qobject.h

··· 28 28 /** 29 29 * object_property_set_qobject: 30 30 * @obj: the object 31 31 - * @ret: The value that will be written to the property. 32 31 * @name: the name of the property 32 32 + * @value: The value that will be written to the property. 33 33 * @errp: returns an error if this function fails 34 34 * 35 35 * Writes a property to a object. 36 36 */ 37 37 - void object_property_set_qobject(Object *obj, struct QObject *qobj, 38 38 - const char *name, struct Error **errp); 37 37 + void object_property_set_qobject(Object *obj, 38 38 + const char *name, struct QObject *value, 39 39 + struct Error **errp); 39 40 40 41 #endif

+1 -1

linux-user/syscall.c

··· 7722 7722 if (CPU_NEXT(first_cpu)) { 7723 7723 TaskState *ts = cpu->opaque; 7724 7724 7725 7725 - object_property_set_bool(OBJECT(cpu), false, "realized", NULL); 7725 7725 + object_property_set_bool(OBJECT(cpu), "realized", false, NULL); 7726 7726 object_unref(OBJECT(cpu)); 7727 7727 /* 7728 7728 * At this point the CPU should be unrealized and removed

+1 -1

net/filter.c

··· 338 338 case COLO_EVENT_CHECKPOINT: 339 339 break; 340 340 case COLO_EVENT_FAILOVER: 341 341 - object_property_set_str(OBJECT(nf), "off", "status", errp); 341 341 + object_property_set_str(OBJECT(nf), "status", "off", errp); 342 342 break; 343 343 default: 344 344 break;

+1 -1

net/net.c

··· 1164 1164 continue; 1165 1165 } 1166 1166 v = string_output_visitor_new(false, &str); 1167 1167 - object_property_get(OBJECT(nf), v, prop->name, NULL); 1167 1167 + object_property_get(OBJECT(nf), prop->name, v, NULL); 1168 1168 visit_complete(v, &str); 1169 1169 visit_free(v); 1170 1170 monitor_printf(mon, ",%s=%s", prop->name, str);

+1 -1

qdev-monitor.c

··· 186 186 if (strcmp(name, "bus") == 0) 187 187 return 0; 188 188 189 189 - object_property_parse(obj, value, name, &err); 189 189 + object_property_parse(obj, name, value, &err); 190 190 if (err != NULL) { 191 191 error_propagate(errp, err); 192 192 return -1;

+26 -26

qom/object.c

··· 404 404 continue; 405 405 } 406 406 p->used = true; 407 407 - object_property_parse(obj, p->value, p->property, &err); 407 407 + object_property_parse(obj, p->property, p->value, &err); 408 408 if (err != NULL) { 409 409 error_prepend(&err, "can't apply global %s.%s=%s: ", 410 410 p->driver, p->property, p->value); ··· 798 798 const char *value = va_arg(vargs, char *); 799 799 800 800 g_assert(value != NULL); 801 801 - object_property_parse(obj, value, propname, &local_err); 801 801 + object_property_parse(obj, propname, value, &local_err); 802 802 if (local_err) { 803 803 error_propagate(errp, local_err); 804 804 return -1; ··· 1312 1312 g_hash_table_remove(obj->properties, name); 1313 1313 } 1314 1314 1315 1315 - void object_property_get(Object *obj, Visitor *v, const char *name, 1315 1315 + void object_property_get(Object *obj, const char *name, Visitor *v, 1316 1316 Error **errp) 1317 1317 { 1318 1318 ObjectProperty *prop = object_property_find(obj, name, errp); ··· 1327 1327 } 1328 1328 } 1329 1329 1330 1330 - void object_property_set(Object *obj, Visitor *v, const char *name, 1330 1330 + void object_property_set(Object *obj, const char *name, Visitor *v, 1331 1331 Error **errp) 1332 1332 { 1333 1333 ObjectProperty *prop = object_property_find(obj, name, errp); ··· 1342 1342 } 1343 1343 } 1344 1344 1345 1345 - void object_property_set_str(Object *obj, const char *value, 1346 1346 - const char *name, Error **errp) 1345 1345 + void object_property_set_str(Object *obj, const char *name, 1346 1346 + const char *value, Error **errp) 1347 1347 { 1348 1348 QString *qstr = qstring_from_str(value); 1349 1349 - object_property_set_qobject(obj, QOBJECT(qstr), name, errp); 1349 1349 + object_property_set_qobject(obj, name, QOBJECT(qstr), errp); 1350 1350 1351 1351 qobject_unref(qstr); 1352 1352 } ··· 1370 1370 return retval; 1371 1371 } 1372 1372 1373 1373 - void object_property_set_link(Object *obj, Object *value, 1374 1374 - const char *name, Error **errp) 1373 1373 + void object_property_set_link(Object *obj, const char *name, 1374 1374 + Object *value, Error **errp) 1375 1375 { 1376 1376 if (value) { 1377 1377 char *path = object_get_canonical_path(value); 1378 1378 - object_property_set_str(obj, path, name, errp); 1378 1378 + object_property_set_str(obj, name, path, errp); 1379 1379 g_free(path); 1380 1380 } else { 1381 1381 - object_property_set_str(obj, "", name, errp); 1381 1381 + object_property_set_str(obj, name, "", errp); 1382 1382 } 1383 1383 } 1384 1384 ··· 1400 1400 return target; 1401 1401 } 1402 1402 1403 1403 - void object_property_set_bool(Object *obj, bool value, 1404 1404 - const char *name, Error **errp) 1403 1403 + void object_property_set_bool(Object *obj, const char *name, 1404 1404 + bool value, Error **errp) 1405 1405 { 1406 1406 QBool *qbool = qbool_from_bool(value); 1407 1407 - object_property_set_qobject(obj, QOBJECT(qbool), name, errp); 1407 1407 + object_property_set_qobject(obj, name, QOBJECT(qbool), errp); 1408 1408 1409 1409 qobject_unref(qbool); 1410 1410 } ··· 1431 1431 return retval; 1432 1432 } 1433 1433 1434 1434 - void object_property_set_int(Object *obj, int64_t value, 1435 1435 - const char *name, Error **errp) 1434 1434 + void object_property_set_int(Object *obj, const char *name, 1435 1435 + int64_t value, Error **errp) 1436 1436 { 1437 1437 QNum *qnum = qnum_from_int(value); 1438 1438 - object_property_set_qobject(obj, QOBJECT(qnum), name, errp); 1438 1438 + object_property_set_qobject(obj, name, QOBJECT(qnum), errp); 1439 1439 1440 1440 qobject_unref(qnum); 1441 1441 } ··· 1500 1500 object_property_set_default(prop, QOBJECT(qnum_from_uint(value))); 1501 1501 } 1502 1502 1503 1503 - void object_property_set_uint(Object *obj, uint64_t value, 1504 1504 - const char *name, Error **errp) 1503 1503 + void object_property_set_uint(Object *obj, const char *name, 1504 1504 + uint64_t value, Error **errp) 1505 1505 { 1506 1506 QNum *qnum = qnum_from_uint(value); 1507 1507 1508 1508 - object_property_set_qobject(obj, QOBJECT(qnum), name, errp); 1508 1508 + object_property_set_qobject(obj, name, QOBJECT(qnum), errp); 1509 1509 qobject_unref(qnum); 1510 1510 } 1511 1511 ··· 1567 1567 return ret; 1568 1568 } 1569 1569 1570 1570 - void object_property_parse(Object *obj, const char *string, 1571 1571 - const char *name, Error **errp) 1570 1570 + void object_property_parse(Object *obj, const char *name, 1571 1571 + const char *string, Error **errp) 1572 1572 { 1573 1573 Visitor *v = string_input_visitor_new(string); 1574 1574 - object_property_set(obj, v, name, errp); 1574 1574 + object_property_set(obj, name, v, errp); 1575 1575 visit_free(v); 1576 1576 } 1577 1577 ··· 1583 1583 Error *local_err = NULL; 1584 1584 1585 1585 v = string_output_visitor_new(human, &string); 1586 1586 - object_property_get(obj, v, name, &local_err); 1586 1586 + object_property_get(obj, name, v, &local_err); 1587 1587 if (local_err) { 1588 1588 error_propagate(errp, local_err); 1589 1589 goto out; ··· 2645 2645 { 2646 2646 AliasProperty *prop = opaque; 2647 2647 2648 2648 - object_property_get(prop->target_obj, v, prop->target_name, errp); 2648 2648 + object_property_get(prop->target_obj, prop->target_name, v, errp); 2649 2649 } 2650 2650 2651 2651 static void property_set_alias(Object *obj, Visitor *v, const char *name, ··· 2653 2653 { 2654 2654 AliasProperty *prop = opaque; 2655 2655 2656 2656 - object_property_set(prop->target_obj, v, prop->target_name, errp); 2656 2656 + object_property_set(prop->target_obj, prop->target_name, v, errp); 2657 2657 } 2658 2658 2659 2659 static Object *property_resolve_alias(Object *obj, void *opaque,

+1 -1

qom/object_interfaces.c

··· 67 67 goto out; 68 68 } 69 69 for (e = qdict_first(qdict); e; e = qdict_next(qdict, e)) { 70 70 - object_property_set(obj, v, e->key, &local_err); 70 70 + object_property_set(obj, e->key, v, &local_err); 71 71 if (local_err) { 72 72 break; 73 73 }

+1 -1

qom/qom-hmp-cmds.c

··· 57 57 error_set(&err, ERROR_CLASS_DEVICE_NOT_FOUND, 58 58 "Device '%s' not found", path); 59 59 } else { 60 60 - object_property_parse(obj, value, property, &err); 60 60 + object_property_parse(obj, property, value, &err); 61 61 } 62 62 } else { 63 63 QObject *obj = qobject_from_json(value, &err);

+1 -1

qom/qom-qmp-cmds.c

··· 71 71 return; 72 72 } 73 73 74 74 - object_property_set_qobject(obj, value, property, errp); 74 74 + object_property_set_qobject(obj, property, value, errp); 75 75 } 76 76 77 77 QObject *qmp_qom_get(const char *path, const char *property, Error **errp)

+5 -4

qom/qom-qobject.c

··· 17 17 #include "qapi/qobject-input-visitor.h" 18 18 #include "qapi/qobject-output-visitor.h" 19 19 20 20 - void object_property_set_qobject(Object *obj, QObject *value, 21 21 - const char *name, Error **errp) 20 20 + void object_property_set_qobject(Object *obj, 21 21 + const char *name, QObject *value, 22 22 + Error **errp) 22 23 { 23 24 Visitor *v; 24 25 25 26 v = qobject_input_visitor_new(value); 26 26 - object_property_set(obj, v, name, errp); 27 27 + object_property_set(obj, name, v, errp); 27 28 visit_free(v); 28 29 } 29 30 ··· 35 36 Visitor *v; 36 37 37 38 v = qobject_output_visitor_new(&ret); 38 38 - object_property_get(obj, v, name, &local_err); 39 39 + object_property_get(obj, name, v, &local_err); 39 40 if (!local_err) { 40 41 visit_complete(v, &ret); 41 42 }

+6 -6

softmmu/vl.c

··· 2469 2469 return 0; 2470 2470 } 2471 2471 2472 2472 - object_property_parse(obj, value, name, &local_err); 2472 2472 + object_property_parse(obj, name, value, &local_err); 2473 2473 2474 2474 if (local_err) { 2475 2475 error_propagate(errp, local_err); ··· 2817 2817 2818 2818 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 2819 2819 if (path) { 2820 2820 - object_property_set_str(obj, path, "mem-path", &error_fatal); 2820 2820 + object_property_set_str(obj, "mem-path", path, &error_fatal); 2821 2821 } 2822 2822 - object_property_set_int(obj, ms->ram_size, "size", &error_fatal); 2822 2822 + object_property_set_int(obj, "size", ms->ram_size, &error_fatal); 2823 2823 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 2824 2824 obj); 2825 2825 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 2826 2826 - object_property_set_bool(obj, false, "x-use-canonical-path-for-ramblock-id", 2827 2827 - &error_fatal); 2826 2826 + object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 2827 2827 + false, &error_fatal); 2828 2828 user_creatable_complete(USER_CREATABLE(obj), &error_fatal); 2829 2829 object_unref(obj); 2830 2830 - object_property_set_str(OBJECT(ms), mc->default_ram_id, "memory-backend", 2830 2830 + object_property_set_str(OBJECT(ms), "memory-backend", mc->default_ram_id, 2831 2831 &error_fatal); 2832 2832 } 2833 2833

+1 -1

target/arm/monitor.c

··· 184 184 i = 0; 185 185 while ((name = cpu_model_advertised_features[i++]) != NULL) { 186 186 if (qdict_get(qdict_in, name)) { 187 187 - object_property_set(obj, visitor, name, &err); 187 187 + object_property_set(obj, name, visitor, &err); 188 188 if (err) { 189 189 break; 190 190 }

+27 -30

target/i386/cpu.c

··· 4260 4260 host_vendor_fms(vendor, &family, &model, &stepping); 4261 4261 cpu_x86_fill_model_id(model_id); 4262 4262 4263 4263 - object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort); 4264 4264 - object_property_set_int(OBJECT(cpu), family, "family", &error_abort); 4265 4265 - object_property_set_int(OBJECT(cpu), model, "model", &error_abort); 4266 4266 - object_property_set_int(OBJECT(cpu), stepping, "stepping", 4263 4263 + object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 4264 4264 + object_property_set_int(OBJECT(cpu), "family", family, &error_abort); 4265 4265 + object_property_set_int(OBJECT(cpu), "model", model, &error_abort); 4266 4266 + object_property_set_int(OBJECT(cpu), "stepping", stepping, 4267 4267 &error_abort); 4268 4268 - object_property_set_str(OBJECT(cpu), model_id, "model-id", 4268 4268 + object_property_set_str(OBJECT(cpu), "model-id", model_id, 4269 4269 &error_abort); 4270 4270 4271 4271 if (kvm_enabled()) { ··· 4285 4285 } 4286 4286 4287 4287 if (lmce_supported()) { 4288 4288 - object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort); 4288 4288 + object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort); 4289 4289 } 4290 4290 } else { 4291 4291 - object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD, 4292 4292 - "vendor", &error_abort); 4293 4293 - object_property_set_int(OBJECT(cpu), 6, "family", &error_abort); 4294 4294 - object_property_set_int(OBJECT(cpu), 6, "model", &error_abort); 4295 4295 - object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort); 4296 4296 - object_property_set_str(OBJECT(cpu), 4291 4291 + object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4292 4292 + &error_abort); 4293 4293 + object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); 4294 4294 + object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); 4295 4295 + object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); 4296 4296 + object_property_set_str(OBJECT(cpu), "model-id", 4297 4297 "QEMU TCG CPU version " QEMU_HW_VERSION, 4298 4298 - "model-id", &error_abort); 4298 4298 + &error_abort); 4299 4299 } 4300 4300 4301 4301 - object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort); 4301 4301 + object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4302 4302 } 4303 4303 4304 4304 static const TypeInfo max_x86_cpu_type_info = { ··· 5067 5067 if (!pv->value) { 5068 5068 continue; 5069 5069 } 5070 5070 - object_property_parse(OBJECT(cpu), pv->value, pv->prop, 5070 5070 + object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5071 5071 &error_abort); 5072 5072 } 5073 5073 } ··· 5086 5086 PropValue *p; 5087 5087 5088 5088 for (p = vdef->props; p && p->prop; p++) { 5089 5089 - object_property_parse(OBJECT(cpu), p->value, p->prop, 5089 5089 + object_property_parse(OBJECT(cpu), p->prop, p->value, 5090 5090 &error_abort); 5091 5091 } 5092 5092 ··· 5117 5117 */ 5118 5118 5119 5119 /* CPU models only set _minimum_ values for level/xlevel: */ 5120 5120 - object_property_set_uint(OBJECT(cpu), def->level, "min-level", 5120 5120 + object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5121 5121 &error_abort); 5122 5122 - object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", 5122 5122 + object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5123 5123 &error_abort); 5124 5124 5125 5125 - object_property_set_int(OBJECT(cpu), def->family, "family", 5125 5125 + object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5126 5126 + object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5127 5127 + object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5126 5128 &error_abort); 5127 5127 - object_property_set_int(OBJECT(cpu), def->model, "model", 5128 5128 - &error_abort); 5129 5129 - object_property_set_int(OBJECT(cpu), def->stepping, "stepping", 5130 5130 - &error_abort); 5131 5131 - object_property_set_str(OBJECT(cpu), def->model_id, "model-id", 5129 5129 + object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5132 5130 &error_abort); 5133 5131 for (w = 0; w < FEATURE_WORDS; w++) { 5134 5132 env->features[w] = def->features[w]; ··· 5166 5164 vendor = host_vendor; 5167 5165 } 5168 5166 5169 5169 - object_property_set_str(OBJECT(cpu), vendor, "vendor", 5170 5170 - &error_abort); 5167 5167 + object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 5171 5168 5172 5169 x86_cpu_apply_version_props(cpu, model); 5173 5170 } ··· 5274 5271 Error *err = NULL; 5275 5272 5276 5273 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) { 5277 5277 - object_property_set_qobject(obj, qdict_entry_value(prop), 5278 5278 - qdict_entry_key(prop), &err); 5274 5274 + object_property_set_qobject(obj, qdict_entry_key(prop), 5275 5275 + qdict_entry_value(prop), &err); 5279 5276 if (err) { 5280 5277 break; 5281 5278 } ··· 6343 6340 6344 6341 for (l = plus_features; l; l = l->next) { 6345 6342 const char *prop = l->data; 6346 6346 - object_property_set_bool(OBJECT(cpu), true, prop, &local_err); 6343 6343 + object_property_set_bool(OBJECT(cpu), prop, true, &local_err); 6347 6344 if (local_err) { 6348 6345 goto out; 6349 6346 } ··· 6351 6348 6352 6349 for (l = minus_features; l; l = l->next) { 6353 6350 const char *prop = l->data; 6354 6354 - object_property_set_bool(OBJECT(cpu), false, prop, &local_err); 6351 6351 + object_property_set_bool(OBJECT(cpu), prop, false, &local_err); 6355 6352 if (local_err) { 6356 6353 goto out; 6357 6354 }

+1 -1

target/ppc/translate_init.inc.c

··· 10482 10482 10483 10483 if (compat_str) { 10484 10484 char *v = compat_str + strlen("compat="); 10485 10485 - object_property_set_str(machine, v, "max-cpu-compat", &local_err); 10485 10485 + object_property_set_str(machine, "max-cpu-compat", v, &local_err); 10486 10486 } 10487 10487 g_strfreev(inpieces); 10488 10488 if (local_err) {

+1 -1

target/s390x/cpu_models.c

··· 517 517 return; 518 518 } 519 519 for (e = qdict_first(qdict); e; e = qdict_next(qdict, e)) { 520 520 - object_property_set(obj, visitor, e->key, &err); 520 520 + object_property_set(obj, e->key, visitor, &err); 521 521 if (err) { 522 522 break; 523 523 }

+2 -2

ui/console.c

··· 1910 1910 } 1911 1911 graphic_console_set_hwops(s, hw_ops, opaque); 1912 1912 if (dev) { 1913 1913 - object_property_set_link(OBJECT(s), OBJECT(dev), "device", 1913 1913 + object_property_set_link(OBJECT(s), "device", OBJECT(dev), 1914 1914 &error_abort); 1915 1915 } 1916 1916 ··· 1937 1937 } 1938 1938 1939 1939 trace_console_gfx_close(con->index); 1940 1940 - object_property_set_link(OBJECT(con), NULL, "device", &error_abort); 1940 1940 + object_property_set_link(OBJECT(con), "device", NULL, &error_abort); 1941 1941 graphic_console_set_hwops(con, &unused_ops, NULL); 1942 1942 1943 1943 if (con->gl) {