jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
xilinx_spips: Set all of the reset values
Following the ZynqMP register spec let's ensure that all reset values
are set.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 19836f3e0a298b13343c5a59c87425355e7fd8bd.1513104804.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Alistair Francis
and committed by
Peter Maydell
4f0da466
cbf8b991
+31
-6
+30
-5
hw/ssi/xilinx_spips.c
+30
-5
hw/ssi/xilinx_spips.c
···
66
66
67
67
/* interrupt mechanism */
68
68
#define R_INTR_STATUS (0x04 / 4)
69
+
#define R_INTR_STATUS_RESET (0x104)
69
70
#define R_INTR_EN (0x08 / 4)
70
71
#define R_INTR_DIS (0x0C / 4)
71
72
#define R_INTR_MASK (0x10 / 4)
···
102
103
#define R_SLAVE_IDLE_COUNT (0x24 / 4)
103
104
#define R_TX_THRES (0x28 / 4)
104
105
#define R_RX_THRES (0x2C / 4)
106
+
#define R_GPIO (0x30 / 4)
107
+
#define R_LPBK_DLY_ADJ (0x38 / 4)
108
+
#define R_LPBK_DLY_ADJ_RESET (0x33)
105
109
#define R_TXD1 (0x80 / 4)
106
110
#define R_TXD2 (0x84 / 4)
107
111
#define R_TXD3 (0x88 / 4)
···
140
144
#define R_GQSPI_IER (0x108 / 4)
141
145
#define R_GQSPI_IDR (0x10c / 4)
142
146
#define R_GQSPI_IMR (0x110 / 4)
147
+
#define R_GQSPI_IMR_RESET (0xfbe)
143
148
#define R_GQSPI_TX_THRESH (0x128 / 4)
144
149
#define R_GQSPI_RX_THRESH (0x12c / 4)
150
+
#define R_GQSPI_GPIO (0x130 / 4)
151
+
#define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4)
152
+
#define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33)
145
153
#define R_GQSPI_CNFG (0x100 / 4)
146
154
FIELD(GQSPI_CNFG, MODE_EN, 30, 2)
147
155
FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1)
···
177
185
FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1)
178
186
FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1)
179
187
FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8)
180
-
#define R_GQSPI_MOD_ID (0x168 / 4)
181
-
#define R_GQSPI_MOD_ID_VALUE 0x010A0000
188
+
#define R_GQSPI_MOD_ID (0x1fc / 4)
189
+
#define R_GQSPI_MOD_ID_RESET (0x10a0000)
190
+
191
+
#define R_QSPIDMA_DST_CTRL (0x80c / 4)
192
+
#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00)
193
+
#define R_QSPIDMA_DST_I_MASK (0x820 / 4)
194
+
#define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
195
+
#define R_QSPIDMA_DST_CTRL2 (0x824 / 4)
196
+
#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8)
197
+
182
198
/* size of TXRX FIFOs */
183
199
#define RXFF_A (128)
184
200
#define TXFF_A (128)
···
351
367
fifo8_reset(&s->rx_fifo_g);
352
368
fifo8_reset(&s->rx_fifo_g);
353
369
fifo32_reset(&s->fifo_g);
370
+
s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
371
+
s->regs[R_GPIO] = 1;
372
+
s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET;
373
+
s->regs[R_GQSPI_GFIFO_THRESH] = 0x10;
374
+
s->regs[R_MOD_ID] = 0x01090101;
375
+
s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET;
354
376
s->regs[R_GQSPI_TX_THRESH] = 1;
355
377
s->regs[R_GQSPI_RX_THRESH] = 1;
356
-
s->regs[R_GQSPI_GFIFO_THRESH] = 1;
357
-
s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;
358
-
s->regs[R_MOD_ID] = 0x01090101;
378
+
s->regs[R_GQSPI_GPIO] = 1;
379
+
s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET;
380
+
s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET;
381
+
s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET;
382
+
s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET;
383
+
s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET;
359
384
s->man_start_com_g = false;
360
385
s->gqspi_irqline = 0;
361
386
xlnx_zynqmp_qspips_update_ixr(s);
+1
-1
include/hw/ssi/xilinx_spips.h
+1
-1
include/hw/ssi/xilinx_spips.h