jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-05-30' into staging
- Replace hw_error() with qemu_log_mask() in the m68k coldfire machine code
# gpg: Signature made Sat 30 May 2020 08:44:41 BST
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "huth@tuxfamily.org"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* remotes/huth-gitlab/tags/pull-request-2020-05-30:
hw/m68k/mcf52xx: Replace hw_error() by qemu_log_mask()
hw/m68k/mcf5206: Reduce m5206_mbar_read/write() offset arg to 16-bit
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+32
-17
+9
-5
hw/m68k/mcf5206.c
+9
-5
hw/m68k/mcf5206.c
···
8
8
9
9
#include "qemu/osdep.h"
10
10
#include "qemu/error-report.h"
11
+
#include "qemu/log.h"
11
12
#include "cpu.h"
12
13
#include "hw/hw.h"
13
14
#include "hw/irq.h"
···
225
226
break;
226
227
default:
227
228
/* Unknown vector. */
228
-
error_report("Unhandled vector for IRQ %d", irq);
229
+
qemu_log_mask(LOG_UNIMP, "%s: Unhandled vector for IRQ %d\n",
230
+
__func__, irq);
229
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vector = 0xf;
230
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break;
231
233
}
···
273
275
}
274
276
275
277
static uint64_t m5206_mbar_read(m5206_mbar_state *s,
276
-
uint64_t offset, unsigned size)
278
+
uint16_t offset, unsigned size)
277
279
{
278
280
if (offset >= 0x100 && offset < 0x120) {
279
281
return m5206_timer_read(s->timer[0], offset - 0x100);
···
306
308
case 0x170: return s->uivr[0];
307
309
case 0x1b0: return s->uivr[1];
308
310
}
309
-
hw_error("Bad MBAR read offset 0x%x", (int)offset);
311
+
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad MBAR offset 0x%"PRIx16"\n",
312
+
__func__, offset);
310
313
return 0;
311
314
}
312
315
313
-
static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
316
+
static void m5206_mbar_write(m5206_mbar_state *s, uint16_t offset,
314
317
uint64_t value, unsigned size)
315
318
{
316
319
if (offset >= 0x100 && offset < 0x120) {
···
360
363
s->uivr[1] = value;
361
364
break;
362
365
default:
363
-
hw_error("Bad MBAR write offset 0x%x", (int)offset);
366
+
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad MBAR offset 0x%"PRIx16"\n",
367
+
__func__, offset);
364
368
break;
365
369
}
366
370
}
+10
-6
hw/m68k/mcf5208.c
+10
-6
hw/m68k/mcf5208.c
···
9
9
#include "qemu/osdep.h"
10
10
#include "qemu/units.h"
11
11
#include "qemu/error-report.h"
12
+
#include "qemu/log.h"
12
13
#include "qapi/error.h"
13
14
#include "qemu-common.h"
14
15
#include "cpu.h"
15
-
#include "hw/hw.h"
16
16
#include "hw/irq.h"
17
17
#include "hw/m68k/mcf.h"
18
18
#include "hw/m68k/mcf_fec.h"
···
111
111
case 4:
112
112
break;
113
113
default:
114
-
hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
115
-
break;
114
+
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
115
+
__func__, offset);
116
+
return;
116
117
}
117
118
m5208_timer_update(s);
118
119
}
···
136
137
case 4:
137
138
return ptimer_get_count(s->timer);
138
139
default:
139
-
hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
140
+
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
141
+
__func__, addr);
140
142
return 0;
141
143
}
142
144
}
···
164
166
return 0;
165
167
166
168
default:
167
-
hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
169
+
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
170
+
__func__, addr);
168
171
return 0;
169
172
}
170
173
}
···
172
175
static void m5208_sys_write(void *opaque, hwaddr addr,
173
176
uint64_t value, unsigned size)
174
177
{
175
-
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
178
+
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
179
+
__func__, addr);
176
180
}
177
181
178
182
static const MemoryRegionOps m5208_sys_ops = {
+7
-3
hw/m68k/mcf_intc.c
+7
-3
hw/m68k/mcf_intc.c
···
8
8
9
9
#include "qemu/osdep.h"
10
10
#include "qemu/module.h"
11
+
#include "qemu/log.h"
11
12
#include "cpu.h"
12
13
#include "hw/hw.h"
13
14
#include "hw/irq.h"
···
80
81
case 0xe1: case 0xe2: case 0xe3: case 0xe4:
81
82
case 0xe5: case 0xe6: case 0xe7:
82
83
/* LnIACK */
83
-
hw_error("mcf_intc_read: LnIACK not implemented\n");
84
+
qemu_log_mask(LOG_UNIMP, "%s: LnIACK not implemented (offset 0x%02x)\n",
85
+
__func__, offset);
86
+
/* fallthru */
84
87
default:
85
88
return 0;
86
89
}
···
127
130
}
128
131
break;
129
132
default:
130
-
hw_error("mcf_intc_write: Bad write offset %d\n", offset);
131
-
break;
133
+
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n",
134
+
__func__, offset);
135
+
return;
132
136
}
133
137
mcf_intc_update(s);
134
138
}
+6
-3
hw/net/mcf_fec.c
+6
-3
hw/net/mcf_fec.c
···
7
7
*/
8
8
9
9
#include "qemu/osdep.h"
10
-
#include "hw/hw.h"
10
+
#include "qemu/log.h"
11
11
#include "hw/irq.h"
12
12
#include "net/net.h"
13
13
#include "qemu/module.h"
···
392
392
case 0x188: return s->emrbr;
393
393
case 0x200 ... 0x2e0: return s->mib[(addr & 0x1ff) / 4];
394
394
default:
395
-
hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
395
+
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" HWADDR_PRIX "\n",
396
+
__func__, addr);
396
397
return 0;
397
398
}
398
399
}
···
492
493
s->mib[(addr & 0x1ff) / 4] = value;
493
494
break;
494
495
default:
495
-
hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
496
+
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" HWADDR_PRIX "\n",
497
+
__func__, addr);
498
+
return;
496
499
}
497
500
mcf_fec_update(s);
498
501
}