jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
test: lm32: use semihosting for testing
Instead of the lm32-sys device, use semihosting to print to the host
console and exit the test.
Signed-off-by: Michael Walle <michael@walle.cc>
+103
-22
+8
-7
tests/tcg/lm32/Makefile
+8
-7
tests/tcg/lm32/Makefile
···
3
3
CROSS=lm32-elf-
4
4
5
5
SIM = qemu-system-lm32
6
-
SIMFLAGS = -M lm32-evr -nographic -device lm32-sys -net none -kernel
6
+
SIMFLAGS = -M lm32-evr -nographic -semihosting -net none -kernel
7
7
8
8
CC = $(CROSS)gcc
9
9
AS = $(CROSS)as
···
18
18
ASFLAGS += -Wa,-I,$(TSRC_PATH)/
19
19
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CRT = crt.o
21
+
HELPER = helper.o
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TESTCASES += test_add.tst
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TESTCASES += test_addi.tst
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24
TESTCASES += test_and.tst
···
91
92
%.o: $(TSRC_PATH)/%.S
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$(AS) $(ASFLAGS) -c $< -o $@
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-
%.tst: %.o $(TSRC_PATH)/macros.inc $(CRT)
95
-
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@
95
+
%.tst: %.o $(TSRC_PATH)/macros.inc $(CRT) $(HELPER)
96
+
$(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $(HELPER) $< -o $@
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-
build: $(CRT) $(TESTCASES)
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+
build: $(TESTCASES)
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check: $(TESTCASES:test_%.tst=check_%)
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-
check_%: test_%.tst $(CRT) $(SYS)
102
-
$(SIM) $(SIMFLAGS) $<
102
+
check_%: test_%.tst
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+
@$(SIM) $(SIMFLAGS) $<
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clean:
105
-
$(RM) -fr $(TESTCASES) $(CRT)
106
+
$(RM) -fr $(TESTCASES) $(CRT) $(HELPER)
+2
-2
tests/tcg/lm32/crt.S
+2
-2
tests/tcg/lm32/crt.S
+65
tests/tcg/lm32/helper.S
+65
tests/tcg/lm32/helper.S
···
1
+
.text
2
+
.global _start, _write, _exit
3
+
.global _tc_fail, _tc_pass
4
+
5
+
_write:
6
+
addi sp, sp, -4
7
+
sw (sp+4), r8
8
+
mvi r8, 5
9
+
scall
10
+
lw r8, (sp+4)
11
+
addi sp, sp, 4
12
+
ret
13
+
14
+
_exit:
15
+
mvi r8, 1
16
+
scall
17
+
1:
18
+
bi 1b
19
+
20
+
_tc_pass:
21
+
.data
22
+
1:
23
+
.ascii "OK\n"
24
+
2:
25
+
.text
26
+
addi sp, sp, -16
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+
sw (sp+4), ra
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+
sw (sp+8), r1
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+
sw (sp+12), r2
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+
sw (sp+16), r3
31
+
mvi r1, 1
32
+
mvhi r2, hi(1b)
33
+
ori r2, r2, lo(1b)
34
+
mvi r3, (2b - 1b)
35
+
calli _write
36
+
lw r3, (sp+16)
37
+
lw r2, (sp+12)
38
+
lw r1, (sp+8)
39
+
lw ra, (sp+4)
40
+
addi sp, sp, 16
41
+
ret
42
+
43
+
_tc_fail:
44
+
.data
45
+
1:
46
+
.ascii "FAILED\n"
47
+
2:
48
+
.text
49
+
addi sp, sp, -16
50
+
sw (sp+4), ra
51
+
sw (sp+8), r1
52
+
sw (sp+12), r2
53
+
sw (sp+16), r3
54
+
sw (sp+4), ra
55
+
mvi r1, 1
56
+
mvhi r2, hi(1b)
57
+
ori r2, r2, lo(1b)
58
+
mvi r3, (2b - 1b)
59
+
calli _write
60
+
lw r3, (sp+16)
61
+
lw r2, (sp+12)
62
+
lw r1, (sp+8)
63
+
lw ra, (sp+4)
64
+
addi sp, sp, 16
65
+
ret
+24
-13
tests/tcg/lm32/macros.inc
+24
-13
tests/tcg/lm32/macros.inc
···
1
1
2
+
.equ MAX_TESTNAME_LEN, 32
2
3
.macro test_name name
3
4
.data
4
5
tn_\name:
5
-
.asciz "\name"
6
+
.ascii "\name"
7
+
.space MAX_TESTNAME_LEN - (. - tn_\name), ' '
6
8
.text
7
-
mvhi r13, hi(tn_\name)
8
-
ori r13, r13, lo(tn_\name)
9
-
sw (r12+8), r13
9
+
.global \name
10
+
\name:
11
+
addi sp, sp, -12
12
+
sw (sp+4), r1
13
+
sw (sp+8), r2
14
+
sw (sp+12), r3
15
+
mvi r1, 1
16
+
mvhi r2, hi(tn_\name)
17
+
ori r2, r2, lo(tn_\name)
18
+
mvi r3, MAX_TESTNAME_LEN
19
+
calli _write
20
+
lw r3, (sp+12)
21
+
lw r2, (sp+8)
22
+
lw r1, (sp+4)
23
+
addi sp, sp, 12
10
24
.endm
11
25
12
26
.macro load reg val
···
15
29
.endm
16
30
17
31
.macro tc_pass
18
-
mvi r13, 0
19
-
sw (r12+4), r13
32
+
calli _tc_pass
20
33
.endm
21
34
22
35
.macro tc_fail
23
-
mvi r13, 1
24
-
sw (r12+4), r13
36
+
addi r12, r12, 1
37
+
calli _tc_fail
25
38
.endm
26
39
27
40
.macro check_r3 val
···
63
76
.global _main
64
77
.text
65
78
_main:
66
-
mvhi r12, hi(0xffff0000) # base address of test block
67
-
ori r12, r12, lo(0xffff0000)
79
+
mvi r12, 0
68
80
.endm
69
81
70
82
.macro end
71
-
sw (r12+0), r0
72
-
1:
73
-
bi 1b
83
+
mv r1, r12
84
+
calli _exit
74
85
.endm
75
86
76
87
# base +