jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
bcm2835_sdhost: add bcm2835 sdhost controller
This adds the BCM2835 SDHost controller from Arasan.
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
Message-id: 20170224164021.9066-2-clement.deschamps@antfield.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Clement Deschamps
and committed by
Peter Maydell
43ddc182
5db53e35
+478
+1
hw/sd/Makefile.objs
+1
hw/sd/Makefile.objs
+429
hw/sd/bcm2835_sdhost.c
+429
hw/sd/bcm2835_sdhost.c
···
1
+
/*
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* Raspberry Pi (BCM2835) SD Host Controller
3
+
*
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* Copyright (c) 2017 Antfield SAS
5
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*
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* Authors:
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* Clement Deschamps <clement.deschamps@antfield.fr>
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* Luc Michel <luc.michel@antfield.fr>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "sysemu/blockdev.h"
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#include "hw/sd/bcm2835_sdhost.h"
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+
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#define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus"
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#define BCM2835_SDHOST_BUS(obj) \
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OBJECT_CHECK(SDBus, (obj), TYPE_BCM2835_SDHOST_BUS)
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+
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#define SDCMD 0x00 /* Command to SD card - 16 R/W */
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#define SDARG 0x04 /* Argument to SD card - 32 R/W */
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#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
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#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
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#define SDRSP0 0x10 /* SD card rsp (31:0) - 32 R */
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#define SDRSP1 0x14 /* SD card rsp (63:32) - 32 R */
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#define SDRSP2 0x18 /* SD card rsp (95:64) - 32 R */
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#define SDRSP3 0x1c /* SD card rsp (127:96) - 32 R */
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#define SDHSTS 0x20 /* SD host status - 11 R */
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#define SDVDD 0x30 /* SD card power control - 1 R/W */
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#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
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#define SDHCFG 0x38 /* Host configuration - 2 R/W */
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#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
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#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
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#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
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+
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#define SDCMD_NEW_FLAG 0x8000
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#define SDCMD_FAIL_FLAG 0x4000
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#define SDCMD_BUSYWAIT 0x800
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#define SDCMD_NO_RESPONSE 0x400
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#define SDCMD_LONG_RESPONSE 0x200
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#define SDCMD_WRITE_CMD 0x80
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#define SDCMD_READ_CMD 0x40
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#define SDCMD_CMD_MASK 0x3f
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+
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#define SDCDIV_MAX_CDIV 0x7ff
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+
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#define SDHSTS_BUSY_IRPT 0x400
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#define SDHSTS_BLOCK_IRPT 0x200
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#define SDHSTS_SDIO_IRPT 0x100
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#define SDHSTS_REW_TIME_OUT 0x80
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#define SDHSTS_CMD_TIME_OUT 0x40
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#define SDHSTS_CRC16_ERROR 0x20
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#define SDHSTS_CRC7_ERROR 0x10
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#define SDHSTS_FIFO_ERROR 0x08
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/* Reserved */
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/* Reserved */
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#define SDHSTS_DATA_FLAG 0x01
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+
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#define SDHCFG_BUSY_IRPT_EN (1 << 10)
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#define SDHCFG_BLOCK_IRPT_EN (1 << 8)
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#define SDHCFG_SDIO_IRPT_EN (1 << 5)
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#define SDHCFG_DATA_IRPT_EN (1 << 4)
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#define SDHCFG_SLOW_CARD (1 << 3)
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#define SDHCFG_WIDE_EXT_BUS (1 << 2)
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#define SDHCFG_WIDE_INT_BUS (1 << 1)
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#define SDHCFG_REL_CMD_LINE (1 << 0)
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+
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#define SDEDM_FORCE_DATA_MODE (1 << 19)
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#define SDEDM_CLOCK_PULSE (1 << 20)
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#define SDEDM_BYPASS (1 << 21)
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+
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#define SDEDM_WRITE_THRESHOLD_SHIFT 9
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#define SDEDM_READ_THRESHOLD_SHIFT 14
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#define SDEDM_THRESHOLD_MASK 0x1f
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+
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#define SDEDM_FSM_MASK 0xf
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#define SDEDM_FSM_IDENTMODE 0x0
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#define SDEDM_FSM_DATAMODE 0x1
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#define SDEDM_FSM_READDATA 0x2
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#define SDEDM_FSM_WRITEDATA 0x3
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#define SDEDM_FSM_READWAIT 0x4
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#define SDEDM_FSM_READCRC 0x5
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#define SDEDM_FSM_WRITECRC 0x6
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#define SDEDM_FSM_WRITEWAIT1 0x7
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#define SDEDM_FSM_POWERDOWN 0x8
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#define SDEDM_FSM_POWERUP 0x9
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#define SDEDM_FSM_WRITESTART1 0xa
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#define SDEDM_FSM_WRITESTART2 0xb
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#define SDEDM_FSM_GENPULSES 0xc
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#define SDEDM_FSM_WRITEWAIT2 0xd
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#define SDEDM_FSM_STARTPOWDOWN 0xf
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#define SDDATA_FIFO_WORDS 16
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static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s)
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{
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uint32_t irq = s->status &
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(SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT);
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qemu_set_irq(s->irq, !!irq);
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}
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static void bcm2835_sdhost_send_command(BCM2835SDHostState *s)
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{
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SDRequest request;
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uint8_t rsp[16];
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int rlen;
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request.cmd = s->cmd & SDCMD_CMD_MASK;
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request.arg = s->cmdarg;
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rlen = sdbus_do_command(&s->sdbus, &request, rsp);
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if (rlen < 0) {
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goto error;
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}
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if (!(s->cmd & SDCMD_NO_RESPONSE)) {
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#define RWORD(n) (((uint32_t)rsp[n] << 24) | (rsp[n + 1] << 16) \
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| (rsp[n + 2] << 8) | rsp[n + 3])
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if (rlen == 0 || (rlen == 4 && (s->cmd & SDCMD_LONG_RESPONSE))) {
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goto error;
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}
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if (rlen != 4 && rlen != 16) {
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goto error;
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}
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if (rlen == 4) {
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s->rsp[0] = RWORD(0);
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s->rsp[1] = s->rsp[2] = s->rsp[3] = 0;
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} else {
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s->rsp[0] = RWORD(12);
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s->rsp[1] = RWORD(8);
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s->rsp[2] = RWORD(4);
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s->rsp[3] = RWORD(0);
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}
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#undef RWORD
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}
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return;
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+
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error:
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s->cmd |= SDCMD_FAIL_FLAG;
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s->status |= SDHSTS_CMD_TIME_OUT;
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}
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static void bcm2835_sdhost_fifo_push(BCM2835SDHostState *s, uint32_t value)
146
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{
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int n;
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if (s->fifo_len == BCM2835_SDHOST_FIFO_LEN) {
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/* FIFO overflow */
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return;
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}
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n = (s->fifo_pos + s->fifo_len) & (BCM2835_SDHOST_FIFO_LEN - 1);
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s->fifo_len++;
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s->fifo[n] = value;
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}
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static uint32_t bcm2835_sdhost_fifo_pop(BCM2835SDHostState *s)
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{
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uint32_t value;
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+
162
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if (s->fifo_len == 0) {
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/* FIFO underflow */
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return 0;
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}
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value = s->fifo[s->fifo_pos];
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s->fifo_len--;
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s->fifo_pos = (s->fifo_pos + 1) & (BCM2835_SDHOST_FIFO_LEN - 1);
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return value;
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}
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static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
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{
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uint32_t value = 0;
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int n;
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int is_read;
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+
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is_read = (s->cmd & SDCMD_READ_CMD) != 0;
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if (s->datacnt != 0 && (!is_read || sdbus_data_ready(&s->sdbus))) {
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if (is_read) {
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n = 0;
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while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) {
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value |= (uint32_t)sdbus_read_data(&s->sdbus) << (n * 8);
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s->datacnt--;
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n++;
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if (n == 4) {
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bcm2835_sdhost_fifo_push(s, value);
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n = 0;
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value = 0;
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}
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}
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if (n != 0) {
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bcm2835_sdhost_fifo_push(s, value);
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}
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} else { /* write */
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n = 0;
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while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) {
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if (n == 0) {
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value = bcm2835_sdhost_fifo_pop(s);
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n = 4;
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}
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n--;
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s->datacnt--;
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sdbus_write_data(&s->sdbus, value & 0xff);
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value >>= 8;
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}
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}
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}
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if (s->datacnt == 0) {
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s->status |= SDHSTS_DATA_FLAG;
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s->edm &= ~0xf;
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s->edm |= SDEDM_FSM_DATAMODE;
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+
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if (s->config & SDHCFG_DATA_IRPT_EN) {
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s->status |= SDHSTS_SDIO_IRPT;
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}
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if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
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s->status |= SDHSTS_BUSY_IRPT;
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}
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if ((s->cmd & SDCMD_WRITE_CMD) && (s->config & SDHCFG_BLOCK_IRPT_EN)) {
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s->status |= SDHSTS_BLOCK_IRPT;
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}
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bcm2835_sdhost_update_irq(s);
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}
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s->edm &= ~(0x1f << 4);
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s->edm |= ((s->fifo_len & 0x1f) << 4);
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}
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static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
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uint32_t res = 0;
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+
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switch (offset) {
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case SDCMD:
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res = s->cmd;
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break;
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case SDHSTS:
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res = s->status;
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break;
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case SDRSP0:
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res = s->rsp[0];
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break;
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case SDRSP1:
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res = s->rsp[1];
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break;
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case SDRSP2:
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res = s->rsp[2];
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break;
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case SDRSP3:
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res = s->rsp[3];
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break;
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case SDEDM:
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res = s->edm;
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break;
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case SDVDD:
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res = s->vdd;
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break;
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case SDDATA:
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res = bcm2835_sdhost_fifo_pop(s);
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bcm2835_sdhost_fifo_run(s);
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break;
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case SDHBCT:
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res = s->hbct;
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break;
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case SDHBLC:
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res = s->hblc;
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break;
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+
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
278
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__func__, offset);
279
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res = 0;
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break;
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}
282
+
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return res;
284
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}
285
+
286
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static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
287
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uint64_t value, unsigned size)
288
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{
289
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BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
290
+
291
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switch (offset) {
292
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case SDCMD:
293
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s->cmd = value;
294
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if (value & SDCMD_NEW_FLAG) {
295
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bcm2835_sdhost_send_command(s);
296
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bcm2835_sdhost_fifo_run(s);
297
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s->cmd &= ~SDCMD_NEW_FLAG;
298
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}
299
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break;
300
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case SDTOUT:
301
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break;
302
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case SDCDIV:
303
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break;
304
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case SDHSTS:
305
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s->status &= ~value;
306
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bcm2835_sdhost_update_irq(s);
307
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break;
308
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case SDARG:
309
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s->cmdarg = value;
310
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break;
311
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case SDEDM:
312
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if ((value & 0xf) == 0xf) {
313
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/* power down */
314
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value &= ~0xf;
315
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}
316
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s->edm = value;
317
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break;
318
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case SDHCFG:
319
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s->config = value;
320
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bcm2835_sdhost_fifo_run(s);
321
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break;
322
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case SDVDD:
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s->vdd = value;
324
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break;
325
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case SDDATA:
326
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bcm2835_sdhost_fifo_push(s, value);
327
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bcm2835_sdhost_fifo_run(s);
328
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break;
329
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case SDHBCT:
330
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s->hbct = value;
331
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break;
332
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case SDHBLC:
333
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s->hblc = value;
334
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s->datacnt = s->hblc * s->hbct;
335
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bcm2835_sdhost_fifo_run(s);
336
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break;
337
+
338
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default:
339
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
340
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__func__, offset);
341
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break;
342
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}
343
+
}
344
+
345
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static const MemoryRegionOps bcm2835_sdhost_ops = {
346
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.read = bcm2835_sdhost_read,
347
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.write = bcm2835_sdhost_write,
348
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.endianness = DEVICE_NATIVE_ENDIAN,
349
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};
350
+
351
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static const VMStateDescription vmstate_bcm2835_sdhost = {
352
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.name = TYPE_BCM2835_SDHOST,
353
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.version_id = 1,
354
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.minimum_version_id = 1,
355
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.fields = (VMStateField[]) {
356
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VMSTATE_UINT32(cmd, BCM2835SDHostState),
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VMSTATE_UINT32(cmdarg, BCM2835SDHostState),
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VMSTATE_UINT32(status, BCM2835SDHostState),
359
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VMSTATE_UINT32_ARRAY(rsp, BCM2835SDHostState, 4),
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VMSTATE_UINT32(config, BCM2835SDHostState),
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VMSTATE_UINT32(edm, BCM2835SDHostState),
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VMSTATE_UINT32(vdd, BCM2835SDHostState),
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VMSTATE_UINT32(hbct, BCM2835SDHostState),
364
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VMSTATE_UINT32(hblc, BCM2835SDHostState),
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VMSTATE_INT32(fifo_pos, BCM2835SDHostState),
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VMSTATE_INT32(fifo_len, BCM2835SDHostState),
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VMSTATE_UINT32_ARRAY(fifo, BCM2835SDHostState, BCM2835_SDHOST_FIFO_LEN),
368
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VMSTATE_UINT32(datacnt, BCM2835SDHostState),
369
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VMSTATE_END_OF_LIST()
370
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}
371
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};
372
+
373
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static void bcm2835_sdhost_init(Object *obj)
374
+
{
375
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BCM2835SDHostState *s = BCM2835_SDHOST(obj);
376
+
377
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qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
378
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TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
379
+
380
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memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s,
381
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TYPE_BCM2835_SDHOST, 0x1000);
382
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
383
+
sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
384
+
}
385
+
386
+
static void bcm2835_sdhost_reset(DeviceState *dev)
387
+
{
388
+
BCM2835SDHostState *s = BCM2835_SDHOST(dev);
389
+
390
+
s->cmd = 0;
391
+
s->cmdarg = 0;
392
+
s->edm = 0x0000c60f;
393
+
s->config = 0;
394
+
s->hbct = 0;
395
+
s->hblc = 0;
396
+
s->datacnt = 0;
397
+
s->fifo_pos = 0;
398
+
s->fifo_len = 0;
399
+
}
400
+
401
+
static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data)
402
+
{
403
+
DeviceClass *dc = DEVICE_CLASS(klass);
404
+
405
+
dc->reset = bcm2835_sdhost_reset;
406
+
dc->vmsd = &vmstate_bcm2835_sdhost;
407
+
}
408
+
409
+
static TypeInfo bcm2835_sdhost_info = {
410
+
.name = TYPE_BCM2835_SDHOST,
411
+
.parent = TYPE_SYS_BUS_DEVICE,
412
+
.instance_size = sizeof(BCM2835SDHostState),
413
+
.class_init = bcm2835_sdhost_class_init,
414
+
.instance_init = bcm2835_sdhost_init,
415
+
};
416
+
417
+
static const TypeInfo bcm2835_sdhost_bus_info = {
418
+
.name = TYPE_BCM2835_SDHOST_BUS,
419
+
.parent = TYPE_SD_BUS,
420
+
.instance_size = sizeof(SDBus),
421
+
};
422
+
423
+
static void bcm2835_sdhost_register_types(void)
424
+
{
425
+
type_register_static(&bcm2835_sdhost_info);
426
+
type_register_static(&bcm2835_sdhost_bus_info);
427
+
}
428
+
429
+
type_init(bcm2835_sdhost_register_types)
+48
include/hw/sd/bcm2835_sdhost.h
+48
include/hw/sd/bcm2835_sdhost.h
···
1
+
/*
2
+
* Raspberry Pi (BCM2835) SD Host Controller
3
+
*
4
+
* Copyright (c) 2017 Antfield SAS
5
+
*
6
+
* Authors:
7
+
* Clement Deschamps <clement.deschamps@antfield.fr>
8
+
* Luc Michel <luc.michel@antfield.fr>
9
+
*
10
+
* This work is licensed under the terms of the GNU GPL, version 2 or later.
11
+
* See the COPYING file in the top-level directory.
12
+
*/
13
+
14
+
#ifndef BCM2835_SDHOST_H
15
+
#define BCM2835_SDHOST_H
16
+
17
+
#include "hw/sysbus.h"
18
+
#include "hw/sd/sd.h"
19
+
20
+
#define TYPE_BCM2835_SDHOST "bcm2835-sdhost"
21
+
#define BCM2835_SDHOST(obj) \
22
+
OBJECT_CHECK(BCM2835SDHostState, (obj), TYPE_BCM2835_SDHOST)
23
+
24
+
#define BCM2835_SDHOST_FIFO_LEN 16
25
+
26
+
typedef struct {
27
+
SysBusDevice busdev;
28
+
SDBus sdbus;
29
+
MemoryRegion iomem;
30
+
31
+
uint32_t cmd;
32
+
uint32_t cmdarg;
33
+
uint32_t status;
34
+
uint32_t rsp[4];
35
+
uint32_t config;
36
+
uint32_t edm;
37
+
uint32_t vdd;
38
+
uint32_t hbct;
39
+
uint32_t hblc;
40
+
int32_t fifo_pos;
41
+
int32_t fifo_len;
42
+
uint32_t fifo[BCM2835_SDHOST_FIFO_LEN];
43
+
uint32_t datacnt;
44
+
45
+
qemu_irq irq;
46
+
} BCM2835SDHostState;
47
+
48
+
#endif