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pci-testdev: add optional memory bar

Add memory bar to pci-testdev. Size is configurable using the membar
property. Setting the size to zero (default) turns it off. Can be used
to check whether guests handle large pci bars correctly.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

authored by

Gerd Hoffmann and committed by
Michael S. Tsirkin 41746334 7115dcf4

+29 -5
+10 -5
docs/specs/pci-testdev.txt
··· 1 1 pci-test is a device used for testing low level IO 2 2 3 - device implements up to two BARs: BAR0 and BAR1. 4 - Each BAR can be memory or IO. Guests must detect 5 - BAR type and act accordingly. 3 + device implements up to three BARs: BAR0, BAR1 and BAR2. 4 + Each of BAR 0+1 can be memory or IO. Guests must detect 5 + BAR types and act accordingly. 6 6 7 - Each BAR size is up to 4K bytes. 8 - Each BAR starts with the following header: 7 + BAR 0+1 size is up to 4K bytes each. 8 + BAR 0+1 starts with the following header: 9 9 10 10 typedef struct PCITestDevHdr { 11 11 uint8_t test; <- write-only, starts a given test number ··· 24 24 device is expected to always implement tests 0 to N on each BAR, and to add new 25 25 tests with higher numbers. In this way a guest can scan test numbers until it 26 26 detects an access type that it does not support on this BAR, then stop. 27 + 28 + BAR2 is a 64bit memory bar, without backing storage. It is disabled 29 + by default and can be enabled using the membar=<size> property. This 30 + can be used to test whether guests handle pci bars of a specific 31 + (possibly quite large) size correctly.
+19
hw/misc/pci-testdev.c
··· 85 85 MemoryRegion portio; 86 86 IOTest *tests; 87 87 int current; 88 + 89 + uint64_t membar_size; 90 + MemoryRegion membar; 88 91 } PCITestDevState; 89 92 90 93 #define TYPE_PCI_TEST_DEV "pci-testdev" ··· 253 256 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); 254 257 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->portio); 255 258 259 + if (d->membar_size) { 260 + memory_region_init(&d->membar, OBJECT(d), "pci-testdev-membar", 261 + d->membar_size); 262 + pci_register_bar(pci_dev, 2, 263 + PCI_BASE_ADDRESS_SPACE_MEMORY | 264 + PCI_BASE_ADDRESS_MEM_PREFETCH | 265 + PCI_BASE_ADDRESS_MEM_TYPE_64, 266 + &d->membar); 267 + } 268 + 256 269 d->current = -1; 257 270 d->tests = g_malloc0(IOTEST_MAX * sizeof *d->tests); 258 271 for (i = 0; i < IOTEST_MAX; ++i) { ··· 305 318 pci_testdev_reset(d); 306 319 } 307 320 321 + static Property pci_testdev_properties[] = { 322 + DEFINE_PROP_SIZE("membar", PCITestDevState, membar_size, 0), 323 + DEFINE_PROP_END_OF_LIST(), 324 + }; 325 + 308 326 static void pci_testdev_class_init(ObjectClass *klass, void *data) 309 327 { 310 328 DeviceClass *dc = DEVICE_CLASS(klass); ··· 319 337 dc->desc = "PCI Test Device"; 320 338 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 321 339 dc->reset = qdev_pci_testdev_reset; 340 + dc->props = pci_testdev_properties; 322 341 } 323 342 324 343 static const TypeInfo pci_testdev_info = {