qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

hw/unicore32: restrict hw addr defines to source file

and drop unused #includes

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

authored by

Philippe Mathieu-Daudé and committed by
Michael Tokarev
40a3bbc9 2070aaeb

+10 -15
+10 -5
hw/unicore32/puv3.c
··· 11 11 12 12 #include "qemu/osdep.h" 13 13 #include "qapi/error.h" 14 - #include "qemu-common.h" 15 14 #include "cpu.h" 16 15 #include "ui/console.h" 17 - #include "elf.h" 18 - #include "exec/address-spaces.h" 19 - #include "hw/sysbus.h" 20 16 #include "hw/boards.h" 21 17 #include "hw/loader.h" 22 18 #include "hw/i386/pc.h" 23 - #include "qemu/error-report.h" 24 19 #include "sysemu/qtest.h" 25 20 26 21 #undef DEBUG_PUV3 ··· 28 23 29 24 #define KERNEL_LOAD_ADDR 0x03000000 30 25 #define KERNEL_MAX_SIZE 0x00800000 /* Just a guess */ 26 + 27 + /* PKUnity System bus (AHB): 0xc0000000 - 0xedffffff (640MB) */ 28 + #define PUV3_DMA_BASE (0xc0200000) /* AHB-4 */ 29 + 30 + /* PKUnity Peripheral bus (APB): 0xee000000 - 0xefffffff (128MB) */ 31 + #define PUV3_GPIO_BASE (0xee500000) /* APB-5 */ 32 + #define PUV3_INTC_BASE (0xee600000) /* APB-6 */ 33 + #define PUV3_OST_BASE (0xee800000) /* APB-8 */ 34 + #define PUV3_PM_BASE (0xeea00000) /* APB-10 */ 35 + #define PUV3_PS2_BASE (0xeeb00000) /* APB-11 */ 31 36 32 37 static void puv3_intc_cpu_handler(void *opaque, int irq, int level) 33 38 {
-10
include/hw/unicore32/puv3.h
··· 14 14 15 15 #define PUV3_REGS_OFFSET (0x1000) /* 4K is reasonable */ 16 16 17 - /* PKUnity System bus (AHB): 0xc0000000 - 0xedffffff (640MB) */ 18 - #define PUV3_DMA_BASE (0xc0200000) /* AHB-4 */ 19 - 20 - /* PKUnity Peripheral bus (APB): 0xee000000 - 0xefffffff (128MB) */ 21 - #define PUV3_GPIO_BASE (0xee500000) /* APB-5 */ 22 - #define PUV3_INTC_BASE (0xee600000) /* APB-6 */ 23 - #define PUV3_OST_BASE (0xee800000) /* APB-8 */ 24 - #define PUV3_PM_BASE (0xeea00000) /* APB-10 */ 25 - #define PUV3_PS2_BASE (0xeeb00000) /* APB-11 */ 26 - 27 17 /* Hardware interrupts */ 28 18 #define PUV3_IRQS_NR (32) 29 19