+2 -2

hw/alpha/typhoon.c

··· 826 826 PCIBus *b; 827 827 int i; 828 828 829 829 - dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE); 829 829 + dev = qdev_new(TYPE_TYPHOON_PCI_HOST_BRIDGE); 830 830 831 831 s = TYPHOON_PCI_HOST_BRIDGE(dev); 832 832 phb = PCI_HOST_BRIDGE(dev); ··· 889 889 &s->pchip.reg_mem, &s->pchip.reg_io, 890 890 0, 64, TYPE_PCI_BUS); 891 891 phb->bus = b; 892 892 - qdev_init_nofail(dev); 892 892 + qdev_realize_and_unref(dev, NULL, &error_fatal); 893 893 894 894 /* Host memory as seen from the PCI side, via the IOMMU. */ 895 895 memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu),

+4 -3

hw/arm/aspeed.c

··· 241 241 { 242 242 DeviceState *card; 243 243 244 244 - card = qdev_create(qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 245 245 - TYPE_SD_CARD); 244 244 + card = qdev_new(TYPE_SD_CARD); 246 245 if (dinfo) { 247 246 qdev_prop_set_drive(card, "drive", blk_by_legacy_dinfo(dinfo), 248 247 &error_fatal); 249 248 } 250 250 - object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); 249 249 + qdev_realize_and_unref(card, 250 250 + qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 251 251 + &error_fatal); 251 252 } 252 253 253 254 static void aspeed_machine_init(MachineState *machine)

+2 -2

hw/arm/cubieboard.c

··· 92 92 bus = qdev_get_child_bus(DEVICE(a10), "sd-bus"); 93 93 94 94 /* Plug in SD card */ 95 95 - carddev = qdev_create(bus, TYPE_SD_CARD); 95 95 + carddev = qdev_new(TYPE_SD_CARD); 96 96 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 97 97 - object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); 97 97 + qdev_realize_and_unref(carddev, bus, &error_fatal); 98 98 99 99 memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE, 100 100 machine->ram);

+21 -20

hw/arm/exynos4210.c

··· 173 173 DeviceState *dev; 174 174 int i; 175 175 176 176 - dev = qdev_create(NULL, "pl330"); 176 176 + dev = qdev_new("pl330"); 177 177 qdev_prop_set_uint8(dev, "num_events", nevents); 178 178 qdev_prop_set_uint8(dev, "num_chnls", 8); 179 179 qdev_prop_set_uint8(dev, "num_periph_req", nreq); ··· 184 184 qdev_prop_set_uint8(dev, "rd_q_dep", 8); 185 185 qdev_prop_set_uint8(dev, "data_width", width); 186 186 qdev_prop_set_uint16(dev, "data_buffer_dep", width); 187 187 - qdev_init_nofail(dev); 187 187 + qdev_realize_and_unref(dev, NULL, &error_fatal); 188 188 busdev = SYS_BUS_DEVICE(dev); 189 189 sysbus_mmio_map(busdev, 0, base); 190 190 ··· 232 232 233 233 /* IRQ Gate */ 234 234 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 235 235 - dev = qdev_create(NULL, "exynos4210.irq_gate"); 235 235 + dev = qdev_new("exynos4210.irq_gate"); 236 236 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 237 237 - qdev_init_nofail(dev); 237 237 + qdev_realize_and_unref(dev, NULL, &error_fatal); 238 238 /* Get IRQ Gate input in gate_irq */ 239 239 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 240 240 gate_irq[i][n] = qdev_get_gpio_in(dev, n); ··· 247 247 } 248 248 249 249 /* Private memory region and Internal GIC */ 250 250 - dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); 250 250 + dev = qdev_new(TYPE_A9MPCORE_PRIV); 251 251 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 252 252 - qdev_init_nofail(dev); 252 252 + qdev_realize_and_unref(dev, NULL, &error_fatal); 253 253 busdev = SYS_BUS_DEVICE(dev); 254 254 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 255 255 for (n = 0; n < EXYNOS4210_NCPUS; n++) { ··· 263 263 sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); 264 264 265 265 /* External GIC */ 266 266 - dev = qdev_create(NULL, "exynos4210.gic"); 266 266 + dev = qdev_new("exynos4210.gic"); 267 267 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 268 268 - qdev_init_nofail(dev); 268 268 + qdev_realize_and_unref(dev, NULL, &error_fatal); 269 269 busdev = SYS_BUS_DEVICE(dev); 270 270 /* Map CPU interface */ 271 271 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); ··· 279 279 } 280 280 281 281 /* Internal Interrupt Combiner */ 282 282 - dev = qdev_create(NULL, "exynos4210.combiner"); 283 283 - qdev_init_nofail(dev); 282 282 + dev = qdev_new("exynos4210.combiner"); 283 283 + qdev_realize_and_unref(dev, NULL, &error_fatal); 284 284 busdev = SYS_BUS_DEVICE(dev); 285 285 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 286 286 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); ··· 289 289 sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); 290 290 291 291 /* External Interrupt Combiner */ 292 292 - dev = qdev_create(NULL, "exynos4210.combiner"); 292 292 + dev = qdev_new("exynos4210.combiner"); 293 293 qdev_prop_set_uint32(dev, "external", 1); 294 294 - qdev_init_nofail(dev); 294 294 + qdev_realize_and_unref(dev, NULL, &error_fatal); 295 295 busdev = SYS_BUS_DEVICE(dev); 296 296 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 297 297 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); ··· 353 353 NULL); 354 354 355 355 /* Multi Core Timer */ 356 356 - dev = qdev_create(NULL, "exynos4210.mct"); 357 357 - qdev_init_nofail(dev); 356 356 + dev = qdev_new("exynos4210.mct"); 357 357 + qdev_realize_and_unref(dev, NULL, &error_fatal); 358 358 busdev = SYS_BUS_DEVICE(dev); 359 359 for (n = 0; n < 4; n++) { 360 360 /* Connect global timer interrupts to Combiner gpio_in */ ··· 379 379 i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)]; 380 380 } 381 381 382 382 - dev = qdev_create(NULL, "exynos4210.i2c"); 383 383 - qdev_init_nofail(dev); 382 382 + dev = qdev_new("exynos4210.i2c"); 383 383 + qdev_realize_and_unref(dev, NULL, &error_fatal); 384 384 busdev = SYS_BUS_DEVICE(dev); 385 385 sysbus_connect_irq(busdev, 0, i2c_irq); 386 386 sysbus_mmio_map(busdev, 0, addr); ··· 423 423 * public datasheet which is very similar (implementing 424 424 * MMC Specification Version 4.0 being the only difference noted) 425 425 */ 426 426 - dev = qdev_create(NULL, TYPE_S3C_SDHCI); 426 426 + dev = qdev_new(TYPE_S3C_SDHCI); 427 427 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 428 428 - qdev_init_nofail(dev); 428 428 + qdev_realize_and_unref(dev, NULL, &error_fatal); 429 429 430 430 busdev = SYS_BUS_DEVICE(dev); 431 431 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); ··· 433 433 434 434 di = drive_get(IF_SD, 0, n); 435 435 blk = di ? blk_by_legacy_dinfo(di) : NULL; 436 436 - carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 436 436 + carddev = qdev_new(TYPE_SD_CARD); 437 437 qdev_prop_set_drive(carddev, "drive", blk, &error_abort); 438 438 - qdev_init_nofail(carddev); 438 438 + qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 439 439 + &error_fatal); 439 440 } 440 441 441 442 /*** Display controller (FIMD) ***/

+2 -2

hw/arm/exynos4_boards.c

··· 81 81 /* This should be a 9215 but the 9118 is close enough */ 82 82 if (nd_table[0].used) { 83 83 qemu_check_nic_model(&nd_table[0], "lan9118"); 84 84 - dev = qdev_create(NULL, TYPE_LAN9118); 84 84 + dev = qdev_new(TYPE_LAN9118); 85 85 qdev_set_nic_properties(dev, &nd_table[0]); 86 86 qdev_prop_set_uint32(dev, "mode_16bit", 1); 87 87 - qdev_init_nofail(dev); 87 87 + qdev_realize_and_unref(dev, NULL, &error_fatal); 88 88 s = SYS_BUS_DEVICE(dev); 89 89 sysbus_mmio_map(s, 0, base); 90 90 sysbus_connect_irq(s, 0, irq);

+2 -3

hw/arm/imx25_pdk.c

··· 130 130 di = drive_get_next(IF_SD); 131 131 blk = di ? blk_by_legacy_dinfo(di) : NULL; 132 132 bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus"); 133 133 - carddev = qdev_create(bus, TYPE_SD_CARD); 133 133 + carddev = qdev_new(TYPE_SD_CARD); 134 134 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 135 135 - object_property_set_bool(OBJECT(carddev), true, 136 136 - "realized", &error_fatal); 135 135 + qdev_realize_and_unref(carddev, bus, &error_fatal); 137 136 } 138 137 139 138 /*

+2 -2

hw/arm/integratorcp.c

··· 620 620 0, ram_size); 621 621 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 622 622 623 623 - dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 623 623 + dev = qdev_new(TYPE_INTEGRATOR_CM); 624 624 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 625 625 - qdev_init_nofail(dev); 625 625 + qdev_realize_and_unref(dev, NULL, &error_fatal); 626 626 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 627 627 628 628 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,

+2 -3

hw/arm/mcimx6ul-evk.c

··· 54 54 di = drive_get_next(IF_SD); 55 55 blk = di ? blk_by_legacy_dinfo(di) : NULL; 56 56 bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); 57 57 - carddev = qdev_create(bus, TYPE_SD_CARD); 57 57 + carddev = qdev_new(TYPE_SD_CARD); 58 58 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 59 59 - object_property_set_bool(OBJECT(carddev), true, 60 60 - "realized", &error_fatal); 59 59 + qdev_realize_and_unref(carddev, bus, &error_fatal); 61 60 } 62 61 63 62 if (!qtest_enabled()) {

+2 -3

hw/arm/mcimx7d-sabre.c

··· 56 56 di = drive_get_next(IF_SD); 57 57 blk = di ? blk_by_legacy_dinfo(di) : NULL; 58 58 bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); 59 59 - carddev = qdev_create(bus, TYPE_SD_CARD); 59 59 + carddev = qdev_new(TYPE_SD_CARD); 60 60 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 61 61 - object_property_set_bool(OBJECT(carddev), true, 62 62 - "realized", &error_fatal); 61 61 + qdev_realize_and_unref(carddev, bus, &error_fatal); 63 62 } 64 63 65 64 if (!qtest_enabled()) {

+2 -2

hw/arm/mps2-tz.c

··· 246 246 * except that it doesn't support the checksum-offload feature. 247 247 */ 248 248 qemu_check_nic_model(nd, "lan9118"); 249 249 - mms->lan9118 = qdev_create(NULL, TYPE_LAN9118); 249 249 + mms->lan9118 = qdev_new(TYPE_LAN9118); 250 250 qdev_set_nic_properties(mms->lan9118, nd); 251 251 - qdev_init_nofail(mms->lan9118); 251 251 + qdev_realize_and_unref(mms->lan9118, NULL, &error_fatal); 252 252 253 253 s = SYS_BUS_DEVICE(mms->lan9118); 254 254 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));

+2 -2

hw/arm/msf2-som.c

··· 61 61 &error_fatal); 62 62 memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); 63 63 64 64 - dev = qdev_create(NULL, TYPE_MSF2_SOC); 64 64 + dev = qdev_new(TYPE_MSF2_SOC); 65 65 qdev_prop_set_string(dev, "part-name", "M2S010"); 66 66 qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type); 67 67 ··· 77 77 qdev_prop_set_uint32(dev, "apb0div", 2); 78 78 qdev_prop_set_uint32(dev, "apb1div", 2); 79 79 80 80 - object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); 80 80 + qdev_realize_and_unref(dev, NULL, &error_fatal); 81 81 82 82 soc = MSF2_SOC(dev); 83 83

+4 -4

hw/arm/musicpal.c

··· 1651 1651 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); 1652 1652 1653 1653 qemu_check_nic_model(&nd_table[0], "mv88w8618"); 1654 1654 - dev = qdev_create(NULL, TYPE_MV88W8618_ETH); 1654 1654 + dev = qdev_new(TYPE_MV88W8618_ETH); 1655 1655 qdev_set_nic_properties(dev, &nd_table[0]); 1656 1656 - qdev_init_nofail(dev); 1656 1656 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1657 1657 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); 1658 1658 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); 1659 1659 ··· 1688 1688 } 1689 1689 1690 1690 wm8750_dev = i2c_create_slave(i2c, TYPE_WM8750, MP_WM_ADDR); 1691 1691 - dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO); 1691 1691 + dev = qdev_new(TYPE_MV88W8618_AUDIO); 1692 1692 s = SYS_BUS_DEVICE(dev); 1693 1693 object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev), 1694 1694 "wm8750", NULL); 1695 1695 - qdev_init_nofail(dev); 1695 1695 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1696 1696 sysbus_mmio_map(s, 0, MP_AUDIO_BASE); 1697 1697 sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); 1698 1698

+2 -2

hw/arm/netduino2.c

··· 34 34 { 35 35 DeviceState *dev; 36 36 37 37 - dev = qdev_create(NULL, TYPE_STM32F205_SOC); 37 37 + dev = qdev_new(TYPE_STM32F205_SOC); 38 38 qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); 39 39 - object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); 39 39 + qdev_realize_and_unref(dev, NULL, &error_fatal); 40 40 41 41 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 42 42 FLASH_SIZE);

+2 -2

hw/arm/netduinoplus2.c

··· 34 34 { 35 35 DeviceState *dev; 36 36 37 37 - dev = qdev_create(NULL, TYPE_STM32F405_SOC); 37 37 + dev = qdev_new(TYPE_STM32F405_SOC); 38 38 qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); 39 39 - object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal); 39 39 + qdev_realize_and_unref(dev, NULL, &error_fatal); 40 40 41 41 armv7m_load_kernel(ARM_CPU(first_cpu), 42 42 machine->kernel_filename,

+4 -4

hw/arm/nseries.c

··· 174 174 char *otp_region; 175 175 DriveInfo *dinfo; 176 176 177 177 - s->nand = qdev_create(NULL, "onenand"); 177 177 + s->nand = qdev_new("onenand"); 178 178 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG); 179 179 /* Either 0x40 or 0x48 are OK for the device ID */ 180 180 qdev_prop_set_uint16(s->nand, "device_id", 0x48); ··· 185 185 qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo), 186 186 &error_fatal); 187 187 } 188 188 - qdev_init_nofail(s->nand); 188 188 + qdev_realize_and_unref(s->nand, NULL, &error_fatal); 189 189 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0, 190 190 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO)); 191 191 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS, ··· 802 802 static void n8x0_usb_setup(struct n800_s *s) 803 803 { 804 804 SysBusDevice *dev; 805 805 - s->usb = qdev_create(NULL, "tusb6010"); 805 805 + s->usb = qdev_new("tusb6010"); 806 806 dev = SYS_BUS_DEVICE(s->usb); 807 807 - qdev_init_nofail(s->usb); 807 807 + qdev_realize_and_unref(s->usb, NULL, &error_fatal); 808 808 sysbus_connect_irq(dev, 0, 809 809 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO)); 810 810 /* Using the NOR interface */

+8 -8

hw/arm/omap1.c

··· 3887 3887 3888 3888 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); 3889 3889 3890 3890 - s->ih[0] = qdev_create(NULL, "omap-intc"); 3890 3890 + s->ih[0] = qdev_new("omap-intc"); 3891 3891 qdev_prop_set_uint32(s->ih[0], "size", 0x100); 3892 3892 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck")); 3893 3893 - qdev_init_nofail(s->ih[0]); 3893 3893 + qdev_realize_and_unref(s->ih[0], NULL, &error_fatal); 3894 3894 busdev = SYS_BUS_DEVICE(s->ih[0]); 3895 3895 sysbus_connect_irq(busdev, 0, 3896 3896 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 3897 3897 sysbus_connect_irq(busdev, 1, 3898 3898 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); 3899 3899 sysbus_mmio_map(busdev, 0, 0xfffecb00); 3900 3900 - s->ih[1] = qdev_create(NULL, "omap-intc"); 3900 3900 + s->ih[1] = qdev_new("omap-intc"); 3901 3901 qdev_prop_set_uint32(s->ih[1], "size", 0x800); 3902 3902 omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck")); 3903 3903 - qdev_init_nofail(s->ih[1]); 3903 3903 + qdev_realize_and_unref(s->ih[1], NULL, &error_fatal); 3904 3904 busdev = SYS_BUS_DEVICE(s->ih[1]); 3905 3905 sysbus_connect_irq(busdev, 0, 3906 3906 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); ··· 4010 4010 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), 4011 4011 s->wakeup, omap_findclk(s, "clk32-kHz")); 4012 4012 4013 4013 - s->gpio = qdev_create(NULL, "omap-gpio"); 4013 4013 + s->gpio = qdev_new("omap-gpio"); 4014 4014 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 4015 4015 omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck")); 4016 4016 - qdev_init_nofail(s->gpio); 4016 4016 + qdev_realize_and_unref(s->gpio, NULL, &error_fatal); 4017 4017 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, 4018 4018 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); 4019 4019 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); ··· 4028 4028 s->pwt = omap_pwt_init(system_memory, 0xfffb6000, 4029 4029 omap_findclk(s, "armxor_ck")); 4030 4030 4031 4031 - s->i2c[0] = qdev_create(NULL, "omap_i2c"); 4031 4031 + s->i2c[0] = qdev_new("omap_i2c"); 4032 4032 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); 4033 4033 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck")); 4034 4034 - qdev_init_nofail(s->i2c[0]); 4034 4034 + qdev_realize_and_unref(s->i2c[0], NULL, &error_fatal); 4035 4035 busdev = SYS_BUS_DEVICE(s->i2c[0]); 4036 4036 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); 4037 4037 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);

+8 -8

hw/arm/omap2.c

··· 2306 2306 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54); 2307 2307 2308 2308 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ 2309 2309 - s->ih[0] = qdev_create(NULL, "omap2-intc"); 2309 2309 + s->ih[0] = qdev_new("omap2-intc"); 2310 2310 qdev_prop_set_uint8(s->ih[0], "revision", 0x21); 2311 2311 omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk")); 2312 2312 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk")); 2313 2313 - qdev_init_nofail(s->ih[0]); 2313 2313 + qdev_realize_and_unref(s->ih[0], NULL, &error_fatal); 2314 2314 busdev = SYS_BUS_DEVICE(s->ih[0]); 2315 2315 sysbus_connect_irq(busdev, 0, 2316 2316 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); ··· 2423 2423 omap_findclk(s, "clk32-kHz"), 2424 2424 omap_findclk(s, "core_l4_iclk")); 2425 2425 2426 2426 - s->i2c[0] = qdev_create(NULL, "omap_i2c"); 2426 2426 + s->i2c[0] = qdev_new("omap_i2c"); 2427 2427 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34); 2428 2428 omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk")); 2429 2429 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk")); 2430 2430 - qdev_init_nofail(s->i2c[0]); 2430 2430 + qdev_realize_and_unref(s->i2c[0], NULL, &error_fatal); 2431 2431 busdev = SYS_BUS_DEVICE(s->i2c[0]); 2432 2432 sysbus_connect_irq(busdev, 0, 2433 2433 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ)); ··· 2435 2435 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]); 2436 2436 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0)); 2437 2437 2438 2438 - s->i2c[1] = qdev_create(NULL, "omap_i2c"); 2438 2438 + s->i2c[1] = qdev_new("omap_i2c"); 2439 2439 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34); 2440 2440 omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk")); 2441 2441 omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk")); 2442 2442 - qdev_init_nofail(s->i2c[1]); 2442 2442 + qdev_realize_and_unref(s->i2c[1], NULL, &error_fatal); 2443 2443 busdev = SYS_BUS_DEVICE(s->i2c[1]); 2444 2444 sysbus_connect_irq(busdev, 0, 2445 2445 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ)); ··· 2447 2447 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]); 2448 2448 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0)); 2449 2449 2450 2450 - s->gpio = qdev_create(NULL, "omap2-gpio"); 2450 2450 + s->gpio = qdev_new("omap2-gpio"); 2451 2451 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 2452 2452 omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk")); 2453 2453 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_dbclk")); ··· 2458 2458 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4, 2459 2459 omap_findclk(s, "gpio5_dbclk")); 2460 2460 } 2461 2461 - qdev_init_nofail(s->gpio); 2461 2461 + qdev_realize_and_unref(s->gpio, NULL, &error_fatal); 2462 2462 busdev = SYS_BUS_DEVICE(s->gpio); 2463 2463 sysbus_connect_irq(busdev, 0, 2464 2464 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));

+2 -2

hw/arm/orangepi.c

··· 94 94 bus = qdev_get_child_bus(DEVICE(h3), "sd-bus"); 95 95 96 96 /* Plug in SD card */ 97 97 - carddev = qdev_create(bus, TYPE_SD_CARD); 97 97 + carddev = qdev_new(TYPE_SD_CARD); 98 98 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 99 99 - object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); 99 99 + qdev_realize_and_unref(carddev, bus, &error_fatal); 100 100 101 101 /* SDRAM */ 102 102 memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],

+4 -4

hw/arm/pxa2xx.c

··· 1510 1510 PXA2xxI2CState *s; 1511 1511 I2CBus *i2cbus; 1512 1512 1513 1513 - dev = qdev_create(NULL, TYPE_PXA2XX_I2C); 1513 1513 + dev = qdev_new(TYPE_PXA2XX_I2C); 1514 1514 qdev_prop_set_uint32(dev, "size", region_size + 1); 1515 1515 qdev_prop_set_uint32(dev, "offset", base & region_size); 1516 1516 - qdev_init_nofail(dev); 1516 1516 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1517 1517 1518 1518 i2c_dev = SYS_BUS_DEVICE(dev); 1519 1519 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); ··· 2073 2073 DeviceState *dev; 2074 2074 SysBusDevice *sbd; 2075 2075 2076 2076 - dev = qdev_create(NULL, TYPE_PXA2XX_FIR); 2076 2076 + dev = qdev_new(TYPE_PXA2XX_FIR); 2077 2077 qdev_prop_set_chr(dev, "chardev", chr); 2078 2078 - qdev_init_nofail(dev); 2078 2078 + qdev_realize_and_unref(dev, NULL, &error_fatal); 2079 2079 sbd = SYS_BUS_DEVICE(dev); 2080 2080 sysbus_mmio_map(sbd, 0, base); 2081 2081 sysbus_connect_irq(sbd, 0, irq);

+3 -2

hw/arm/pxa2xx_gpio.c

··· 14 14 #include "hw/sysbus.h" 15 15 #include "migration/vmstate.h" 16 16 #include "hw/arm/pxa.h" 17 17 + #include "qapi/error.h" 17 18 #include "qemu/log.h" 18 19 #include "qemu/module.h" 19 20 ··· 269 270 CPUState *cs = CPU(cpu); 270 271 DeviceState *dev; 271 272 272 272 - dev = qdev_create(NULL, TYPE_PXA2XX_GPIO); 273 273 + dev = qdev_new(TYPE_PXA2XX_GPIO); 273 274 qdev_prop_set_int32(dev, "lines", lines); 274 275 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index); 275 275 - qdev_init_nofail(dev); 276 276 + qdev_realize_and_unref(dev, NULL, &error_fatal); 276 277 277 278 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 278 279 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,

+3 -2

hw/arm/pxa2xx_pic.c

··· 9 9 */ 10 10 11 11 #include "qemu/osdep.h" 12 12 + #include "qapi/error.h" 12 13 #include "qemu/module.h" 13 14 #include "cpu.h" 14 15 #include "hw/arm/pxa.h" ··· 267 268 268 269 DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) 269 270 { 270 270 - DeviceState *dev = qdev_create(NULL, TYPE_PXA2XX_PIC); 271 271 + DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC); 271 272 PXA2xxPICState *s = PXA2XX_PIC(dev); 272 273 273 274 s->cpu = cpu; ··· 279 280 s->is_fiq[0] = 0; 280 281 s->is_fiq[1] = 0; 281 282 282 282 - qdev_init_nofail(dev); 283 283 + qdev_realize_and_unref(dev, NULL, &error_fatal); 283 284 284 285 qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); 285 286

+2 -2

hw/arm/raspi.c

··· 297 297 error_report("No SD bus found in SOC object"); 298 298 exit(1); 299 299 } 300 300 - carddev = qdev_create(bus, TYPE_SD_CARD); 300 300 + carddev = qdev_new(TYPE_SD_CARD); 301 301 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 302 302 - object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); 302 302 + qdev_realize_and_unref(carddev, bus, &error_fatal); 303 303 304 304 vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size", 305 305 &error_abort);

+10 -10

hw/arm/realview.c

··· 161 161 } 162 162 163 163 sys_id = is_pb ? 0x01780500 : 0xc1400400; 164 164 - sysctl = qdev_create(NULL, "realview_sysctl"); 164 164 + sysctl = qdev_new("realview_sysctl"); 165 165 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 166 166 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 167 167 - qdev_init_nofail(sysctl); 167 167 + qdev_realize_and_unref(sysctl, NULL, &error_fatal); 168 168 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 169 169 170 170 if (is_mpcore) { 171 171 - dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); 171 171 + dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); 172 172 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 173 173 - qdev_init_nofail(dev); 173 173 + qdev_realize_and_unref(dev, NULL, &error_fatal); 174 174 busdev = SYS_BUS_DEVICE(dev); 175 175 sysbus_mmio_map(busdev, 0, periphbase); 176 176 for (n = 0; n < smp_cpus; n++) { ··· 188 188 pic[n] = qdev_get_gpio_in(dev, n); 189 189 } 190 190 191 191 - pl041 = qdev_create(NULL, "pl041"); 191 191 + pl041 = qdev_new("pl041"); 192 192 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 193 193 - qdev_init_nofail(pl041); 193 193 + qdev_realize_and_unref(pl041, NULL, &error_fatal); 194 194 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 195 195 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 196 196 ··· 203 203 pl011_create(0x1000c000, pic[15], serial_hd(3)); 204 204 205 205 /* DMA controller is optional, apparently. */ 206 206 - dev = qdev_create(NULL, "pl081"); 206 206 + dev = qdev_new("pl081"); 207 207 object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", 208 208 &error_fatal); 209 209 - qdev_init_nofail(dev); 209 209 + qdev_realize_and_unref(dev, NULL, &error_fatal); 210 210 busdev = SYS_BUS_DEVICE(dev); 211 211 sysbus_mmio_map(busdev, 0, 0x10030000); 212 212 sysbus_connect_irq(busdev, 0, pic[24]); ··· 239 239 sysbus_create_simple("pl031", 0x10017000, pic[10]); 240 240 241 241 if (!is_pb) { 242 242 - dev = qdev_create(NULL, "realview_pci"); 242 242 + dev = qdev_new("realview_pci"); 243 243 busdev = SYS_BUS_DEVICE(dev); 244 244 - qdev_init_nofail(dev); 244 244 + qdev_realize_and_unref(dev, NULL, &error_fatal); 245 245 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 246 246 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 247 247 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */

+10 -10

hw/arm/sbsa-ref.c

··· 339 339 340 340 gictype = gicv3_class_name(); 341 341 342 342 - sms->gic = qdev_create(NULL, gictype); 342 342 + sms->gic = qdev_new(gictype); 343 343 qdev_prop_set_uint32(sms->gic, "revision", 3); 344 344 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); 345 345 /* ··· 356 356 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 357 357 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 358 358 359 359 - qdev_init_nofail(sms->gic); 359 359 + qdev_realize_and_unref(sms->gic, NULL, &error_fatal); 360 360 gicbusdev = SYS_BUS_DEVICE(sms->gic); 361 361 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 362 362 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); ··· 409 409 { 410 410 hwaddr base = sbsa_ref_memmap[uart].base; 411 411 int irq = sbsa_ref_irqmap[uart]; 412 412 - DeviceState *dev = qdev_create(NULL, TYPE_PL011); 412 412 + DeviceState *dev = qdev_new(TYPE_PL011); 413 413 SysBusDevice *s = SYS_BUS_DEVICE(dev); 414 414 415 415 qdev_prop_set_chr(dev, "chardev", chr); 416 416 - qdev_init_nofail(dev); 416 416 + qdev_realize_and_unref(dev, NULL, &error_fatal); 417 417 memory_region_add_subregion(mem, base, 418 418 sysbus_mmio_get_region(s, 0)); 419 419 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); ··· 464 464 AHCIState *ahci; 465 465 int i; 466 466 467 467 - dev = qdev_create(NULL, "sysbus-ahci"); 467 467 + dev = qdev_new("sysbus-ahci"); 468 468 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 469 469 - qdev_init_nofail(dev); 469 469 + qdev_realize_and_unref(dev, NULL, &error_fatal); 470 470 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 471 471 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 472 472 ··· 497 497 DeviceState *dev; 498 498 int i; 499 499 500 500 - dev = qdev_create(NULL, "arm-smmuv3"); 500 500 + dev = qdev_new("arm-smmuv3"); 501 501 502 502 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 503 503 &error_abort); 504 504 - qdev_init_nofail(dev); 504 504 + qdev_realize_and_unref(dev, NULL, &error_fatal); 505 505 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 506 506 for (i = 0; i < NUM_SMMU_IRQS; i++) { 507 507 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, ··· 525 525 PCIHostState *pci; 526 526 int i; 527 527 528 528 - dev = qdev_create(NULL, TYPE_GPEX_HOST); 529 529 - qdev_init_nofail(dev); 528 528 + dev = qdev_new(TYPE_GPEX_HOST); 529 529 + qdev_realize_and_unref(dev, NULL, &error_fatal); 530 530 531 531 /* Map ECAM space */ 532 532 ecam_alias = g_new0(MemoryRegion, 1);

+2 -2

hw/arm/spitz.c

··· 155 155 { 156 156 DeviceState *dev; 157 157 158 158 - dev = qdev_create(NULL, TYPE_SL_NAND); 158 158 + dev = qdev_new(TYPE_SL_NAND); 159 159 160 160 qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG); 161 161 if (size == FLASH_128M) ··· 163 163 else if (size == FLASH_1024M) 164 164 qdev_prop_set_uint8(dev, "chip_id", 0xf1); 165 165 166 166 - qdev_init_nofail(dev); 166 166 + qdev_realize_and_unref(dev, NULL, &error_fatal); 167 167 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE); 168 168 } 169 169

+6 -6

hw/arm/stellaris.c

··· 1308 1308 &error_fatal); 1309 1309 memory_region_add_subregion(system_memory, 0x20000000, sram); 1310 1310 1311 1311 - nvic = qdev_create(NULL, TYPE_ARMV7M); 1311 1311 + nvic = qdev_new(TYPE_ARMV7M); 1312 1312 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); 1313 1313 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); 1314 1314 qdev_prop_set_bit(nvic, "enable-bitband", true); 1315 1315 object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), 1316 1316 "memory", &error_abort); 1317 1317 /* This will exit with an error if the user passed us a bad cpu_type */ 1318 1318 - qdev_init_nofail(nvic); 1318 1318 + qdev_realize_and_unref(nvic, NULL, &error_fatal); 1319 1319 1320 1320 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1321 1321 qemu_allocate_irq(&do_sys_reset, NULL, 0)); ··· 1347 1347 1348 1348 1349 1349 if (board->dc1 & (1 << 3)) { /* watchdog present */ 1350 1350 - dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG); 1350 1350 + dev = qdev_new(TYPE_LUMINARY_WATCHDOG); 1351 1351 1352 1352 /* system_clock_scale is valid now */ 1353 1353 uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; 1354 1354 qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); 1355 1355 1356 1356 - qdev_init_nofail(dev); 1356 1356 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1357 1357 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1358 1358 0, 1359 1359 0x40000000u); ··· 1425 1425 1426 1426 qemu_check_nic_model(&nd_table[0], "stellaris"); 1427 1427 1428 1428 - enet = qdev_create(NULL, "stellaris_enet"); 1428 1428 + enet = qdev_new("stellaris_enet"); 1429 1429 qdev_set_nic_properties(enet, &nd_table[0]); 1430 1430 - qdev_init_nofail(enet); 1430 1430 + qdev_realize_and_unref(enet, NULL, &error_fatal); 1431 1431 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1432 1432 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1433 1433 }

+5 -4

hw/arm/strongarm.c

··· 42 42 #include "chardev/char-serial.h" 43 43 #include "sysemu/sysemu.h" 44 44 #include "hw/ssi/ssi.h" 45 45 + #include "qapi/error.h" 45 46 #include "qemu/cutils.h" 46 47 #include "qemu/log.h" 47 48 ··· 644 645 DeviceState *dev; 645 646 int i; 646 647 647 647 - dev = qdev_create(NULL, TYPE_STRONGARM_GPIO); 648 648 - qdev_init_nofail(dev); 648 648 + dev = qdev_new(TYPE_STRONGARM_GPIO); 649 649 + qdev_realize_and_unref(dev, NULL, &error_fatal); 649 650 650 651 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 651 652 for (i = 0; i < 12; i++) ··· 1626 1627 s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL); 1627 1628 1628 1629 for (i = 0; sa_serial[i].io_base; i++) { 1629 1629 - DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART); 1630 1630 + DeviceState *dev = qdev_new(TYPE_STRONGARM_UART); 1630 1631 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1631 1631 - qdev_init_nofail(dev); 1632 1632 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1632 1633 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1633 1634 sa_serial[i].io_base); 1634 1635 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,

+8 -8

hw/arm/versatilepb.c

··· 223 223 /* SDRAM at address zero. */ 224 224 memory_region_add_subregion(sysmem, 0, machine->ram); 225 225 226 226 - sysctl = qdev_create(NULL, "realview_sysctl"); 226 226 + sysctl = qdev_new("realview_sysctl"); 227 227 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); 228 228 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); 229 229 - qdev_init_nofail(sysctl); 229 229 + qdev_realize_and_unref(sysctl, NULL, &error_fatal); 230 230 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 231 231 232 232 dev = sysbus_create_varargs("pl190", 0x10140000, ··· 245 245 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); 246 246 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); 247 247 248 248 - dev = qdev_create(NULL, "versatile_pci"); 248 248 + dev = qdev_new("versatile_pci"); 249 249 busdev = SYS_BUS_DEVICE(dev); 250 250 - qdev_init_nofail(dev); 250 250 + qdev_realize_and_unref(dev, NULL, &error_fatal); 251 251 sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ 252 252 sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ 253 253 sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ ··· 286 286 pl011_create(0x101f3000, pic[14], serial_hd(2)); 287 287 pl011_create(0x10009000, sic[6], serial_hd(3)); 288 288 289 289 - dev = qdev_create(NULL, "pl080"); 289 289 + dev = qdev_new("pl080"); 290 290 object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", 291 291 &error_fatal); 292 292 - qdev_init_nofail(dev); 292 292 + qdev_realize_and_unref(dev, NULL, &error_fatal); 293 293 busdev = SYS_BUS_DEVICE(dev); 294 294 sysbus_mmio_map(busdev, 0, 0x10130000); 295 295 sysbus_connect_irq(busdev, 0, pic[17]); ··· 319 319 i2c_create_slave(i2c, "ds1338", 0x68); 320 320 321 321 /* Add PL041 AACI Interface to the LM4549 codec */ 322 322 - pl041 = qdev_create(NULL, "pl041"); 322 322 + pl041 = qdev_new("pl041"); 323 323 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 324 324 - qdev_init_nofail(pl041); 324 324 + qdev_realize_and_unref(pl041, NULL, &error_fatal); 325 325 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 326 326 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); 327 327

+8 -8

hw/arm/vexpress.c

··· 236 236 * this must happen after the CPUs are created because a15mpcore_priv 237 237 * wires itself up to the CPU's generic_timer gpio out lines. 238 238 */ 239 239 - dev = qdev_create(NULL, privdev); 239 239 + dev = qdev_new(privdev); 240 240 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 241 241 - qdev_init_nofail(dev); 241 241 + qdev_realize_and_unref(dev, NULL, &error_fatal); 242 242 busdev = SYS_BUS_DEVICE(dev); 243 243 sysbus_mmio_map(busdev, 0, periphbase); 244 244 ··· 514 514 static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, 515 515 DriveInfo *di) 516 516 { 517 517 - DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 517 517 + DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 518 518 519 519 if (di) { 520 520 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di), ··· 532 532 qdev_prop_set_uint16(dev, "id2", 0x00); 533 533 qdev_prop_set_uint16(dev, "id3", 0x00); 534 534 qdev_prop_set_string(dev, "name", name); 535 535 - qdev_init_nofail(dev); 535 535 + qdev_realize_and_unref(dev, NULL, &error_fatal); 536 536 537 537 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 538 538 return PFLASH_CFI01(dev); ··· 593 593 594 594 sys_id = 0x1190f500; 595 595 596 596 - sysctl = qdev_create(NULL, "realview_sysctl"); 596 596 + sysctl = qdev_new("realview_sysctl"); 597 597 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 598 598 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id); 599 599 qdev_prop_set_uint32(sysctl, "len-db-voltage", ··· 610 610 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 611 611 g_free(propname); 612 612 } 613 613 - qdev_init_nofail(sysctl); 613 613 + qdev_realize_and_unref(sysctl, NULL, &error_fatal); 614 614 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 615 615 616 616 /* VE_SP810: not modelled */ 617 617 /* VE_SERIALPCI: not modelled */ 618 618 619 619 - pl041 = qdev_create(NULL, "pl041"); 619 619 + pl041 = qdev_new("pl041"); 620 620 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 621 621 - qdev_init_nofail(pl041); 621 621 + qdev_realize_and_unref(pl041, NULL, &error_fatal); 622 622 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 623 623 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 624 624

+16 -16

hw/arm/virt.c

··· 572 572 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 573 573 } 574 574 575 575 - dev = qdev_create(NULL, TYPE_ACPI_GED); 575 575 + dev = qdev_new(TYPE_ACPI_GED); 576 576 qdev_prop_set_uint32(dev, "ged-event", event); 577 577 578 578 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 579 579 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 580 580 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 581 581 582 582 - qdev_init_nofail(dev); 582 582 + qdev_realize_and_unref(dev, NULL, &error_fatal); 583 583 584 584 return dev; 585 585 } ··· 594 594 return; 595 595 } 596 596 597 597 - dev = qdev_create(NULL, itsclass); 597 597 + dev = qdev_new(itsclass); 598 598 599 599 object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", 600 600 &error_abort); 601 601 - qdev_init_nofail(dev); 601 601 + qdev_realize_and_unref(dev, NULL, &error_fatal); 602 602 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 603 603 604 604 fdt_add_its_gic_node(vms); ··· 610 610 int irq = vms->irqmap[VIRT_GIC_V2M]; 611 611 DeviceState *dev; 612 612 613 613 - dev = qdev_create(NULL, "arm-gicv2m"); 613 613 + dev = qdev_new("arm-gicv2m"); 614 614 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 615 615 qdev_prop_set_uint32(dev, "base-spi", irq); 616 616 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 617 617 - qdev_init_nofail(dev); 617 617 + qdev_realize_and_unref(dev, NULL, &error_fatal); 618 618 619 619 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 620 620 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, ··· 636 636 637 637 gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); 638 638 639 639 - vms->gic = qdev_create(NULL, gictype); 639 639 + vms->gic = qdev_new(gictype); 640 640 qdev_prop_set_uint32(vms->gic, "revision", type); 641 641 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 642 642 /* Note that the num-irq property counts both internal and external ··· 671 671 vms->virt); 672 672 } 673 673 } 674 674 - qdev_init_nofail(vms->gic); 674 674 + qdev_realize_and_unref(vms->gic, NULL, &error_fatal); 675 675 gicbusdev = SYS_BUS_DEVICE(vms->gic); 676 676 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 677 677 if (type == 3) { ··· 754 754 int irq = vms->irqmap[uart]; 755 755 const char compat[] = "arm,pl011\0arm,primecell"; 756 756 const char clocknames[] = "uartclk\0apb_pclk"; 757 757 - DeviceState *dev = qdev_create(NULL, TYPE_PL011); 757 757 + DeviceState *dev = qdev_new(TYPE_PL011); 758 758 SysBusDevice *s = SYS_BUS_DEVICE(dev); 759 759 760 760 qdev_prop_set_chr(dev, "chardev", chr); 761 761 - qdev_init_nofail(dev); 761 761 + qdev_realize_and_unref(dev, NULL, &error_fatal); 762 762 memory_region_add_subregion(mem, base, 763 763 sysbus_mmio_get_region(s, 0)); 764 764 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); ··· 1173 1173 return; 1174 1174 } 1175 1175 1176 1176 - dev = qdev_create(NULL, "arm-smmuv3"); 1176 1176 + dev = qdev_new("arm-smmuv3"); 1177 1177 1178 1178 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1179 1179 &error_abort); 1180 1180 - qdev_init_nofail(dev); 1180 1180 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1181 1181 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1182 1182 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1183 1183 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, ··· 1253 1253 int i, ecam_id; 1254 1254 PCIHostState *pci; 1255 1255 1256 1256 - dev = qdev_create(NULL, TYPE_GPEX_HOST); 1257 1257 - qdev_init_nofail(dev); 1256 1256 + dev = qdev_new(TYPE_GPEX_HOST); 1257 1257 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1258 1258 1259 1259 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1260 1260 base_ecam = vms->memmap[ecam_id].base; ··· 1372 1372 int i; 1373 1373 MemoryRegion *sysmem = get_system_memory(); 1374 1374 1375 1375 - dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1375 1375 + dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1376 1376 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1377 1377 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1378 1378 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1379 1379 - qdev_init_nofail(dev); 1379 1379 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1380 1380 vms->platform_bus_dev = dev; 1381 1381 1382 1382 s = SYS_BUS_DEVICE(dev);

+19 -19

hw/arm/xilinx_zynq.c

··· 114 114 DeviceState *dev; 115 115 SysBusDevice *s; 116 116 117 117 - dev = qdev_create(NULL, TYPE_CADENCE_GEM); 117 117 + dev = qdev_new(TYPE_CADENCE_GEM); 118 118 if (nd->used) { 119 119 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 120 120 qdev_set_nic_properties(dev, nd); 121 121 } 122 122 - qdev_init_nofail(dev); 122 122 + qdev_realize_and_unref(dev, NULL, &error_fatal); 123 123 s = SYS_BUS_DEVICE(dev); 124 124 sysbus_mmio_map(s, 0, base); 125 125 sysbus_connect_irq(s, 0, irq); ··· 136 136 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; 137 137 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; 138 138 139 139 - dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 139 139 + dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); 140 140 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 141 141 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 142 142 qdev_prop_set_uint8(dev, "num-busses", num_busses); 143 143 - qdev_init_nofail(dev); 143 143 + qdev_realize_and_unref(dev, NULL, &error_fatal); 144 144 busdev = SYS_BUS_DEVICE(dev); 145 145 sysbus_mmio_map(busdev, 0, base_addr); 146 146 if (is_qspi) { ··· 222 222 0); 223 223 224 224 /* Create slcr, keep a pointer to connect clocks */ 225 225 - slcr = qdev_create(NULL, "xilinx,zynq_slcr"); 226 226 - qdev_init_nofail(slcr); 225 225 + slcr = qdev_new("xilinx,zynq_slcr"); 226 226 + qdev_realize_and_unref(slcr, NULL, &error_fatal); 227 227 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); 228 228 229 229 /* Create the main clock source, and feed slcr with it */ ··· 234 234 clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); 235 235 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); 236 236 237 237 - dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); 237 237 + dev = qdev_new(TYPE_A9MPCORE_PRIV); 238 238 qdev_prop_set_uint32(dev, "num-cpu", 1); 239 239 - qdev_init_nofail(dev); 239 239 + qdev_realize_and_unref(dev, NULL, &error_fatal); 240 240 busdev = SYS_BUS_DEVICE(dev); 241 241 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 242 242 sysbus_connect_irq(busdev, 0, ··· 280 280 * - SDIO Specification Version 2.0 281 281 * - MMC Specification Version 3.31 282 282 */ 283 283 - dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); 283 283 + dev = qdev_new(TYPE_SYSBUS_SDHCI); 284 284 qdev_prop_set_uint8(dev, "sd-spec-version", 2); 285 285 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); 286 286 - qdev_init_nofail(dev); 286 286 + qdev_realize_and_unref(dev, NULL, &error_fatal); 287 287 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); 288 288 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); 289 289 290 290 di = drive_get_next(IF_SD); 291 291 blk = di ? blk_by_legacy_dinfo(di) : NULL; 292 292 - carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 292 292 + carddev = qdev_new(TYPE_SD_CARD); 293 293 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 294 294 - object_property_set_bool(OBJECT(carddev), true, "realized", 295 295 - &error_fatal); 294 294 + qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), 295 295 + &error_fatal); 296 296 } 297 297 298 298 - dev = qdev_create(NULL, TYPE_ZYNQ_XADC); 299 299 - qdev_init_nofail(dev); 298 298 + dev = qdev_new(TYPE_ZYNQ_XADC); 299 299 + qdev_realize_and_unref(dev, NULL, &error_fatal); 300 300 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); 301 301 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); 302 302 303 303 - dev = qdev_create(NULL, "pl330"); 303 303 + dev = qdev_new("pl330"); 304 304 qdev_prop_set_uint8(dev, "num_chnls", 8); 305 305 qdev_prop_set_uint8(dev, "num_periph_req", 4); 306 306 qdev_prop_set_uint8(dev, "num_events", 16); ··· 312 312 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 313 313 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 314 314 315 315 - qdev_init_nofail(dev); 315 315 + qdev_realize_and_unref(dev, NULL, &error_fatal); 316 316 busdev = SYS_BUS_DEVICE(dev); 317 317 sysbus_mmio_map(busdev, 0, 0xF8003000); 318 318 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ ··· 320 320 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); 321 321 } 322 322 323 323 - dev = qdev_create(NULL, "xlnx.ps7-dev-cfg"); 324 324 - qdev_init_nofail(dev); 323 323 + dev = qdev_new("xlnx.ps7-dev-cfg"); 324 324 + qdev_realize_and_unref(dev, NULL, &error_fatal); 325 325 busdev = SYS_BUS_DEVICE(dev); 326 326 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); 327 327 sysbus_mmio_map(busdev, 0, 0xF8007000);

+5 -4

hw/arm/xlnx-versal-virt.c

··· 432 432 qemu_irq pic_irq; 433 433 434 434 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); 435 435 - dev = qdev_create(NULL, "virtio-mmio"); 435 435 + dev = qdev_new("virtio-mmio"); 436 436 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev)); 437 437 - qdev_init_nofail(dev); 437 437 + qdev_realize_and_unref(dev, NULL, &error_fatal); 438 438 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); 439 439 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 440 440 memory_region_add_subregion(&s->soc.mr_ps, base, mr); ··· 463 463 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 464 464 DeviceState *card; 465 465 466 466 - card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD); 466 466 + card = qdev_new(TYPE_SD_CARD); 467 467 object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card)); 468 468 qdev_prop_set_drive(card, "drive", blk, &error_fatal); 469 469 - object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); 469 469 + qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"), 470 470 + &error_fatal); 470 471 } 471 472 472 473 static void versal_virt_init(MachineState *machine)

+2 -2

hw/arm/xlnx-versal.c

··· 304 304 MemoryRegion *mr, 305 305 hwaddr base, hwaddr size) 306 306 { 307 307 - DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE); 307 307 + DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 308 308 MemoryRegion *mr_dev; 309 309 310 310 qdev_prop_set_string(dev, "name", name); 311 311 qdev_prop_set_uint64(dev, "size", size); 312 312 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 313 313 - qdev_init_nofail(dev); 313 313 + qdev_realize_and_unref(dev, NULL, &error_fatal); 314 314 315 315 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 316 316 memory_region_add_subregion(mr, base, mr_dev);

+2 -3

hw/arm/xlnx-zcu102.c

··· 143 143 error_report("No SD bus found for SD card %d", i); 144 144 exit(1); 145 145 } 146 146 - carddev = qdev_create(bus, TYPE_SD_CARD); 146 146 + carddev = qdev_new(TYPE_SD_CARD); 147 147 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); 148 148 - object_property_set_bool(OBJECT(carddev), true, "realized", 149 149 - &error_fatal); 148 148 + qdev_realize_and_unref(carddev, bus, &error_fatal); 150 149 } 151 150 152 151 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {

+2 -2

hw/audio/intel-hda.c

··· 1309 1309 1310 1310 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda")); 1311 1311 hdabus = QLIST_FIRST(&controller->child_bus); 1312 1312 - codec = qdev_create(hdabus, "hda-duplex"); 1313 1313 - qdev_init_nofail(codec); 1312 1312 + codec = qdev_new("hda-duplex"); 1313 1313 + qdev_realize_and_unref(codec, hdabus, &error_fatal); 1314 1314 return 0; 1315 1315 } 1316 1316

+6 -6

hw/block/fdc.c

··· 2516 2516 continue; 2517 2517 } 2518 2518 2519 2519 - dev = qdev_create(&fdctrl->bus.bus, "floppy"); 2519 2519 + dev = qdev_new("floppy"); 2520 2520 qdev_prop_set_uint32(dev, "unit", i); 2521 2521 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type); 2522 2522 ··· 2531 2531 return; 2532 2532 } 2533 2533 2534 2534 - object_property_set_bool(OBJECT(dev), true, "realized", &local_err); 2534 2534 + qdev_realize_and_unref(dev, &fdctrl->bus.bus, &local_err); 2535 2535 if (local_err) { 2536 2536 error_propagate(errp, local_err); 2537 2537 return; ··· 2571 2571 SysBusDevice *sbd; 2572 2572 FDCtrlSysBus *sys; 2573 2573 2574 2574 - dev = qdev_create(NULL, "sysbus-fdc"); 2574 2574 + dev = qdev_new("sysbus-fdc"); 2575 2575 sys = SYSBUS_FDC(dev); 2576 2576 fdctrl = &sys->state; 2577 2577 fdctrl->dma_chann = dma_chann; /* FIXME */ ··· 2583 2583 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2584 2584 &error_fatal); 2585 2585 } 2586 2586 - qdev_init_nofail(dev); 2586 2586 + qdev_realize_and_unref(dev, NULL, &error_fatal); 2587 2587 sbd = SYS_BUS_DEVICE(dev); 2588 2588 sysbus_connect_irq(sbd, 0, irq); 2589 2589 sysbus_mmio_map(sbd, 0, mmio_base); ··· 2595 2595 DeviceState *dev; 2596 2596 FDCtrlSysBus *sys; 2597 2597 2598 2598 - dev = qdev_create(NULL, "SUNW,fdtwo"); 2598 2598 + dev = qdev_new("SUNW,fdtwo"); 2599 2599 if (fds[0]) { 2600 2600 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]), 2601 2601 &error_fatal); 2602 2602 } 2603 2603 - qdev_init_nofail(dev); 2603 2603 + qdev_realize_and_unref(dev, NULL, &error_fatal); 2604 2604 sys = SYSBUS_FDC(dev); 2605 2605 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); 2606 2606 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);

+2 -2

hw/block/pflash_cfi01.c

··· 959 959 uint16_t id2, uint16_t id3, 960 960 int be) 961 961 { 962 962 - DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 962 962 + DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 963 963 964 964 if (blk) { 965 965 qdev_prop_set_drive(dev, "drive", blk, &error_abort); ··· 974 974 qdev_prop_set_uint16(dev, "id2", id2); 975 975 qdev_prop_set_uint16(dev, "id3", id3); 976 976 qdev_prop_set_string(dev, "name", name); 977 977 - qdev_init_nofail(dev); 977 977 + qdev_realize_and_unref(dev, NULL, &error_fatal); 978 978 979 979 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 980 980 return PFLASH_CFI01(dev);

+2 -2

hw/block/pflash_cfi02.c

··· 998 998 uint16_t unlock_addr1, 999 999 int be) 1000 1000 { 1001 1001 - DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02); 1001 1001 + DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02); 1002 1002 1003 1003 if (blk) { 1004 1004 qdev_prop_set_drive(dev, "drive", blk, &error_abort); ··· 1016 1016 qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); 1017 1017 qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); 1018 1018 qdev_prop_set_string(dev, "name", name); 1019 1019 - qdev_init_nofail(dev); 1019 1019 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1020 1020 1021 1021 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1022 1022 return PFLASH_CFI02(dev);

+3 -2

hw/char/exynos4210_uart.c

··· 22 22 #include "qemu/osdep.h" 23 23 #include "hw/sysbus.h" 24 24 #include "migration/vmstate.h" 25 25 + #include "qapi/error.h" 25 26 #include "qemu/error-report.h" 26 27 #include "qemu/module.h" 27 28 #include "qemu/timer.h" ··· 652 653 DeviceState *dev; 653 654 SysBusDevice *bus; 654 655 655 655 - dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); 656 656 + dev = qdev_new(TYPE_EXYNOS4210_UART); 656 657 657 658 qdev_prop_set_chr(dev, "chardev", chr); 658 659 qdev_prop_set_uint32(dev, "channel", channel); ··· 660 661 qdev_prop_set_uint32(dev, "tx-size", fifo_size); 661 662 662 663 bus = SYS_BUS_DEVICE(dev); 663 663 - qdev_init_nofail(dev); 664 664 + qdev_realize_and_unref(dev, NULL, &error_fatal); 664 665 if (addr != (hwaddr)-1) { 665 666 sysbus_mmio_map(bus, 0, addr); 666 667 }

+3 -2

hw/char/mcf_uart.c

··· 10 10 #include "hw/irq.h" 11 11 #include "hw/sysbus.h" 12 12 #include "qemu/module.h" 13 13 + #include "qapi/error.h" 13 14 #include "hw/m68k/mcf.h" 14 15 #include "hw/qdev-properties.h" 15 16 #include "chardev/char-fe.h" ··· 343 344 { 344 345 DeviceState *dev; 345 346 346 346 - dev = qdev_create(NULL, TYPE_MCF_UART); 347 347 + dev = qdev_new(TYPE_MCF_UART); 347 348 if (chrdrv) { 348 349 qdev_prop_set_chr(dev, "chardev", chrdrv); 349 350 } 350 350 - qdev_init_nofail(dev); 351 351 + qdev_realize_and_unref(dev, NULL, &error_fatal); 351 352 352 353 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 353 354

+2 -2

hw/char/spapr_vty.c

··· 158 158 { 159 159 DeviceState *dev; 160 160 161 161 - dev = qdev_create(&bus->bus, "spapr-vty"); 161 161 + dev = qdev_new("spapr-vty"); 162 162 qdev_prop_set_chr(dev, "chardev", chardev); 163 163 - qdev_init_nofail(dev); 163 163 + qdev_realize_and_unref(dev, &bus->bus, &error_fatal); 164 164 } 165 165 166 166 static Property spapr_vty_properties[] = {

+2 -2

hw/core/sysbus.c

··· 230 230 qemu_irq irq; 231 231 int n; 232 232 233 233 - dev = qdev_create(NULL, name); 233 233 + dev = qdev_new(name); 234 234 s = SYS_BUS_DEVICE(dev); 235 235 - qdev_init_nofail(dev); 235 235 + qdev_realize_and_unref(dev, NULL, &error_fatal); 236 236 if (addr != (hwaddr)-1) { 237 237 sysbus_mmio_map(s, 0, addr); 238 238 }

+2 -2

hw/cris/axis_dev88.c

··· 289 289 &gpio_state.iomem); 290 290 291 291 292 292 - dev = qdev_create(NULL, "etraxfs,pic"); 293 293 - qdev_init_nofail(dev); 292 292 + dev = qdev_new("etraxfs,pic"); 293 293 + qdev_realize_and_unref(dev, NULL, &error_fatal); 294 294 s = SYS_BUS_DEVICE(dev); 295 295 sysbus_mmio_map(s, 0, 0x3001c000); 296 296 sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));

+2 -2

hw/display/milkymist-tmu2.c

··· 543 543 XFree(configs); 544 544 XCloseDisplay(d); 545 545 546 546 - dev = qdev_create(NULL, TYPE_MILKYMIST_TMU2); 547 547 - qdev_init_nofail(dev); 546 546 + dev = qdev_new(TYPE_MILKYMIST_TMU2); 547 547 + qdev_realize_and_unref(dev, NULL, &error_fatal); 548 548 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 549 549 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 550 550

+2 -2

hw/display/sm501.c

··· 1969 1969 sysbus_init_mmio(sbd, &s->state.mmio_region); 1970 1970 1971 1971 /* bridge to usb host emulation module */ 1972 1972 - usb_dev = qdev_create(NULL, "sysbus-ohci"); 1972 1972 + usb_dev = qdev_new("sysbus-ohci"); 1973 1973 qdev_prop_set_uint32(usb_dev, "num-ports", 2); 1974 1974 qdev_prop_set_uint64(usb_dev, "dma-offset", s->base); 1975 1975 - qdev_init_nofail(usb_dev); 1975 1975 + qdev_realize_and_unref(usb_dev, NULL, &error_fatal); 1976 1976 memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, 1977 1977 sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0)); 1978 1978 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));

+4 -4

hw/dma/pxa2xx_dma.c

··· 495 495 { 496 496 DeviceState *dev; 497 497 498 498 - dev = qdev_create(NULL, "pxa2xx-dma"); 498 498 + dev = qdev_new("pxa2xx-dma"); 499 499 qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); 500 500 - qdev_init_nofail(dev); 500 500 + qdev_realize_and_unref(dev, NULL, &error_fatal); 501 501 502 502 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 503 503 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); ··· 509 509 { 510 510 DeviceState *dev; 511 511 512 512 - dev = qdev_create(NULL, "pxa2xx-dma"); 512 512 + dev = qdev_new("pxa2xx-dma"); 513 513 qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); 514 514 - qdev_init_nofail(dev); 514 514 + qdev_realize_and_unref(dev, NULL, &error_fatal); 515 515 516 516 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 517 517 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

+3 -2

hw/dma/rc4030.c

··· 28 28 #include "hw/mips/mips.h" 29 29 #include "hw/sysbus.h" 30 30 #include "migration/vmstate.h" 31 31 + #include "qapi/error.h" 31 32 #include "qemu/timer.h" 32 33 #include "qemu/log.h" 33 34 #include "qemu/module.h" ··· 744 745 { 745 746 DeviceState *dev; 746 747 747 747 - dev = qdev_create(NULL, TYPE_RC4030); 748 748 - qdev_init_nofail(dev); 748 748 + dev = qdev_new(TYPE_RC4030); 749 749 + qdev_realize_and_unref(dev, NULL, &error_fatal); 749 750 750 751 *dmas = rc4030_allocate_dmas(dev, 4); 751 752 *dma_mr = &RC4030(dev)->dma_mr;

+8 -8

hw/dma/sparc32_dma.c

··· 301 301 SysBusESPState *sysbus; 302 302 ESPState *esp; 303 303 304 304 - d = qdev_create(NULL, TYPE_ESP); 304 304 + d = qdev_new(TYPE_ESP); 305 305 object_property_add_child(OBJECT(dev), "esp", OBJECT(d)); 306 306 sysbus = ESP_STATE(d); 307 307 esp = &sysbus->esp; ··· 310 310 esp->dma_opaque = SPARC32_DMA_DEVICE(dev); 311 311 sysbus->it_shift = 2; 312 312 esp->dma_enabled = 1; 313 313 - qdev_init_nofail(d); 313 313 + qdev_realize_and_unref(d, NULL, &error_fatal); 314 314 } 315 315 316 316 static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data) ··· 343 343 344 344 qemu_check_nic_model(nd, TYPE_LANCE); 345 345 346 346 - d = qdev_create(NULL, TYPE_LANCE); 346 346 + d = qdev_new(TYPE_LANCE); 347 347 object_property_add_child(OBJECT(dev), "lance", OBJECT(d)); 348 348 qdev_set_nic_properties(d, nd); 349 349 object_property_set_link(OBJECT(d), OBJECT(dev), "dma", errp); 350 350 - qdev_init_nofail(d); 350 350 + qdev_realize_and_unref(d, NULL, &error_fatal); 351 351 } 352 352 353 353 static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data) ··· 378 378 return; 379 379 } 380 380 381 381 - espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE); 381 381 + espdma = qdev_new(TYPE_SPARC32_ESPDMA_DEVICE); 382 382 object_property_set_link(OBJECT(espdma), iommu, "iommu", errp); 383 383 object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma)); 384 384 - qdev_init_nofail(espdma); 384 384 + qdev_realize_and_unref(espdma, NULL, &error_fatal); 385 385 386 386 esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp")); 387 387 sbd = SYS_BUS_DEVICE(esp); ··· 393 393 memory_region_add_subregion(&s->dmamem, 0x0, 394 394 sysbus_mmio_get_region(sbd, 0)); 395 395 396 396 - ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE); 396 396 + ledma = qdev_new(TYPE_SPARC32_LEDMA_DEVICE); 397 397 object_property_set_link(OBJECT(ledma), iommu, "iommu", errp); 398 398 object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma)); 399 399 - qdev_init_nofail(ledma); 399 399 + qdev_realize_and_unref(ledma, NULL, &error_fatal); 400 400 401 401 lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance")); 402 402 sbd = SYS_BUS_DEVICE(lance);

+2 -2

hw/hppa/dino.c

··· 521 521 PCIBus *b; 522 522 int i; 523 523 524 524 - dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE); 524 524 + dev = qdev_new(TYPE_DINO_PCI_HOST_BRIDGE); 525 525 s = DINO_PCI_HOST_BRIDGE(dev); 526 526 s->iar0 = s->iar1 = CPU_HPA + 3; 527 527 s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */ ··· 548 548 &s->pci_mem, get_system_io(), 549 549 PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS); 550 550 s->parent_obj.bus = b; 551 551 - qdev_init_nofail(dev); 551 551 + qdev_realize_and_unref(dev, NULL, &error_fatal); 552 552 553 553 /* Set up windows into PCI bus memory. */ 554 554 for (i = 1; i < 31; i++) {

+2 -2

hw/hppa/lasi.c

··· 300 300 DeviceState *dev; 301 301 LasiState *s; 302 302 303 303 - dev = qdev_create(NULL, TYPE_LASI_CHIP); 303 303 + dev = qdev_new(TYPE_LASI_CHIP); 304 304 s = LASI_CHIP(dev); 305 305 s->iar = CPU_HPA + 3; 306 306 ··· 309 309 s, "lasi", 0x100000); 310 310 memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem); 311 311 312 312 - qdev_init_nofail(dev); 312 312 + qdev_realize_and_unref(dev, NULL, &error_fatal); 313 313 314 314 /* LAN */ 315 315 if (enable_lasi_lan()) {

+2 -2

hw/hppa/machine.c

··· 124 124 125 125 /* Graphics setup. */ 126 126 if (machine->enable_graphics && vga_interface_type != VGA_NONE) { 127 127 - dev = qdev_create(NULL, "artist"); 128 128 - qdev_init_nofail(dev); 127 127 + dev = qdev_new("artist"); 128 128 + qdev_realize_and_unref(dev, NULL, &error_fatal); 129 129 s = SYS_BUS_DEVICE(dev); 130 130 sysbus_mmio_map(s, 0, LASI_GFX_HPA); 131 131 sysbus_mmio_map(s, 1, ARTIST_FB_ADDR);

+3 -2

hw/i2c/core.c

··· 11 11 #include "hw/i2c/i2c.h" 12 12 #include "hw/qdev-properties.h" 13 13 #include "migration/vmstate.h" 14 14 + #include "qapi/error.h" 14 15 #include "qemu/module.h" 15 16 #include "trace.h" 16 17 ··· 270 271 { 271 272 DeviceState *dev; 272 273 273 273 - dev = qdev_create(&bus->qbus, name); 274 274 + dev = qdev_new(name); 274 275 qdev_prop_set_uint8(dev, "address", addr); 275 275 - qdev_init_nofail(dev); 276 276 + qdev_realize_and_unref(dev, &bus->qbus, &error_fatal); 276 277 return dev; 277 278 } 278 279

+2 -2

hw/i2c/smbus_eeprom.c

··· 169 169 { 170 170 DeviceState *dev; 171 171 172 172 - dev = qdev_create((BusState *) smbus, TYPE_SMBUS_EEPROM); 172 172 + dev = qdev_new(TYPE_SMBUS_EEPROM); 173 173 qdev_prop_set_uint8(dev, "address", address); 174 174 /* FIXME: use an array of byte or block backend property? */ 175 175 SMBUS_EEPROM(dev)->init_data = eeprom_buf; 176 176 - qdev_init_nofail(dev); 176 176 + qdev_realize_and_unref(dev, (BusState *)smbus, &error_fatal); 177 177 } 178 178 179 179 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,

+2 -2

hw/i386/pc_q35.c

··· 214 214 } 215 215 216 216 /* create pci host bus */ 217 217 - q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE)); 217 217 + q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); 218 218 219 219 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); 220 220 object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory), ··· 230 230 object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size, 231 231 PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); 232 232 /* pci */ 233 233 - qdev_init_nofail(DEVICE(q35_host)); 233 233 + qdev_realize_and_unref(DEVICE(q35_host), NULL, &error_fatal); 234 234 phb = PCI_HOST_BRIDGE(q35_host); 235 235 host_bus = phb->bus; 236 236 /* create ISA bus */

+3 -3

hw/i386/x86.c

··· 345 345 346 346 assert(parent_name); 347 347 if (kvm_ioapic_in_kernel()) { 348 348 - dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 348 348 + dev = qdev_new(TYPE_KVM_IOAPIC); 349 349 } else { 350 350 - dev = qdev_create(NULL, TYPE_IOAPIC); 350 350 + dev = qdev_new(TYPE_IOAPIC); 351 351 } 352 352 object_property_add_child(object_resolve_path(parent_name, NULL), 353 353 "ioapic", OBJECT(dev)); 354 354 - qdev_init_nofail(dev); 354 354 + qdev_realize_and_unref(dev, NULL, &error_fatal); 355 355 d = SYS_BUS_DEVICE(dev); 356 356 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 357 357

+2 -2

hw/ide/qdev.c

··· 127 127 { 128 128 DeviceState *dev; 129 129 130 130 - dev = qdev_create(&bus->qbus, drive->media_cd ? "ide-cd" : "ide-hd"); 130 130 + dev = qdev_new(drive->media_cd ? "ide-cd" : "ide-hd"); 131 131 qdev_prop_set_uint32(dev, "unit", unit); 132 132 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(drive), 133 133 &error_fatal); 134 134 - qdev_init_nofail(dev); 134 134 + qdev_realize_and_unref(dev, &bus->qbus, &error_fatal); 135 135 return DO_UPCAST(IDEDevice, qdev, dev); 136 136 } 137 137

+3 -2

hw/intc/exynos4210_gic.c

··· 23 23 #include "qemu/osdep.h" 24 24 #include "hw/sysbus.h" 25 25 #include "migration/vmstate.h" 26 26 + #include "qapi/error.h" 26 27 #include "qemu/module.h" 27 28 #include "hw/irq.h" 28 29 #include "hw/qdev-properties.h" ··· 296 297 uint32_t n = s->num_cpu; 297 298 uint32_t i; 298 299 299 299 - s->gic = qdev_create(NULL, "arm_gic"); 300 300 + s->gic = qdev_new("arm_gic"); 300 301 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 301 302 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); 302 302 - qdev_init_nofail(s->gic); 303 303 + qdev_realize_and_unref(s->gic, NULL, &error_fatal); 303 304 gicbusdev = SYS_BUS_DEVICE(s->gic); 304 305 305 306 /* Pass through outbound IRQ lines from the GIC */

+3 -3

hw/intc/s390_flic.c

··· 63 63 DeviceState *dev; 64 64 65 65 if (kvm_enabled()) { 66 66 - dev = qdev_create(NULL, TYPE_KVM_S390_FLIC); 66 66 + dev = qdev_new(TYPE_KVM_S390_FLIC); 67 67 object_property_add_child(qdev_get_machine(), TYPE_KVM_S390_FLIC, 68 68 OBJECT(dev)); 69 69 } else { 70 70 - dev = qdev_create(NULL, TYPE_QEMU_S390_FLIC); 70 70 + dev = qdev_new(TYPE_QEMU_S390_FLIC); 71 71 object_property_add_child(qdev_get_machine(), TYPE_QEMU_S390_FLIC, 72 72 OBJECT(dev)); 73 73 } 74 74 - qdev_init_nofail(dev); 74 74 + qdev_realize_and_unref(dev, NULL, &error_fatal); 75 75 } 76 76 77 77 static int qemu_s390_register_io_adapter(S390FLICState *fs, uint32_t id,

+2 -2

hw/isa/isa-bus.c

··· 61 61 return NULL; 62 62 } 63 63 if (!dev) { 64 64 - dev = qdev_create(NULL, "isabus-bridge"); 65 65 - qdev_init_nofail(dev); 64 64 + dev = qdev_new("isabus-bridge"); 65 65 + qdev_realize_and_unref(dev, NULL, &error_fatal); 66 66 } 67 67 68 68 isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL));

+7 -6

hw/lm32/lm32.h

··· 3 3 4 4 #include "hw/char/lm32_juart.h" 5 5 #include "hw/qdev-properties.h" 6 6 + #include "qapi/error.h" 6 7 7 8 static inline DeviceState *lm32_pic_init(qemu_irq cpu_irq) 8 9 { 9 10 DeviceState *dev; 10 11 SysBusDevice *d; 11 12 12 12 - dev = qdev_create(NULL, "lm32-pic"); 13 13 - qdev_init_nofail(dev); 13 13 + dev = qdev_new("lm32-pic"); 14 14 + qdev_realize_and_unref(dev, NULL, &error_fatal); 14 15 d = SYS_BUS_DEVICE(dev); 15 16 sysbus_connect_irq(d, 0, cpu_irq); 16 17 ··· 21 22 { 22 23 DeviceState *dev; 23 24 24 24 - dev = qdev_create(NULL, TYPE_LM32_JUART); 25 25 + dev = qdev_new(TYPE_LM32_JUART); 25 26 qdev_prop_set_chr(dev, "chardev", chr); 26 26 - qdev_init_nofail(dev); 27 27 + qdev_realize_and_unref(dev, NULL, &error_fatal); 27 28 28 29 return dev; 29 30 } ··· 35 36 DeviceState *dev; 36 37 SysBusDevice *s; 37 38 38 38 - dev = qdev_create(NULL, "lm32-uart"); 39 39 + dev = qdev_new("lm32-uart"); 39 40 s = SYS_BUS_DEVICE(dev); 40 41 qdev_prop_set_chr(dev, "chardev", chr); 41 41 - qdev_init_nofail(dev); 42 42 + qdev_realize_and_unref(dev, NULL, &error_fatal); 42 43 sysbus_mmio_map(s, 0, addr); 43 44 sysbus_connect_irq(s, 0, irq); 44 45 return dev;

+19 -18

hw/lm32/milkymist-hw.h

··· 3 3 4 4 #include "hw/qdev-core.h" 5 5 #include "net/net.h" 6 6 + #include "qapi/error.h" 6 7 7 8 static inline DeviceState *milkymist_uart_create(hwaddr base, 8 9 qemu_irq irq, ··· 10 11 { 11 12 DeviceState *dev; 12 13 13 13 - dev = qdev_create(NULL, "milkymist-uart"); 14 14 + dev = qdev_new("milkymist-uart"); 14 15 qdev_prop_set_chr(dev, "chardev", chr); 15 15 - qdev_init_nofail(dev); 16 16 + qdev_realize_and_unref(dev, NULL, &error_fatal); 16 17 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 17 18 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 18 19 ··· 23 24 { 24 25 DeviceState *dev; 25 26 26 26 - dev = qdev_create(NULL, "milkymist-hpdmc"); 27 27 - qdev_init_nofail(dev); 27 27 + dev = qdev_new("milkymist-hpdmc"); 28 28 + qdev_realize_and_unref(dev, NULL, &error_fatal); 28 29 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 29 30 30 31 return dev; ··· 34 35 { 35 36 DeviceState *dev; 36 37 37 37 - dev = qdev_create(NULL, "milkymist-memcard"); 38 38 - qdev_init_nofail(dev); 38 38 + dev = qdev_new("milkymist-memcard"); 39 39 + qdev_realize_and_unref(dev, NULL, &error_fatal); 39 40 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 40 41 41 42 return dev; ··· 46 47 { 47 48 DeviceState *dev; 48 49 49 49 - dev = qdev_create(NULL, "milkymist-vgafb"); 50 50 + dev = qdev_new("milkymist-vgafb"); 50 51 qdev_prop_set_uint32(dev, "fb_offset", fb_offset); 51 52 qdev_prop_set_uint32(dev, "fb_mask", fb_mask); 52 52 - qdev_init_nofail(dev); 53 53 + qdev_realize_and_unref(dev, NULL, &error_fatal); 53 54 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 54 55 55 56 return dev; ··· 62 63 { 63 64 DeviceState *dev; 64 65 65 65 - dev = qdev_create(NULL, "milkymist-sysctl"); 66 66 + dev = qdev_new("milkymist-sysctl"); 66 67 qdev_prop_set_uint32(dev, "frequency", freq_hz); 67 68 qdev_prop_set_uint32(dev, "systemid", system_id); 68 69 qdev_prop_set_uint32(dev, "capabilities", capabilities); 69 70 qdev_prop_set_uint32(dev, "gpio_strappings", gpio_strappings); 70 70 - qdev_init_nofail(dev); 71 71 + qdev_realize_and_unref(dev, NULL, &error_fatal); 71 72 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 72 73 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, gpio_irq); 73 74 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, timer0_irq); ··· 81 82 { 82 83 DeviceState *dev; 83 84 84 84 - dev = qdev_create(NULL, "milkymist-pfpu"); 85 85 - qdev_init_nofail(dev); 85 85 + dev = qdev_new("milkymist-pfpu"); 86 86 + qdev_realize_and_unref(dev, NULL, &error_fatal); 86 87 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 87 88 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 88 89 return dev; ··· 94 95 { 95 96 DeviceState *dev; 96 97 97 97 - dev = qdev_create(NULL, "milkymist-ac97"); 98 98 - qdev_init_nofail(dev); 98 98 + dev = qdev_new("milkymist-ac97"); 99 99 + qdev_realize_and_unref(dev, NULL, &error_fatal); 99 100 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 100 101 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, crrequest_irq); 101 102 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, crreply_irq); ··· 111 112 DeviceState *dev; 112 113 113 114 qemu_check_nic_model(&nd_table[0], "minimac2"); 114 114 - dev = qdev_create(NULL, "milkymist-minimac2"); 115 115 + dev = qdev_new("milkymist-minimac2"); 115 116 qdev_set_nic_properties(dev, &nd_table[0]); 116 116 - qdev_init_nofail(dev); 117 117 + qdev_realize_and_unref(dev, NULL, &error_fatal); 117 118 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 118 119 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, buffers_base); 119 120 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, rx_irq); ··· 128 129 { 129 130 DeviceState *dev; 130 131 131 131 - dev = qdev_create(NULL, "milkymist-softusb"); 132 132 + dev = qdev_new("milkymist-softusb"); 132 133 qdev_prop_set_uint32(dev, "pmem_size", pmem_size); 133 134 qdev_prop_set_uint32(dev, "dmem_size", dmem_size); 134 134 - qdev_init_nofail(dev); 135 135 + qdev_realize_and_unref(dev, NULL, &error_fatal); 135 136 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 136 137 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, pmem_base); 137 138 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, dmem_base);

+2 -2

hw/m68k/mcf5208.c

··· 214 214 int i; 215 215 216 216 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET); 217 217 - dev = qdev_create(NULL, TYPE_MCF_FEC_NET); 217 217 + dev = qdev_new(TYPE_MCF_FEC_NET); 218 218 qdev_set_nic_properties(dev, nd); 219 219 - qdev_init_nofail(dev); 219 219 + qdev_realize_and_unref(dev, NULL, &error_fatal); 220 220 221 221 s = SYS_BUS_DEVICE(dev); 222 222 for (i = 0; i < FEC_NUM_IRQ; i++) {

+3 -2

hw/m68k/mcf_intc.c

··· 7 7 */ 8 8 9 9 #include "qemu/osdep.h" 10 10 + #include "qapi/error.h" 10 11 #include "qemu/module.h" 11 12 #include "qemu/log.h" 12 13 #include "cpu.h" ··· 204 205 DeviceState *dev; 205 206 mcf_intc_state *s; 206 207 207 207 - dev = qdev_create(NULL, TYPE_MCF_INTC); 208 208 - qdev_init_nofail(dev); 208 208 + dev = qdev_new(TYPE_MCF_INTC); 209 209 + qdev_realize_and_unref(dev, NULL, &error_fatal); 209 210 210 211 s = MCF_INTC(dev); 211 212 s->cpu = cpu;

+6 -6

hw/m68k/next-cube.c

··· 839 839 DeviceState *dev; 840 840 SysBusDevice *s; 841 841 842 842 - dev = qdev_create(NULL, TYPE_ESCC); 842 842 + dev = qdev_new(TYPE_ESCC); 843 843 qdev_prop_set_uint32(dev, "disabled", 0); 844 844 qdev_prop_set_uint32(dev, "frequency", 9600 * 384); 845 845 qdev_prop_set_uint32(dev, "it_shift", 0); ··· 848 848 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 849 849 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 850 850 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 851 851 - qdev_init_nofail(dev); 851 851 + qdev_realize_and_unref(dev, NULL, &error_fatal); 852 852 853 853 s = SYS_BUS_DEVICE(dev); 854 854 sysbus_connect_irq(s, 0, ser_irq[0]); ··· 895 895 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 896 896 897 897 /* Framebuffer */ 898 898 - dev = qdev_create(NULL, TYPE_NEXTFB); 899 899 - qdev_init_nofail(dev); 898 898 + dev = qdev_new(TYPE_NEXTFB); 899 899 + qdev_realize_and_unref(dev, NULL, &error_fatal); 900 900 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000); 901 901 902 902 /* MMIO */ ··· 918 918 memory_region_add_subregion(sysmem, 0x02100000, scrmem); 919 919 920 920 /* KBD */ 921 921 - dev = qdev_create(NULL, TYPE_NEXTKBD); 922 922 - qdev_init_nofail(dev); 921 921 + dev = qdev_new(TYPE_NEXTKBD); 922 922 + qdev_realize_and_unref(dev, NULL, &error_fatal); 923 923 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000); 924 924 925 925 /* Load ROM here */

+18 -18

hw/m68k/q800.c

··· 218 218 219 219 /* VIA */ 220 220 221 221 - via_dev = qdev_create(NULL, TYPE_MAC_VIA); 221 221 + via_dev = qdev_new(TYPE_MAC_VIA); 222 222 dinfo = drive_get(IF_MTD, 0, 0); 223 223 if (dinfo) { 224 224 qdev_prop_set_drive(via_dev, "drive", blk_by_legacy_dinfo(dinfo), 225 225 &error_abort); 226 226 } 227 227 - qdev_init_nofail(via_dev); 227 227 + qdev_realize_and_unref(via_dev, NULL, &error_fatal); 228 228 sysbus = SYS_BUS_DEVICE(via_dev); 229 229 sysbus_mmio_map(sysbus, 0, VIA_BASE); 230 230 qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, pic[0]); ··· 232 232 233 233 234 234 adb_bus = qdev_get_child_bus(via_dev, "adb.0"); 235 235 - dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 236 236 - qdev_init_nofail(dev); 237 237 - dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 238 238 - qdev_init_nofail(dev); 235 235 + dev = qdev_new(TYPE_ADB_KEYBOARD); 236 236 + qdev_realize_and_unref(dev, adb_bus, &error_fatal); 237 237 + dev = qdev_new(TYPE_ADB_MOUSE); 238 238 + qdev_realize_and_unref(dev, adb_bus, &error_fatal); 239 239 240 240 /* MACSONIC */ 241 241 ··· 259 259 nd_table[0].macaddr.a[1] = 0x00; 260 260 nd_table[0].macaddr.a[2] = 0x07; 261 261 262 262 - dev = qdev_create(NULL, "dp8393x"); 262 262 + dev = qdev_new("dp8393x"); 263 263 qdev_set_nic_properties(dev, &nd_table[0]); 264 264 qdev_prop_set_uint8(dev, "it_shift", 2); 265 265 qdev_prop_set_bit(dev, "big_endian", true); 266 266 object_property_set_link(OBJECT(dev), OBJECT(get_system_memory()), 267 267 "dma_mr", &error_abort); 268 268 - qdev_init_nofail(dev); 268 268 + qdev_realize_and_unref(dev, NULL, &error_fatal); 269 269 sysbus = SYS_BUS_DEVICE(dev); 270 270 sysbus_mmio_map(sysbus, 0, SONIC_BASE); 271 271 sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE); ··· 273 273 274 274 /* SCC */ 275 275 276 276 - dev = qdev_create(NULL, TYPE_ESCC); 276 276 + dev = qdev_new(TYPE_ESCC); 277 277 qdev_prop_set_uint32(dev, "disabled", 0); 278 278 qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK); 279 279 qdev_prop_set_uint32(dev, "it_shift", 1); ··· 282 282 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 283 283 qdev_prop_set_uint32(dev, "chnBtype", 0); 284 284 qdev_prop_set_uint32(dev, "chnAtype", 0); 285 285 - qdev_init_nofail(dev); 285 285 + qdev_realize_and_unref(dev, NULL, &error_fatal); 286 286 sysbus = SYS_BUS_DEVICE(dev); 287 287 sysbus_connect_irq(sysbus, 0, pic[3]); 288 288 sysbus_connect_irq(sysbus, 1, pic[3]); ··· 290 290 291 291 /* SCSI */ 292 292 293 293 - dev = qdev_create(NULL, TYPE_ESP); 293 293 + dev = qdev_new(TYPE_ESP); 294 294 sysbus_esp = ESP_STATE(dev); 295 295 esp = &sysbus_esp->esp; 296 296 esp->dma_memory_read = NULL; ··· 298 298 esp->dma_opaque = NULL; 299 299 sysbus_esp->it_shift = 4; 300 300 esp->dma_enabled = 1; 301 301 - qdev_init_nofail(dev); 301 301 + qdev_realize_and_unref(dev, NULL, &error_fatal); 302 302 303 303 sysbus = SYS_BUS_DEVICE(dev); 304 304 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in_named(via_dev, ··· 314 314 315 315 /* SWIM floppy controller */ 316 316 317 317 - dev = qdev_create(NULL, TYPE_SWIM); 318 318 - qdev_init_nofail(dev); 317 317 + dev = qdev_new(TYPE_SWIM); 318 318 + qdev_realize_and_unref(dev, NULL, &error_fatal); 319 319 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE); 320 320 321 321 /* NuBus */ 322 322 323 323 - dev = qdev_create(NULL, TYPE_MAC_NUBUS_BRIDGE); 324 324 - qdev_init_nofail(dev); 323 323 + dev = qdev_new(TYPE_MAC_NUBUS_BRIDGE); 324 324 + qdev_realize_and_unref(dev, NULL, &error_fatal); 325 325 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, NUBUS_SUPER_SLOT_BASE); 326 326 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE); 327 327 ··· 329 329 330 330 /* framebuffer in nubus slot #9 */ 331 331 332 332 - dev = qdev_create(BUS(nubus), TYPE_NUBUS_MACFB); 332 332 + dev = qdev_new(TYPE_NUBUS_MACFB); 333 333 qdev_prop_set_uint32(dev, "width", graphic_width); 334 334 qdev_prop_set_uint32(dev, "height", graphic_height); 335 335 qdev_prop_set_uint8(dev, "depth", graphic_depth); 336 336 - qdev_init_nofail(dev); 336 336 + qdev_realize_and_unref(dev, BUS(nubus), &error_fatal); 337 337 338 338 cs = CPU(cpu); 339 339 if (linux_boot) {

+10 -10

hw/microblaze/petalogix_ml605_mmu.c

··· 110 110 64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0); 111 111 112 112 113 113 - dev = qdev_create(NULL, "xlnx.xps-intc"); 113 113 + dev = qdev_new("xlnx.xps-intc"); 114 114 qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); 115 115 - qdev_init_nofail(dev); 115 115 + qdev_realize_and_unref(dev, NULL, &error_fatal); 116 116 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 117 117 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 118 118 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ)); ··· 125 125 DEVICE_LITTLE_ENDIAN); 126 126 127 127 /* 2 timers at irq 2 @ 100 Mhz. */ 128 128 - dev = qdev_create(NULL, "xlnx.xps-timer"); 128 128 + dev = qdev_new("xlnx.xps-timer"); 129 129 qdev_prop_set_uint32(dev, "one-timer-only", 0); 130 130 qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); 131 131 - qdev_init_nofail(dev); 131 131 + qdev_realize_and_unref(dev, NULL, &error_fatal); 132 132 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 133 133 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 134 134 135 135 /* axi ethernet and dma initialization. */ 136 136 qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet"); 137 137 - eth0 = qdev_create(NULL, "xlnx.axi-ethernet"); 138 138 - dma = qdev_create(NULL, "xlnx.axi-dma"); 137 137 + eth0 = qdev_new("xlnx.axi-ethernet"); 138 138 + dma = qdev_new("xlnx.axi-dma"); 139 139 140 140 /* FIXME: attach to the sysbus instead */ 141 141 object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0)); ··· 152 152 "axistream-connected", &error_abort); 153 153 object_property_set_link(OBJECT(eth0), cs, 154 154 "axistream-control-connected", &error_abort); 155 155 - qdev_init_nofail(eth0); 155 155 + qdev_realize_and_unref(eth0, NULL, &error_fatal); 156 156 sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR); 157 157 sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]); 158 158 ··· 165 165 "axistream-connected", &error_abort); 166 166 object_property_set_link(OBJECT(dma), cs, 167 167 "axistream-control-connected", &error_abort); 168 168 - qdev_init_nofail(dma); 168 168 + qdev_realize_and_unref(dma, NULL, &error_fatal); 169 169 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); 170 170 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]); 171 171 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]); ··· 173 173 { 174 174 SSIBus *spi; 175 175 176 176 - dev = qdev_create(NULL, "xlnx.xps-spi"); 176 176 + dev = qdev_new("xlnx.xps-spi"); 177 177 qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); 178 178 - qdev_init_nofail(dev); 178 178 + qdev_realize_and_unref(dev, NULL, &error_fatal); 179 179 busdev = SYS_BUS_DEVICE(dev); 180 180 sysbus_mmio_map(busdev, 0, SPI_BASEADDR); 181 181 sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);

+6 -6

hw/microblaze/petalogix_s3adsp1800_mmu.c

··· 89 89 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 90 90 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); 91 91 92 92 - dev = qdev_create(NULL, "xlnx.xps-intc"); 92 92 + dev = qdev_new("xlnx.xps-intc"); 93 93 qdev_prop_set_uint32(dev, "kind-of-intr", 94 94 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); 95 95 - qdev_init_nofail(dev); 95 95 + qdev_realize_and_unref(dev, NULL, &error_fatal); 96 96 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 97 97 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 98 98 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ)); ··· 104 104 serial_hd(0)); 105 105 106 106 /* 2 timers at irq 2 @ 62 Mhz. */ 107 107 - dev = qdev_create(NULL, "xlnx.xps-timer"); 107 107 + dev = qdev_new("xlnx.xps-timer"); 108 108 qdev_prop_set_uint32(dev, "one-timer-only", 0); 109 109 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); 110 110 - qdev_init_nofail(dev); 110 110 + qdev_realize_and_unref(dev, NULL, &error_fatal); 111 111 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 112 112 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 113 113 114 114 qemu_check_nic_model(&nd_table[0], "xlnx.xps-ethernetlite"); 115 115 - dev = qdev_create(NULL, "xlnx.xps-ethernetlite"); 115 115 + dev = qdev_new("xlnx.xps-ethernetlite"); 116 116 qdev_set_nic_properties(dev, &nd_table[0]); 117 117 qdev_prop_set_uint32(dev, "tx-ping-pong", 0); 118 118 qdev_prop_set_uint32(dev, "rx-ping-pong", 0); 119 119 - qdev_init_nofail(dev); 119 119 + qdev_realize_and_unref(dev, NULL, &error_fatal); 120 120 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); 121 121 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); 122 122

+4 -4

hw/mips/boston.c

··· 400 400 DeviceState *dev; 401 401 MemoryRegion *cfg, *mmio; 402 402 403 403 - dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST); 403 403 + dev = qdev_new(TYPE_XILINX_PCIE_HOST); 404 404 405 405 qdev_prop_set_uint32(dev, "bus_nr", bus_nr); 406 406 qdev_prop_set_uint64(dev, "cfg_base", cfg_base); ··· 409 409 qdev_prop_set_uint64(dev, "mmio_size", mmio_size); 410 410 qdev_prop_set_bit(dev, "link_up", link_up); 411 411 412 412 - qdev_init_nofail(dev); 412 412 + qdev_realize_and_unref(dev, NULL, &error_fatal); 413 413 414 414 cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 415 415 memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); ··· 441 441 exit(1); 442 442 } 443 443 444 444 - dev = qdev_create(NULL, TYPE_MIPS_BOSTON); 445 445 - qdev_init_nofail(dev); 444 444 + dev = qdev_new(TYPE_MIPS_BOSTON); 445 445 + qdev_realize_and_unref(dev, NULL, &error_fatal); 446 446 447 447 s = BOSTON(dev); 448 448 s->mach = machine;

+3 -2

hw/mips/gt64xxx_pci.c

··· 23 23 */ 24 24 25 25 #include "qemu/osdep.h" 26 26 + #include "qapi/error.h" 26 27 #include "qemu/units.h" 27 28 #include "qemu/log.h" 28 29 #include "hw/mips/mips.h" ··· 1201 1202 PCIHostState *phb; 1202 1203 DeviceState *dev; 1203 1204 1204 1204 - dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE); 1205 1205 + dev = qdev_new(TYPE_GT64120_PCI_HOST_BRIDGE); 1205 1206 d = GT64120_PCI_HOST_BRIDGE(dev); 1206 1207 phb = PCI_HOST_BRIDGE(dev); 1207 1208 memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); ··· 1212 1213 &d->pci0_mem, 1213 1214 get_system_io(), 1214 1215 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); 1215 1215 - qdev_init_nofail(dev); 1216 1216 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1216 1217 memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, 1217 1218 "isd-mem", 0x1000); 1218 1219

+8 -8

hw/mips/jazz.c

··· 255 255 /* Video card */ 256 256 switch (jazz_model) { 257 257 case JAZZ_MAGNUM: 258 258 - dev = qdev_create(NULL, "sysbus-g364"); 259 259 - qdev_init_nofail(dev); 258 258 + dev = qdev_new("sysbus-g364"); 259 259 + qdev_realize_and_unref(dev, NULL, &error_fatal); 260 260 sysbus = SYS_BUS_DEVICE(dev); 261 261 sysbus_mmio_map(sysbus, 0, 0x60080000); 262 262 sysbus_mmio_map(sysbus, 1, 0x40000000); ··· 287 287 if (strcmp(nd->model, "dp83932") == 0) { 288 288 qemu_check_nic_model(nd, "dp83932"); 289 289 290 290 - dev = qdev_create(NULL, "dp8393x"); 290 290 + dev = qdev_new("dp8393x"); 291 291 qdev_set_nic_properties(dev, nd); 292 292 qdev_prop_set_uint8(dev, "it_shift", 2); 293 293 object_property_set_link(OBJECT(dev), OBJECT(rc4030_dma_mr), 294 294 "dma_mr", &error_abort); 295 295 - qdev_init_nofail(dev); 295 295 + qdev_realize_and_unref(dev, NULL, &error_fatal); 296 296 sysbus = SYS_BUS_DEVICE(dev); 297 297 sysbus_mmio_map(sysbus, 0, 0x80001000); 298 298 sysbus_mmio_map(sysbus, 1, 0x8000b000); ··· 308 308 } 309 309 310 310 /* SCSI adapter */ 311 311 - dev = qdev_create(NULL, TYPE_ESP); 311 311 + dev = qdev_new(TYPE_ESP); 312 312 sysbus_esp = ESP_STATE(dev); 313 313 esp = &sysbus_esp->esp; 314 314 esp->dma_memory_read = rc4030_dma_read; ··· 317 317 sysbus_esp->it_shift = 0; 318 318 /* XXX for now until rc4030 has been changed to use DMA enable signal */ 319 319 esp->dma_enabled = 1; 320 320 - qdev_init_nofail(dev); 320 320 + qdev_realize_and_unref(dev, NULL, &error_fatal); 321 321 322 322 sysbus = SYS_BUS_DEVICE(dev); 323 323 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5)); ··· 362 362 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ 363 363 364 364 /* NVRAM */ 365 365 - dev = qdev_create(NULL, "ds1225y"); 366 366 - qdev_init_nofail(dev); 365 365 + dev = qdev_new("ds1225y"); 366 366 + qdev_realize_and_unref(dev, NULL, &error_fatal); 367 367 sysbus = SYS_BUS_DEVICE(dev); 368 368 sysbus_mmio_map(sysbus, 0, 0x80009000); 369 369

+2 -2

hw/mips/malta.c

··· 1233 1233 int fl_idx = 0; 1234 1234 int be; 1235 1235 1236 1236 - DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA); 1236 1236 + DeviceState *dev = qdev_new(TYPE_MIPS_MALTA); 1237 1237 MaltaState *s = MIPS_MALTA(dev); 1238 1238 1239 1239 /* ··· 1243 1243 */ 1244 1244 empty_slot_init("GT64120", 0, 0x20000000); 1245 1245 1246 1246 - qdev_init_nofail(dev); 1246 1246 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1247 1247 1248 1248 /* create CPU */ 1249 1249 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);

+4 -4

hw/mips/mipssim.c

··· 129 129 DeviceState *dev; 130 130 SysBusDevice *s; 131 131 132 132 - dev = qdev_create(NULL, "mipsnet"); 132 132 + dev = qdev_new("mipsnet"); 133 133 qdev_set_nic_properties(dev, nd); 134 134 - qdev_init_nofail(dev); 134 134 + qdev_realize_and_unref(dev, NULL, &error_fatal); 135 135 136 136 s = SYS_BUS_DEVICE(dev); 137 137 sysbus_connect_irq(s, 0, irq); ··· 216 216 * MIPS CPU INT2, which is interrupt 4. 217 217 */ 218 218 if (serial_hd(0)) { 219 219 - DeviceState *dev = qdev_create(NULL, TYPE_SERIAL_IO); 219 219 + DeviceState *dev = qdev_new(TYPE_SERIAL_IO); 220 220 221 221 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); 222 222 qdev_set_legacy_instance_id(dev, 0x3f8, 2); 223 223 - qdev_init_nofail(dev); 223 223 + qdev_realize_and_unref(dev, NULL, &error_fatal); 224 224 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]); 225 225 sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8, 226 226 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));

+3 -2

hw/misc/empty_slot.c

··· 13 13 #include "hw/sysbus.h" 14 14 #include "hw/qdev-properties.h" 15 15 #include "hw/misc/empty_slot.h" 16 16 + #include "qapi/error.h" 16 17 #include "trace.h" 17 18 18 19 #define TYPE_EMPTY_SLOT "empty_slot" ··· 56 57 /* Only empty slots larger than 0 byte need handling. */ 57 58 DeviceState *dev; 58 59 59 59 - dev = qdev_create(NULL, TYPE_EMPTY_SLOT); 60 60 + dev = qdev_new(TYPE_EMPTY_SLOT); 60 61 61 62 qdev_prop_set_uint64(dev, "size", slot_size); 62 62 - qdev_init_nofail(dev); 63 63 + qdev_realize_and_unref(dev, NULL, &error_fatal); 63 64 64 65 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, addr, -10000); 65 66 }

+2 -2

hw/net/etraxfs_eth.c

··· 654 654 DeviceState *dev; 655 655 qemu_check_nic_model(nd, "fseth"); 656 656 657 657 - dev = qdev_create(NULL, "etraxfs-eth"); 657 657 + dev = qdev_new("etraxfs-eth"); 658 658 qdev_set_nic_properties(dev, nd); 659 659 qdev_prop_set_uint32(dev, "phyaddr", phyaddr); 660 660 ··· 668 668 */ 669 669 ETRAX_FS_ETH(dev)->dma_out = dma_out; 670 670 ETRAX_FS_ETH(dev)->dma_in = dma_in; 671 671 - qdev_init_nofail(dev); 671 671 + qdev_realize_and_unref(dev, NULL, &error_fatal); 672 672 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 673 673 674 674 return dev;

+3 -2

hw/net/fsl_etsec/etsec.c

··· 33 33 #include "hw/qdev-properties.h" 34 34 #include "etsec.h" 35 35 #include "registers.h" 36 36 + #include "qapi/error.h" 36 37 #include "qemu/log.h" 37 38 #include "qemu/module.h" 38 39 ··· 452 453 { 453 454 DeviceState *dev; 454 455 455 455 - dev = qdev_create(NULL, "eTSEC"); 456 456 + dev = qdev_new("eTSEC"); 456 457 qdev_set_nic_properties(dev, nd); 457 457 - qdev_init_nofail(dev); 458 458 + qdev_realize_and_unref(dev, NULL, &error_fatal); 458 459 459 460 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq); 460 461 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);

+3 -2

hw/net/lan9118.c

··· 20 20 #include "hw/net/lan9118.h" 21 21 #include "hw/ptimer.h" 22 22 #include "hw/qdev-properties.h" 23 23 + #include "qapi/error.h" 23 24 #include "qemu/log.h" 24 25 #include "qemu/module.h" 25 26 /* For crc32 */ ··· 1394 1395 SysBusDevice *s; 1395 1396 1396 1397 qemu_check_nic_model(nd, "lan9118"); 1397 1397 - dev = qdev_create(NULL, TYPE_LAN9118); 1398 1398 + dev = qdev_new(TYPE_LAN9118); 1398 1399 qdev_set_nic_properties(dev, nd); 1399 1399 - qdev_init_nofail(dev); 1400 1400 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1400 1401 s = SYS_BUS_DEVICE(dev); 1401 1402 sysbus_mmio_map(s, 0, base); 1402 1403 sysbus_connect_irq(s, 0, irq);

+3 -2

hw/net/lasi_i82596.c

··· 11 11 */ 12 12 13 13 #include "qemu/osdep.h" 14 14 + #include "qapi/error.h" 14 15 #include "qemu/timer.h" 15 16 #include "hw/sysbus.h" 16 17 #include "net/eth.h" ··· 126 127 .a = { 0x08, 0x00, 0x09, 0xef, 0x34, 0xf6 } }; 127 128 128 129 qemu_check_nic_model(&nd_table[0], TYPE_LASI_82596); 129 129 - dev = qdev_create(NULL, TYPE_LASI_82596); 130 130 + dev = qdev_new(TYPE_LASI_82596); 130 131 s = SYSBUS_I82596(dev); 131 132 s->state.irq = lan_irq; 132 133 qdev_set_nic_properties(dev, &nd_table[0]); 133 133 - qdev_init_nofail(dev); 134 134 + qdev_realize_and_unref(dev, NULL, &error_fatal); 134 135 s->state.conf.macaddr = HP_MAC; /* set HP MAC prefix */ 135 136 136 137 /* LASI 82596 ports in main memory. */

+3 -2

hw/net/smc91c111.c

··· 14 14 #include "hw/irq.h" 15 15 #include "hw/net/smc91c111.h" 16 16 #include "hw/qdev-properties.h" 17 17 + #include "qapi/error.h" 17 18 #include "qemu/log.h" 18 19 #include "qemu/module.h" 19 20 /* For crc32 */ ··· 821 822 SysBusDevice *s; 822 823 823 824 qemu_check_nic_model(nd, "smc91c111"); 824 824 - dev = qdev_create(NULL, TYPE_SMC91C111); 825 825 + dev = qdev_new(TYPE_SMC91C111); 825 826 qdev_set_nic_properties(dev, nd); 826 826 - qdev_init_nofail(dev); 827 827 + qdev_realize_and_unref(dev, NULL, &error_fatal); 827 828 s = SYS_BUS_DEVICE(dev); 828 829 sysbus_mmio_map(s, 0, base); 829 830 sysbus_connect_irq(s, 0, irq);

+2 -2

hw/net/spapr_llan.c

··· 372 372 { 373 373 DeviceState *dev; 374 374 375 375 - dev = qdev_create(&bus->bus, "spapr-vlan"); 375 375 + dev = qdev_new("spapr-vlan"); 376 376 377 377 qdev_set_nic_properties(dev, nd); 378 378 379 379 - qdev_init_nofail(dev); 379 379 + qdev_realize_and_unref(dev, &bus->bus, &error_fatal); 380 380 } 381 381 382 382 static int spapr_vlan_devnode(SpaprVioDevice *dev, void *fdt, int node_off)

+6 -6

hw/nios2/10m50_devboard.c

··· 80 80 cpu_irq = nios2_cpu_pic_init(cpu); 81 81 82 82 /* Register: Internal Interrupt Controller (IIC) */ 83 83 - dev = qdev_create(NULL, "altera,iic"); 83 83 + dev = qdev_new("altera,iic"); 84 84 object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu)); 85 85 - qdev_init_nofail(dev); 85 85 + qdev_realize_and_unref(dev, NULL, &error_fatal); 86 86 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); 87 87 for (i = 0; i < 32; i++) { 88 88 irq[i] = qdev_get_gpio_in(dev, i); ··· 93 93 serial_hd(0), DEVICE_NATIVE_ENDIAN); 94 94 95 95 /* Register: Timer sys_clk_timer */ 96 96 - dev = qdev_create(NULL, "ALTR.timer"); 96 96 + dev = qdev_new("ALTR.timer"); 97 97 qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000); 98 98 - qdev_init_nofail(dev); 98 98 + qdev_realize_and_unref(dev, NULL, &error_fatal); 99 99 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xf8001440); 100 100 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[0]); 101 101 102 102 /* Register: Timer sys_clk_timer_1 */ 103 103 - dev = qdev_create(NULL, "ALTR.timer"); 103 103 + dev = qdev_new("ALTR.timer"); 104 104 qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000); 105 105 - qdev_init_nofail(dev); 105 105 + qdev_realize_and_unref(dev, NULL, &error_fatal); 106 106 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880); 107 107 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]); 108 108

+4 -4

hw/nvram/fw_cfg.c

··· 1099 1099 FWCfgState *s; 1100 1100 bool dma_requested = dma_iobase && dma_as; 1101 1101 1102 1102 - dev = qdev_create(NULL, TYPE_FW_CFG_IO); 1102 1102 + dev = qdev_new(TYPE_FW_CFG_IO); 1103 1103 if (!dma_requested) { 1104 1104 qdev_prop_set_bit(dev, "dma_enabled", false); 1105 1105 } 1106 1106 1107 1107 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1108 1108 OBJECT(dev)); 1109 1109 - qdev_init_nofail(dev); 1109 1109 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1110 1110 1111 1111 sbd = SYS_BUS_DEVICE(dev); 1112 1112 ios = FW_CFG_IO(dev); ··· 1138 1138 FWCfgState *s; 1139 1139 bool dma_requested = dma_addr && dma_as; 1140 1140 1141 1141 - dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 1141 1141 + dev = qdev_new(TYPE_FW_CFG_MEM); 1142 1142 qdev_prop_set_uint32(dev, "data_width", data_width); 1143 1143 if (!dma_requested) { 1144 1144 qdev_prop_set_bit(dev, "dma_enabled", false); ··· 1146 1146 1147 1147 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1148 1148 OBJECT(dev)); 1149 1149 - qdev_init_nofail(dev); 1149 1149 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1150 1150 1151 1151 sbd = SYS_BUS_DEVICE(dev); 1152 1152 sysbus_mmio_map(sbd, 0, ctl_addr);

+4 -4

hw/openrisc/openrisc_sim.c

··· 59 59 SysBusDevice *s; 60 60 int i; 61 61 62 62 - dev = qdev_create(NULL, "open_eth"); 62 62 + dev = qdev_new("open_eth"); 63 63 qdev_set_nic_properties(dev, nd); 64 64 - qdev_init_nofail(dev); 64 64 + qdev_realize_and_unref(dev, NULL, &error_fatal); 65 65 66 66 s = SYS_BUS_DEVICE(dev); 67 67 for (i = 0; i < num_cpus; i++) { ··· 78 78 SysBusDevice *s; 79 79 int i; 80 80 81 81 - dev = qdev_create(NULL, "or1k-ompic"); 81 81 + dev = qdev_new("or1k-ompic"); 82 82 qdev_prop_set_uint32(dev, "num-cpus", num_cpus); 83 83 - qdev_init_nofail(dev); 83 83 + qdev_realize_and_unref(dev, NULL, &error_fatal); 84 84 85 85 s = SYS_BUS_DEVICE(dev); 86 86 for (i = 0; i < num_cpus; i++) {

+2 -2

hw/pci-bridge/pci_expander_bridge.c

··· 231 231 dev_name = dev->qdev.id; 232 232 } 233 233 234 234 - ds = qdev_create(NULL, TYPE_PXB_HOST); 234 234 + ds = qdev_new(TYPE_PXB_HOST); 235 235 if (pcie) { 236 236 bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS); 237 237 } else { ··· 255 255 goto err_register_bus; 256 256 } 257 257 258 258 - qdev_init_nofail(ds); 258 258 + qdev_realize_and_unref(ds, NULL, &error_fatal); 259 259 if (bds) { 260 260 qdev_init_nofail(bds); 261 261 }

+3 -2

hw/pci-host/bonito.c

··· 40 40 41 41 #include "qemu/osdep.h" 42 42 #include "qemu/units.h" 43 43 + #include "qapi/error.h" 43 44 #include "qemu/error-report.h" 44 45 #include "hw/pci/pci.h" 45 46 #include "hw/irq.h" ··· 743 744 PCIBonitoState *s; 744 745 PCIDevice *d; 745 746 746 746 - dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE); 747 747 + dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE); 747 748 phb = PCI_HOST_BRIDGE(dev); 748 749 pcihost = BONITO_PCI_HOST_BRIDGE(dev); 749 750 pcihost->pic = pic; 750 750 - qdev_init_nofail(dev); 751 751 + qdev_realize_and_unref(dev, NULL, &error_fatal); 751 752 752 753 d = pci_create(phb->bus, PCI_DEVFN(0, 0), TYPE_PCI_BONITO); 753 754 s = PCI_BONITO(d);

+2 -2

hw/pci-host/i440fx.c

··· 271 271 unsigned i; 272 272 I440FXState *i440fx; 273 273 274 274 - dev = qdev_create(NULL, host_type); 274 274 + dev = qdev_new(host_type); 275 275 s = PCI_HOST_BRIDGE(dev); 276 276 b = pci_root_bus_new(dev, NULL, pci_address_space, 277 277 address_space_io, 0, TYPE_PCI_BUS); 278 278 s->bus = b; 279 279 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev)); 280 280 - qdev_init_nofail(dev); 280 280 + qdev_realize_and_unref(dev, NULL, &error_fatal); 281 281 282 282 d = pci_create_simple(b, 0, pci_type); 283 283 *pi440fx_state = I440FX_PCI_DEVICE(d);

+3 -2

hw/pcmcia/pxa2xx.c

··· 13 13 #include "qemu/osdep.h" 14 14 #include "hw/irq.h" 15 15 #include "hw/sysbus.h" 16 16 + #include "qapi/error.h" 16 17 #include "qemu/module.h" 17 18 #include "hw/pcmcia.h" 18 19 #include "hw/arm/pxa.h" ··· 147 148 DeviceState *dev; 148 149 PXA2xxPCMCIAState *s; 149 150 150 150 - dev = qdev_create(NULL, TYPE_PXA2XX_PCMCIA); 151 151 + dev = qdev_new(TYPE_PXA2XX_PCMCIA); 151 152 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 152 153 s = PXA2XX_PCMCIA(dev); 153 154 154 154 - qdev_init_nofail(dev); 155 155 + qdev_realize_and_unref(dev, NULL, &error_fatal); 155 156 156 157 return s; 157 158 }

+16 -16

hw/ppc/e500.c

··· 743 743 unsigned int smp_cpus = machine->smp.cpus; 744 744 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 745 745 746 746 - dev = qdev_create(NULL, TYPE_OPENPIC); 746 746 + dev = qdev_new(TYPE_OPENPIC); 747 747 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); 748 748 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 749 749 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 750 750 751 751 - qdev_init_nofail(dev); 751 751 + qdev_realize_and_unref(dev, NULL, &error_fatal); 752 752 s = SYS_BUS_DEVICE(dev); 753 753 754 754 k = 0; ··· 768 768 DeviceState *dev; 769 769 CPUState *cs; 770 770 771 771 - dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 771 771 + dev = qdev_new(TYPE_KVM_OPENPIC); 772 772 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 773 773 774 774 - object_property_set_bool(OBJECT(dev), true, "realized", &err); 774 774 + qdev_realize_and_unref(dev, NULL, &err); 775 775 if (err) { 776 776 error_propagate(errp, err); 777 777 object_unparent(OBJECT(dev)); ··· 913 913 /* Register Memory */ 914 914 memory_region_add_subregion(address_space_mem, 0, machine->ram); 915 915 916 916 - dev = qdev_create(NULL, "e500-ccsr"); 916 916 + dev = qdev_new("e500-ccsr"); 917 917 object_property_add_child(qdev_get_machine(), "e500-ccsr", 918 918 OBJECT(dev)); 919 919 - qdev_init_nofail(dev); 919 919 + qdev_realize_and_unref(dev, NULL, &error_fatal); 920 920 ccsr = CCSR(dev); 921 921 ccsr_addr_space = &ccsr->ccsr_space; 922 922 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, ··· 937 937 serial_hd(1), DEVICE_BIG_ENDIAN); 938 938 } 939 939 /* I2C */ 940 940 - dev = qdev_create(NULL, "mpc-i2c"); 940 940 + dev = qdev_new("mpc-i2c"); 941 941 s = SYS_BUS_DEVICE(dev); 942 942 - qdev_init_nofail(dev); 942 942 + qdev_realize_and_unref(dev, NULL, &error_fatal); 943 943 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 944 944 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 945 945 sysbus_mmio_get_region(s, 0)); ··· 948 948 949 949 950 950 /* General Utility device */ 951 951 - dev = qdev_create(NULL, "mpc8544-guts"); 952 952 - qdev_init_nofail(dev); 951 951 + dev = qdev_new("mpc8544-guts"); 952 952 + qdev_realize_and_unref(dev, NULL, &error_fatal); 953 953 s = SYS_BUS_DEVICE(dev); 954 954 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 955 955 sysbus_mmio_get_region(s, 0)); 956 956 957 957 /* PCI */ 958 958 - dev = qdev_create(NULL, "e500-pcihost"); 958 958 + dev = qdev_new("e500-pcihost"); 959 959 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev)); 960 960 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 961 961 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 962 962 - qdev_init_nofail(dev); 962 962 + qdev_realize_and_unref(dev, NULL, &error_fatal); 963 963 s = SYS_BUS_DEVICE(dev); 964 964 for (i = 0; i < PCI_NUM_PINS; i++) { 965 965 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); ··· 985 985 if (pmc->has_mpc8xxx_gpio) { 986 986 qemu_irq poweroff_irq; 987 987 988 988 - dev = qdev_create(NULL, "mpc8xxx_gpio"); 988 988 + dev = qdev_new("mpc8xxx_gpio"); 989 989 s = SYS_BUS_DEVICE(dev); 990 990 - qdev_init_nofail(dev); 990 990 + qdev_realize_and_unref(dev, NULL, &error_fatal); 991 991 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 992 992 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 993 993 sysbus_mmio_get_region(s, 0)); ··· 999 999 1000 1000 /* Platform Bus Device */ 1001 1001 if (pmc->has_platform_bus) { 1002 1002 - dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1002 1002 + dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1003 1003 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1004 1004 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1005 1005 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1006 1006 - qdev_init_nofail(dev); 1006 1006 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1007 1007 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1008 1008 1009 1009 s = SYS_BUS_DEVICE(pms->pbus_dev);

+20 -20

hw/ppc/mac_newworld.c

··· 242 242 } 243 243 244 244 /* UniN init */ 245 245 - dev = qdev_create(NULL, TYPE_UNI_NORTH); 246 246 - qdev_init_nofail(dev); 245 245 + dev = qdev_new(TYPE_UNI_NORTH); 246 246 + qdev_realize_and_unref(dev, NULL, &error_fatal); 247 247 s = SYS_BUS_DEVICE(dev); 248 248 memory_region_add_subregion(get_system_memory(), 0xf8000000, 249 249 sysbus_mmio_get_region(s, 0)); ··· 288 288 } 289 289 } 290 290 291 291 - pic_dev = qdev_create(NULL, TYPE_OPENPIC); 291 291 + pic_dev = qdev_new(TYPE_OPENPIC); 292 292 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); 293 293 - qdev_init_nofail(pic_dev); 293 293 + qdev_realize_and_unref(pic_dev, NULL, &error_fatal); 294 294 s = SYS_BUS_DEVICE(pic_dev); 295 295 k = 0; 296 296 for (i = 0; i < smp_cpus; i++) { ··· 303 303 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 304 304 /* 970 gets a U3 bus */ 305 305 /* Uninorth AGP bus */ 306 306 - dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE); 306 306 + dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); 307 307 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 308 308 &error_abort); 309 309 - qdev_init_nofail(dev); 309 309 + qdev_realize_and_unref(dev, NULL, &error_fatal); 310 310 uninorth_pci = U3_AGP_HOST_BRIDGE(dev); 311 311 s = SYS_BUS_DEVICE(dev); 312 312 /* PCI hole */ ··· 322 322 } else { 323 323 /* Use values found on a real PowerMac */ 324 324 /* Uninorth AGP bus */ 325 325 - dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 325 325 + dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 326 326 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 327 327 &error_abort); 328 328 - qdev_init_nofail(dev); 328 328 + qdev_realize_and_unref(dev, NULL, &error_fatal); 329 329 s = SYS_BUS_DEVICE(dev); 330 330 sysbus_mmio_map(s, 0, 0xf0800000); 331 331 sysbus_mmio_map(s, 1, 0xf0c00000); 332 332 333 333 /* Uninorth internal bus */ 334 334 - dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 334 334 + dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 335 335 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 336 336 &error_abort); 337 337 - qdev_init_nofail(dev); 337 337 + qdev_realize_and_unref(dev, NULL, &error_fatal); 338 338 s = SYS_BUS_DEVICE(dev); 339 339 sysbus_mmio_map(s, 0, 0xf4800000); 340 340 sysbus_mmio_map(s, 1, 0xf4c00000); 341 341 342 342 /* Uninorth main bus */ 343 343 - dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 343 343 + dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 344 344 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000); 345 345 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 346 346 &error_abort); 347 347 - qdev_init_nofail(dev); 347 347 + qdev_realize_and_unref(dev, NULL, &error_fatal); 348 348 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); 349 349 s = SYS_BUS_DEVICE(dev); 350 350 /* PCI hole */ ··· 403 403 } 404 404 405 405 adb_bus = qdev_get_child_bus(dev, "adb.0"); 406 406 - dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 406 406 + dev = qdev_new(TYPE_ADB_KEYBOARD); 407 407 qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true); 408 408 - qdev_init_nofail(dev); 408 408 + qdev_realize_and_unref(dev, adb_bus, &error_fatal); 409 409 410 410 - dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 410 410 + dev = qdev_new(TYPE_ADB_MOUSE); 411 411 qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true); 412 412 - qdev_init_nofail(dev); 412 412 + qdev_realize_and_unref(dev, adb_bus, &error_fatal); 413 413 } 414 414 415 415 if (machine->usb) { ··· 441 441 move the NVRAM out of ROM again for KVM */ 442 442 nvram_addr = 0xFFE00000; 443 443 } 444 444 - dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 444 444 + dev = qdev_new(TYPE_MACIO_NVRAM); 445 445 qdev_prop_set_uint32(dev, "size", 0x2000); 446 446 qdev_prop_set_uint32(dev, "it_shift", 1); 447 447 - qdev_init_nofail(dev); 447 447 + qdev_realize_and_unref(dev, NULL, &error_fatal); 448 448 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 449 449 nvr = MACIO_NVRAM(dev); 450 450 pmac_format_nvram_partition(nvr, 0x2000); 451 451 /* No PCI init: the BIOS will do it */ 452 452 453 453 - dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 453 453 + dev = qdev_new(TYPE_FW_CFG_MEM); 454 454 fw_cfg = FW_CFG(dev); 455 455 qdev_prop_set_uint32(dev, "data_width", 1); 456 456 qdev_prop_set_bit(dev, "dma_enabled", false); 457 457 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 458 458 OBJECT(fw_cfg)); 459 459 - qdev_init_nofail(dev); 459 459 + qdev_realize_and_unref(dev, NULL, &error_fatal); 460 460 s = SYS_BUS_DEVICE(dev); 461 461 sysbus_mmio_map(s, 0, CFG_ADDR); 462 462 sysbus_mmio_map(s, 1, CFG_ADDR + 2);

+10 -10

hw/ppc/mac_oldworld.c

··· 222 222 } 223 223 224 224 /* XXX: we register only 1 output pin for heathrow PIC */ 225 225 - pic_dev = qdev_create(NULL, TYPE_HEATHROW); 226 226 - qdev_init_nofail(pic_dev); 225 225 + pic_dev = qdev_new(TYPE_HEATHROW); 226 226 + qdev_realize_and_unref(pic_dev, NULL, &error_fatal); 227 227 228 228 /* Connect the heathrow PIC outputs to the 6xx bus */ 229 229 for (i = 0; i < smp_cpus; i++) { ··· 252 252 } 253 253 254 254 /* Grackle PCI host bridge */ 255 255 - dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE); 255 255 + dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 256 256 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 257 257 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 258 258 &error_abort); 259 259 - qdev_init_nofail(dev); 259 259 + qdev_realize_and_unref(dev, NULL, &error_fatal); 260 260 s = SYS_BUS_DEVICE(dev); 261 261 sysbus_mmio_map(s, 0, GRACKLE_BASE); 262 262 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); ··· 295 295 296 296 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 297 297 adb_bus = qdev_get_child_bus(dev, "adb.0"); 298 298 - dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 299 299 - qdev_init_nofail(dev); 300 300 - dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 301 301 - qdev_init_nofail(dev); 298 298 + dev = qdev_new(TYPE_ADB_KEYBOARD); 299 299 + qdev_realize_and_unref(dev, adb_bus, &error_fatal); 300 300 + dev = qdev_new(TYPE_ADB_MOUSE); 301 301 + qdev_realize_and_unref(dev, adb_bus, &error_fatal); 302 302 303 303 if (machine_usb(machine)) { 304 304 pci_create_simple(pci_bus, -1, "pci-ohci"); ··· 309 309 310 310 /* No PCI init: the BIOS will do it */ 311 311 312 312 - dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 312 312 + dev = qdev_new(TYPE_FW_CFG_MEM); 313 313 fw_cfg = FW_CFG(dev); 314 314 qdev_prop_set_uint32(dev, "data_width", 1); 315 315 qdev_prop_set_bit(dev, "dma_enabled", false); 316 316 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 317 317 OBJECT(fw_cfg)); 318 318 - qdev_init_nofail(dev); 318 318 + qdev_realize_and_unref(dev, NULL, &error_fatal); 319 319 s = SYS_BUS_DEVICE(dev); 320 320 sysbus_mmio_map(s, 0, CFG_ADDR); 321 321 sysbus_mmio_map(s, 1, CFG_ADDR + 2);

+2 -2

hw/ppc/pnv.c

··· 729 729 /* 730 730 * Create our simple PNOR device 731 731 */ 732 732 - dev = qdev_create(NULL, TYPE_PNV_PNOR); 732 732 + dev = qdev_new(TYPE_PNV_PNOR); 733 733 if (pnor) { 734 734 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 735 735 &error_abort); 736 736 } 737 737 - qdev_init_nofail(dev); 737 737 + qdev_realize_and_unref(dev, NULL, &error_fatal); 738 738 pnv->pnor = PNV_PNOR(dev); 739 739 740 740 /* load skiboot firmware */

+4 -4

hw/ppc/ppc440_uc.c

··· 1367 1367 { 1368 1368 DeviceState *dev; 1369 1369 1370 1370 - dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); 1370 1370 + dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1371 1371 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE); 1372 1372 - qdev_init_nofail(dev); 1372 1372 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1373 1373 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1374 1374 1375 1375 - dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); 1375 1375 + dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1376 1376 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE); 1377 1377 - qdev_init_nofail(dev); 1377 1377 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1378 1378 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1379 1379 }

+5 -4

hw/ppc/prep.c

··· 35 35 #include "hw/pci/pci_host.h" 36 36 #include "hw/ppc/ppc.h" 37 37 #include "hw/boards.h" 38 38 + #include "qapi/error.h" 38 39 #include "qemu/error-report.h" 39 40 #include "qemu/log.h" 40 41 #include "hw/irq.h" ··· 268 269 qemu_register_reset(ppc_prep_reset, cpu); 269 270 270 271 /* PCI host */ 271 271 - dev = qdev_create(NULL, "raven-pcihost"); 272 272 + dev = qdev_new("raven-pcihost"); 272 273 if (!bios_name) { 273 274 bios_name = "openbios-ppc"; 274 275 } ··· 276 277 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 277 278 pcihost = SYS_BUS_DEVICE(dev); 278 279 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev)); 279 279 - qdev_init_nofail(dev); 280 280 + qdev_realize_and_unref(dev, NULL, &error_fatal); 280 281 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 281 282 if (!pci_bus) { 282 283 error_report("could not create PCI host controller"); ··· 338 339 } 339 340 340 341 /* Prepare firmware configuration for OpenBIOS */ 341 341 - dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 342 342 + dev = qdev_new(TYPE_FW_CFG_MEM); 342 343 fw_cfg = FW_CFG(dev); 343 344 qdev_prop_set_uint32(dev, "data_width", 1); 344 345 qdev_prop_set_bit(dev, "dma_enabled", false); 345 346 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 346 347 OBJECT(fw_cfg)); 347 347 - qdev_init_nofail(dev); 348 348 + qdev_realize_and_unref(dev, NULL, &error_fatal); 348 349 s = SYS_BUS_DEVICE(dev); 349 350 sysbus_mmio_map(s, 0, CFG_ADDR); 350 351 sysbus_mmio_map(s, 1, CFG_ADDR + 2);

+2 -2

hw/ppc/sam460ex.c

··· 370 370 371 371 /* USB */ 372 372 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]); 373 373 - dev = qdev_create(NULL, "sysbus-ohci"); 373 373 + dev = qdev_new("sysbus-ohci"); 374 374 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 375 375 qdev_prop_set_uint32(dev, "num-ports", 6); 376 376 - qdev_init_nofail(dev); 376 376 + qdev_realize_and_unref(dev, NULL, &error_fatal); 377 377 sbdev = SYS_BUS_DEVICE(dev); 378 378 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 379 379 sysbus_connect_irq(sbdev, 0, uic[2][30]);

+4 -4

hw/ppc/spapr.c

··· 1712 1712 1713 1713 static void spapr_create_nvram(SpaprMachineState *spapr) 1714 1714 { 1715 1715 - DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1715 1715 + DeviceState *dev = qdev_new("spapr-nvram"); 1716 1716 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1717 1717 1718 1718 if (dinfo) { ··· 1720 1720 &error_fatal); 1721 1721 } 1722 1722 1723 1723 - qdev_init_nofail(dev); 1723 1723 + qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1724 1724 1725 1725 spapr->nvram = (struct SpaprNvram *)dev; 1726 1726 } ··· 2640 2640 { 2641 2641 DeviceState *dev; 2642 2642 2643 2643 - dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); 2643 2643 + dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2644 2644 qdev_prop_set_uint32(dev, "index", 0); 2645 2645 - qdev_init_nofail(dev); 2645 2645 + qdev_realize_and_unref(dev, NULL, &error_fatal); 2646 2646 2647 2647 return PCI_HOST_BRIDGE(dev); 2648 2648 }

+2 -2

hw/ppc/spapr_irq.c

··· 325 325 DeviceState *dev; 326 326 int i; 327 327 328 328 - dev = qdev_create(NULL, TYPE_SPAPR_XIVE); 328 328 + dev = qdev_new(TYPE_SPAPR_XIVE); 329 329 qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_XIRQ_BASE); 330 330 /* 331 331 * 8 XIVE END structures per CPU. One for each available ··· 334 334 qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); 335 335 object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric", 336 336 &error_abort); 337 337 - qdev_init_nofail(dev); 337 337 + qdev_realize_and_unref(dev, NULL, &error_fatal); 338 338 339 339 spapr->xive = SPAPR_XIVE(dev); 340 340

+2 -2

hw/ppc/spapr_vio.c

··· 576 576 DeviceState *dev; 577 577 578 578 /* Create bridge device */ 579 579 - dev = qdev_create(NULL, TYPE_SPAPR_VIO_BRIDGE); 580 580 - qdev_init_nofail(dev); 579 579 + dev = qdev_new(TYPE_SPAPR_VIO_BRIDGE); 580 580 + qdev_realize_and_unref(dev, NULL, &error_fatal); 581 581 582 582 /* Create bus on bridge device */ 583 583 qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");

+5 -4

hw/ppc/virtex_ml507.c

··· 36 36 #include "sysemu/device_tree.h" 37 37 #include "hw/loader.h" 38 38 #include "elf.h" 39 39 + #include "qapi/error.h" 39 40 #include "qemu/error-report.h" 40 41 #include "qemu/log.h" 41 42 #include "qemu/option.h" ··· 228 229 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); 229 230 230 231 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; 231 231 - dev = qdev_create(NULL, "xlnx.xps-intc"); 232 232 + dev = qdev_new("xlnx.xps-intc"); 232 233 qdev_prop_set_uint32(dev, "kind-of-intr", 0); 233 233 - qdev_init_nofail(dev); 234 234 + qdev_realize_and_unref(dev, NULL, &error_fatal); 234 235 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 235 236 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); 236 237 for (i = 0; i < 32; i++) { ··· 241 242 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 242 243 243 244 /* 2 timers at irq 2 @ 62 Mhz. */ 244 244 - dev = qdev_create(NULL, "xlnx.xps-timer"); 245 245 + dev = qdev_new("xlnx.xps-timer"); 245 246 qdev_prop_set_uint32(dev, "one-timer-only", 0); 246 247 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); 247 247 - qdev_init_nofail(dev); 248 248 + qdev_realize_and_unref(dev, NULL, &error_fatal); 248 249 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 249 250 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 250 251

+3 -2

hw/riscv/sifive_clint.c

··· 20 20 */ 21 21 22 22 #include "qemu/osdep.h" 23 23 + #include "qapi/error.h" 23 24 #include "qemu/error-report.h" 24 25 #include "qemu/module.h" 25 26 #include "hw/sysbus.h" ··· 245 246 env->timecmp = 0; 246 247 } 247 248 248 248 - DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_CLINT); 249 249 + DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT); 249 250 qdev_prop_set_uint32(dev, "num-harts", num_harts); 250 251 qdev_prop_set_uint32(dev, "sip-base", sip_base); 251 252 qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); 252 253 qdev_prop_set_uint32(dev, "time-base", time_base); 253 254 qdev_prop_set_uint32(dev, "aperture-size", size); 254 254 - qdev_init_nofail(dev); 255 255 + qdev_realize_and_unref(dev, NULL, &error_fatal); 255 256 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 256 257 return dev; 257 258 }

+3 -2

hw/riscv/sifive_e_prci.c

··· 20 20 21 21 #include "qemu/osdep.h" 22 22 #include "hw/sysbus.h" 23 23 + #include "qapi/error.h" 23 24 #include "qemu/log.h" 24 25 #include "qemu/module.h" 25 26 #include "hw/hw.h" ··· 117 118 */ 118 119 DeviceState *sifive_e_prci_create(hwaddr addr) 119 120 { 120 120 - DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI); 121 121 - qdev_init_nofail(dev); 121 121 + DeviceState *dev = qdev_new(TYPE_SIFIVE_E_PRCI); 122 122 + qdev_realize_and_unref(dev, NULL, &error_fatal); 122 123 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 123 124 return dev; 124 125 }

+3 -2

hw/riscv/sifive_plic.c

··· 19 19 */ 20 20 21 21 #include "qemu/osdep.h" 22 22 + #include "qapi/error.h" 22 23 #include "qemu/log.h" 23 24 #include "qemu/module.h" 24 25 #include "qemu/error-report.h" ··· 494 495 uint32_t context_base, uint32_t context_stride, 495 496 uint32_t aperture_size) 496 497 { 497 497 - DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PLIC); 498 498 + DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC); 498 499 assert(enable_stride == (enable_stride & -enable_stride)); 499 500 assert(context_stride == (context_stride & -context_stride)); 500 501 qdev_prop_set_string(dev, "hart-config", hart_config); ··· 507 508 qdev_prop_set_uint32(dev, "context-base", context_base); 508 509 qdev_prop_set_uint32(dev, "context-stride", context_stride); 509 510 qdev_prop_set_uint32(dev, "aperture-size", aperture_size); 510 510 - qdev_init_nofail(dev); 511 511 + qdev_realize_and_unref(dev, NULL, &error_fatal); 511 512 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 512 513 return dev; 513 514 }

+3 -2

hw/riscv/sifive_test.c

··· 20 20 21 21 #include "qemu/osdep.h" 22 22 #include "hw/sysbus.h" 23 23 + #include "qapi/error.h" 23 24 #include "qemu/log.h" 24 25 #include "qemu/module.h" 25 26 #include "sysemu/runstate.h" ··· 92 93 */ 93 94 DeviceState *sifive_test_create(hwaddr addr) 94 95 { 95 95 - DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_TEST); 96 96 - qdev_init_nofail(dev); 96 96 + DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST); 97 97 + qdev_realize_and_unref(dev, NULL, &error_fatal); 97 98 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 98 99 return dev; 99 100 }

+2 -2

hw/riscv/virt.c

··· 443 443 qemu_irq irq; 444 444 int i; 445 445 446 446 - dev = qdev_create(NULL, TYPE_GPEX_HOST); 446 446 + dev = qdev_new(TYPE_GPEX_HOST); 447 447 448 448 - qdev_init_nofail(dev); 448 448 + qdev_realize_and_unref(dev, NULL, &error_fatal); 449 449 450 450 ecam_alias = g_new0(MemoryRegion, 1); 451 451 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

+3 -2

hw/rtc/m48t59.c

··· 33 33 #include "sysemu/sysemu.h" 34 34 #include "hw/sysbus.h" 35 35 #include "exec/address-spaces.h" 36 36 + #include "qapi/error.h" 36 37 #include "qemu/bcd.h" 37 38 #include "qemu/module.h" 38 39 #include "trace.h" ··· 579 580 continue; 580 581 } 581 582 582 582 - dev = qdev_create(NULL, m48txx_sysbus_info[i].bus_name); 583 583 + dev = qdev_new(m48txx_sysbus_info[i].bus_name); 583 584 qdev_prop_set_int32(dev, "base-year", base_year); 584 584 - qdev_init_nofail(dev); 585 585 + qdev_realize_and_unref(dev, NULL, &error_fatal); 585 586 s = SYS_BUS_DEVICE(dev); 586 587 sysbus_connect_irq(s, 0, IRQ); 587 588 if (io_base != 0) {

+3 -2

hw/rtc/sun4v-rtc.c

··· 11 11 12 12 #include "qemu/osdep.h" 13 13 #include "hw/sysbus.h" 14 14 + #include "qapi/error.h" 14 15 #include "qemu/module.h" 15 16 #include "qemu/timer.h" 16 17 #include "hw/rtc/sun4v-rtc.h" ··· 55 56 DeviceState *dev; 56 57 SysBusDevice *s; 57 58 58 58 - dev = qdev_create(NULL, TYPE_SUN4V_RTC); 59 59 + dev = qdev_new(TYPE_SUN4V_RTC); 59 60 s = SYS_BUS_DEVICE(dev); 60 61 61 61 - qdev_init_nofail(dev); 62 62 + qdev_realize_and_unref(dev, NULL, &error_fatal); 62 63 63 64 sysbus_mmio_map(s, 0, addr); 64 65 }

+2 -2

hw/s390x/ap-bridge.c

··· 49 49 } 50 50 51 51 /* Create bridge device */ 52 52 - dev = qdev_create(NULL, TYPE_AP_BRIDGE); 52 52 + dev = qdev_new(TYPE_AP_BRIDGE); 53 53 object_property_add_child(qdev_get_machine(), TYPE_AP_BRIDGE, 54 54 OBJECT(dev)); 55 55 - qdev_init_nofail(dev); 55 55 + qdev_realize_and_unref(dev, NULL, &error_fatal); 56 56 57 57 /* Create bus on bridge device */ 58 58 bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS);

+2 -2

hw/s390x/css-bridge.c

··· 101 101 DeviceState *dev; 102 102 103 103 /* Create bridge device */ 104 104 - dev = qdev_create(NULL, TYPE_VIRTUAL_CSS_BRIDGE); 104 104 + dev = qdev_new(TYPE_VIRTUAL_CSS_BRIDGE); 105 105 object_property_add_child(qdev_get_machine(), TYPE_VIRTUAL_CSS_BRIDGE, 106 106 OBJECT(dev)); 107 107 - qdev_init_nofail(dev); 107 107 + qdev_realize_and_unref(dev, NULL, &error_fatal); 108 108 109 109 /* Create bus on bridge device */ 110 110 bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");

+6 -6

hw/s390x/s390-virtio-ccw.c

··· 227 227 228 228 qemu_check_nic_model(nd, "virtio"); 229 229 230 230 - dev = qdev_create(bus, name); 230 230 + dev = qdev_new(name); 231 231 qdev_set_nic_properties(dev, nd); 232 232 - qdev_init_nofail(dev); 232 232 + qdev_realize_and_unref(dev, bus, &error_fatal); 233 233 } 234 234 } 235 235 ··· 237 237 { 238 238 DeviceState *dev; 239 239 240 240 - dev = qdev_create(sclp_get_event_facility_bus(), type); 240 240 + dev = qdev_new(type); 241 241 qdev_prop_set_chr(dev, "chardev", chardev); 242 242 - qdev_init_nofail(dev); 242 242 + qdev_realize_and_unref(dev, sclp_get_event_facility_bus(), &error_fatal); 243 243 } 244 244 245 245 static void ccw_init(MachineState *machine) ··· 269 269 machine->initrd_filename, "s390-ccw.img", 270 270 "s390-netboot.img", true); 271 271 272 272 - dev = qdev_create(NULL, TYPE_S390_PCI_HOST_BRIDGE); 272 272 + dev = qdev_new(TYPE_S390_PCI_HOST_BRIDGE); 273 273 object_property_add_child(qdev_get_machine(), TYPE_S390_PCI_HOST_BRIDGE, 274 274 OBJECT(dev)); 275 275 - qdev_init_nofail(dev); 275 275 + qdev_realize_and_unref(dev, NULL, &error_fatal); 276 276 277 277 /* register hypercalls */ 278 278 virtio_ccw_register_hcalls();

+2 -2

hw/scsi/scsi-bus.c

··· 261 261 driver = "scsi-hd"; 262 262 } 263 263 } 264 264 - dev = qdev_create(&bus->qbus, driver); 264 264 + dev = qdev_new(driver); 265 265 name = g_strdup_printf("legacy[%d]", unit); 266 266 object_property_add_child(OBJECT(bus), name, OBJECT(dev)); 267 267 g_free(name); ··· 293 293 qdev_prop_set_enum(dev, "rerror", rerror); 294 294 qdev_prop_set_enum(dev, "werror", werror); 295 295 296 296 - object_property_set_bool(OBJECT(dev), true, "realized", &err); 296 296 + qdev_realize_and_unref(dev, &bus->qbus, &err); 297 297 if (err != NULL) { 298 298 error_propagate(errp, err); 299 299 object_unparent(OBJECT(dev));

+2 -2

hw/scsi/spapr_vscsi.c

··· 1225 1225 { 1226 1226 DeviceState *dev; 1227 1227 1228 1228 - dev = qdev_create(&bus->bus, "spapr-vscsi"); 1228 1228 + dev = qdev_new("spapr-vscsi"); 1229 1229 1230 1230 - qdev_init_nofail(dev); 1230 1230 + qdev_realize_and_unref(dev, &bus->bus, &error_fatal); 1231 1231 scsi_bus_legacy_handle_cmdline(&VIO_SPAPR_VSCSI_DEVICE(dev)->bus); 1232 1232 } 1233 1233

+2 -2

hw/sd/milkymist-memcard.c

··· 278 278 /* FIXME use a qdev drive property instead of drive_get_next() */ 279 279 dinfo = drive_get_next(IF_SD); 280 280 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 281 281 - carddev = qdev_create(BUS(&s->sdbus), TYPE_SD_CARD); 281 281 + carddev = qdev_new(TYPE_SD_CARD); 282 282 qdev_prop_set_drive(carddev, "drive", blk, &err); 283 283 - object_property_set_bool(OBJECT(carddev), true, "realized", &err); 283 283 + qdev_realize_and_unref(carddev, BUS(&s->sdbus), &err); 284 284 if (err) { 285 285 error_setg(errp, "failed to init SD card: %s", error_get_pretty(err)); 286 286 return;

+4 -4

hw/sd/pxa2xx_mmci.c

··· 485 485 PXA2xxMMCIState *s; 486 486 Error *err = NULL; 487 487 488 488 - dev = qdev_create(NULL, TYPE_PXA2XX_MMCI); 488 488 + dev = qdev_new(TYPE_PXA2XX_MMCI); 489 489 s = PXA2XX_MMCI(dev); 490 490 sbd = SYS_BUS_DEVICE(dev); 491 491 sysbus_mmio_map(sbd, 0, base); 492 492 sysbus_connect_irq(sbd, 0, irq); 493 493 qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma); 494 494 qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma); 495 495 - qdev_init_nofail(dev); 495 495 + qdev_realize_and_unref(dev, NULL, &error_fatal); 496 496 497 497 /* Create and plug in the sd card */ 498 498 - carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); 498 498 + carddev = qdev_new(TYPE_SD_CARD); 499 499 qdev_prop_set_drive(carddev, "drive", blk, &err); 500 500 if (err) { 501 501 error_reportf_err(err, "failed to init SD card: "); 502 502 return NULL; 503 503 } 504 504 - object_property_set_bool(OBJECT(carddev), true, "realized", &err); 504 504 + qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), &err); 505 505 if (err) { 506 506 error_reportf_err(err, "failed to init SD card: "); 507 507 return NULL;

+2 -2

hw/sd/ssi-sd.c

··· 252 252 /* Create and plug in the sd card */ 253 253 /* FIXME use a qdev drive property instead of drive_get_next() */ 254 254 dinfo = drive_get_next(IF_SD); 255 255 - carddev = qdev_create(BUS(&s->sdbus), TYPE_SD_CARD); 255 255 + carddev = qdev_new(TYPE_SD_CARD); 256 256 if (dinfo) { 257 257 qdev_prop_set_drive(carddev, "drive", blk_by_legacy_dinfo(dinfo), &err); 258 258 if (err) { ··· 265 265 goto fail; 266 266 } 267 267 268 268 - object_property_set_bool(OBJECT(carddev), true, "realized", &err); 268 268 + qdev_realize_and_unref(carddev, BUS(&s->sdbus), &err); 269 269 if (err) { 270 270 goto fail; 271 271 }

+6 -6

hw/sh4/r2d.c

··· 257 257 s = sh7750_init(cpu, address_space_mem); 258 258 irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); 259 259 260 260 - dev = qdev_create(NULL, "sh_pci"); 260 260 + dev = qdev_new("sh_pci"); 261 261 busdev = SYS_BUS_DEVICE(dev); 262 262 - qdev_init_nofail(dev); 262 262 + qdev_realize_and_unref(dev, NULL, &error_fatal); 263 263 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); 264 264 sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000)); 265 265 sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000)); ··· 268 268 sysbus_connect_irq(busdev, 2, irq[PCI_INTC]); 269 269 sysbus_connect_irq(busdev, 3, irq[PCI_INTD]); 270 270 271 271 - dev = qdev_create(NULL, "sysbus-sm501"); 271 271 + dev = qdev_new("sysbus-sm501"); 272 272 busdev = SYS_BUS_DEVICE(dev); 273 273 qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE); 274 274 qdev_prop_set_uint32(dev, "base", 0x10000000); 275 275 qdev_prop_set_chr(dev, "chardev", serial_hd(2)); 276 276 - qdev_init_nofail(dev); 276 276 + qdev_realize_and_unref(dev, NULL, &error_fatal); 277 277 sysbus_mmio_map(busdev, 0, 0x10000000); 278 278 sysbus_mmio_map(busdev, 1, 0x13e00000); 279 279 sysbus_connect_irq(busdev, 0, irq[SM501]); 280 280 281 281 /* onboard CF (True IDE mode, Master only). */ 282 282 dinfo = drive_get(IF_IDE, 0, 0); 283 283 - dev = qdev_create(NULL, "mmio-ide"); 283 283 + dev = qdev_new("mmio-ide"); 284 284 busdev = SYS_BUS_DEVICE(dev); 285 285 sysbus_connect_irq(busdev, 0, irq[CF_IDE]); 286 286 qdev_prop_set_uint32(dev, "shift", 1); 287 287 - qdev_init_nofail(dev); 287 287 + qdev_realize_and_unref(dev, NULL, &error_fatal); 288 288 sysbus_mmio_map(busdev, 0, 0x14001000); 289 289 sysbus_mmio_map(busdev, 1, 0x1400080c); 290 290 mmio_ide_init_drives(dev, dinfo, NULL);

+6 -6

hw/sparc/leon3.c

··· 228 228 GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA); 229 229 230 230 /* Allocate IRQ manager */ 231 231 - dev = qdev_create(NULL, TYPE_GRLIB_IRQMP); 231 231 + dev = qdev_new(TYPE_GRLIB_IRQMP); 232 232 qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in, 233 233 env, "pil", 1); 234 234 qdev_connect_gpio_out_named(dev, "grlib-irq", 0, 235 235 qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0)); 236 236 - qdev_init_nofail(dev); 236 236 + qdev_realize_and_unref(dev, NULL, &error_fatal); 237 237 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET); 238 238 env->irq_manager = dev; 239 239 env->qemu_irq_ack = leon3_irq_manager; ··· 322 322 } 323 323 324 324 /* Allocate timers */ 325 325 - dev = qdev_create(NULL, TYPE_GRLIB_GPTIMER); 325 325 + dev = qdev_new(TYPE_GRLIB_GPTIMER); 326 326 qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT); 327 327 qdev_prop_set_uint32(dev, "frequency", CPU_CLK); 328 328 qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ); 329 329 - qdev_init_nofail(dev); 329 329 + qdev_realize_and_unref(dev, NULL, &error_fatal); 330 330 331 331 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET); 332 332 for (i = 0; i < LEON3_TIMER_COUNT; i++) { ··· 339 339 0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA); 340 340 341 341 /* Allocate uart */ 342 342 - dev = qdev_create(NULL, TYPE_GRLIB_APB_UART); 342 342 + dev = qdev_new(TYPE_GRLIB_APB_UART); 343 343 qdev_prop_set_chr(dev, "chrdev", serial_hd(0)); 344 344 - qdev_init_nofail(dev); 344 344 + qdev_realize_and_unref(dev, NULL, &error_fatal); 345 345 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET); 346 346 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]); 347 347 grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,

+32 -32

hw/sparc/sun4m.c

··· 316 316 DeviceState *dev; 317 317 SysBusDevice *s; 318 318 319 319 - dev = qdev_create(NULL, TYPE_SUN4M_IOMMU); 319 319 + dev = qdev_new(TYPE_SUN4M_IOMMU); 320 320 qdev_prop_set_uint32(dev, "version", version); 321 321 - qdev_init_nofail(dev); 321 321 + qdev_realize_and_unref(dev, NULL, &error_fatal); 322 322 s = SYS_BUS_DEVICE(dev); 323 323 sysbus_connect_irq(s, 0, irq); 324 324 sysbus_mmio_map(s, 0, addr); ··· 336 336 SysBusESPState *esp; 337 337 SysBusPCNetState *lance; 338 338 339 339 - dma = qdev_create(NULL, TYPE_SPARC32_DMA); 340 340 - qdev_init_nofail(dma); 339 339 + dma = qdev_new(TYPE_SPARC32_DMA); 340 340 + qdev_realize_and_unref(dma, NULL, &error_fatal); 341 341 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 342 342 343 343 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( ··· 367 367 SysBusDevice *s; 368 368 unsigned int i, j; 369 369 370 370 - dev = qdev_create(NULL, "slavio_intctl"); 371 371 - qdev_init_nofail(dev); 370 370 + dev = qdev_new("slavio_intctl"); 371 371 + qdev_realize_and_unref(dev, NULL, &error_fatal); 372 372 373 373 s = SYS_BUS_DEVICE(dev); 374 374 ··· 395 395 SysBusDevice *s; 396 396 unsigned int i; 397 397 398 398 - dev = qdev_create(NULL, "slavio_timer"); 398 398 + dev = qdev_new("slavio_timer"); 399 399 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 400 400 - qdev_init_nofail(dev); 400 400 + qdev_realize_and_unref(dev, NULL, &error_fatal); 401 401 s = SYS_BUS_DEVICE(dev); 402 402 sysbus_connect_irq(s, 0, master_irq); 403 403 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); ··· 433 433 DeviceState *dev; 434 434 SysBusDevice *s; 435 435 436 436 - dev = qdev_create(NULL, "slavio_misc"); 437 437 - qdev_init_nofail(dev); 436 436 + dev = qdev_new("slavio_misc"); 437 437 + qdev_realize_and_unref(dev, NULL, &error_fatal); 438 438 s = SYS_BUS_DEVICE(dev); 439 439 if (base) { 440 440 /* 8 bit registers */ ··· 470 470 DeviceState *dev; 471 471 SysBusDevice *s; 472 472 473 473 - dev = qdev_create(NULL, "eccmemctl"); 473 473 + dev = qdev_new("eccmemctl"); 474 474 qdev_prop_set_uint32(dev, "version", version); 475 475 - qdev_init_nofail(dev); 475 475 + qdev_realize_and_unref(dev, NULL, &error_fatal); 476 476 s = SYS_BUS_DEVICE(dev); 477 477 sysbus_connect_irq(s, 0, irq); 478 478 sysbus_mmio_map(s, 0, base); ··· 486 486 DeviceState *dev; 487 487 SysBusDevice *s; 488 488 489 489 - dev = qdev_create(NULL, "apc"); 490 490 - qdev_init_nofail(dev); 489 489 + dev = qdev_new("apc"); 490 490 + qdev_realize_and_unref(dev, NULL, &error_fatal); 491 491 s = SYS_BUS_DEVICE(dev); 492 492 /* Power management (APC) XXX: not a Slavio device */ 493 493 sysbus_mmio_map(s, 0, power_base); ··· 500 500 DeviceState *dev; 501 501 SysBusDevice *s; 502 502 503 503 - dev = qdev_create(NULL, "SUNW,tcx"); 503 503 + dev = qdev_new("SUNW,tcx"); 504 504 qdev_prop_set_uint32(dev, "vram_size", vram_size); 505 505 qdev_prop_set_uint16(dev, "width", width); 506 506 qdev_prop_set_uint16(dev, "height", height); 507 507 qdev_prop_set_uint16(dev, "depth", depth); 508 508 - qdev_init_nofail(dev); 508 508 + qdev_realize_and_unref(dev, NULL, &error_fatal); 509 509 s = SYS_BUS_DEVICE(dev); 510 510 511 511 /* 10/ROM : FCode ROM */ ··· 552 552 DeviceState *dev; 553 553 SysBusDevice *s; 554 554 555 555 - dev = qdev_create(NULL, "cgthree"); 555 555 + dev = qdev_new("cgthree"); 556 556 qdev_prop_set_uint32(dev, "vram-size", vram_size); 557 557 qdev_prop_set_uint16(dev, "width", width); 558 558 qdev_prop_set_uint16(dev, "height", height); 559 559 qdev_prop_set_uint16(dev, "depth", depth); 560 560 - qdev_init_nofail(dev); 560 560 + qdev_realize_and_unref(dev, NULL, &error_fatal); 561 561 s = SYS_BUS_DEVICE(dev); 562 562 563 563 /* FCode ROM */ ··· 581 581 DeviceState *dev; 582 582 SysBusDevice *s; 583 583 584 584 - dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); 585 585 - qdev_init_nofail(dev); 584 584 + dev = qdev_new(TYPE_MACIO_ID_REGISTER); 585 585 + qdev_realize_and_unref(dev, NULL, &error_fatal); 586 586 s = SYS_BUS_DEVICE(dev); 587 587 588 588 sysbus_mmio_map(s, 0, addr); ··· 647 647 DeviceState *dev; 648 648 SysBusDevice *s; 649 649 650 650 - dev = qdev_create(NULL, TYPE_TCX_AFX); 651 651 - qdev_init_nofail(dev); 650 650 + dev = qdev_new(TYPE_TCX_AFX); 651 651 + qdev_realize_and_unref(dev, NULL, &error_fatal); 652 652 s = SYS_BUS_DEVICE(dev); 653 653 654 654 sysbus_mmio_map(s, 0, addr); ··· 708 708 char *filename; 709 709 int ret; 710 710 711 711 - dev = qdev_create(NULL, TYPE_OPENPROM); 712 712 - qdev_init_nofail(dev); 711 711 + dev = qdev_new(TYPE_OPENPROM); 712 712 + qdev_realize_and_unref(dev, NULL, &error_fatal); 713 713 s = SYS_BUS_DEVICE(dev); 714 714 715 715 sysbus_mmio_map(s, 0, addr); ··· 877 877 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 878 878 879 879 /* Create and map RAM frontend */ 880 880 - dev = qdev_create(NULL, "memory"); 880 880 + dev = qdev_new("memory"); 881 881 object_property_set_link(OBJECT(dev), ram_memdev, "memdev", &error_fatal); 882 882 - qdev_init_nofail(dev); 882 882 + qdev_realize_and_unref(dev, NULL, &error_fatal); 883 883 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 884 884 885 885 /* models without ECC don't trap when missing ram is accessed */ ··· 982 982 983 983 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 984 984 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 985 985 - dev = qdev_create(NULL, TYPE_ESCC); 985 985 + dev = qdev_new(TYPE_ESCC); 986 986 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 987 987 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 988 988 qdev_prop_set_uint32(dev, "it_shift", 1); ··· 990 990 qdev_prop_set_chr(dev, "chrA", NULL); 991 991 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 992 992 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 993 993 - qdev_init_nofail(dev); 993 993 + qdev_realize_and_unref(dev, NULL, &error_fatal); 994 994 s = SYS_BUS_DEVICE(dev); 995 995 sysbus_connect_irq(s, 0, slavio_irq[14]); 996 996 sysbus_connect_irq(s, 1, slavio_irq[14]); 997 997 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 998 998 999 999 - dev = qdev_create(NULL, TYPE_ESCC); 999 999 + dev = qdev_new(TYPE_ESCC); 1000 1000 qdev_prop_set_uint32(dev, "disabled", 0); 1001 1001 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 1002 1002 qdev_prop_set_uint32(dev, "it_shift", 1); ··· 1004 1004 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 1005 1005 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 1006 1006 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 1007 1007 - qdev_init_nofail(dev); 1007 1007 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1008 1008 1009 1009 s = SYS_BUS_DEVICE(dev); 1010 1010 sysbus_connect_irq(s, 0, slavio_irq[15]); ··· 1062 1062 ecc_init(hwdef->ecc_base, slavio_irq[28], 1063 1063 hwdef->ecc_version); 1064 1064 1065 1065 - dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 1065 1065 + dev = qdev_new(TYPE_FW_CFG_MEM); 1066 1066 fw_cfg = FW_CFG(dev); 1067 1067 qdev_prop_set_uint32(dev, "data_width", 1); 1068 1068 qdev_prop_set_bit(dev, "dma_enabled", false); 1069 1069 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1070 1070 OBJECT(fw_cfg)); 1071 1071 - qdev_init_nofail(dev); 1071 1071 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1072 1072 s = SYS_BUS_DEVICE(dev); 1073 1073 sysbus_mmio_map(s, 0, CFG_ADDR); 1074 1074 sysbus_mmio_map(s, 1, CFG_ADDR + 2);

+12 -12

hw/sparc64/sun4u.c

··· 351 351 qdev_init_nofail(dev); 352 352 353 353 /* Power */ 354 354 - dev = qdev_create(NULL, TYPE_SUN4U_POWER); 355 355 - qdev_init_nofail(dev); 354 354 + dev = qdev_new(TYPE_SUN4U_POWER); 355 355 + qdev_realize_and_unref(dev, NULL, &error_fatal); 356 356 sbd = SYS_BUS_DEVICE(dev); 357 357 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, 358 358 sysbus_mmio_get_region(sbd, 0)); ··· 426 426 char *filename; 427 427 int ret; 428 428 429 429 - dev = qdev_create(NULL, TYPE_OPENPROM); 430 430 - qdev_init_nofail(dev); 429 429 + dev = qdev_new(TYPE_OPENPROM); 430 430 + qdev_realize_and_unref(dev, NULL, &error_fatal); 431 431 s = SYS_BUS_DEVICE(dev); 432 432 433 433 sysbus_mmio_map(s, 0, addr); ··· 520 520 RamDevice *d; 521 521 522 522 /* allocate RAM */ 523 523 - dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 523 523 + dev = qdev_new(TYPE_SUN4U_MEMORY); 524 524 s = SYS_BUS_DEVICE(dev); 525 525 526 526 d = SUN4U_RAM(dev); 527 527 d->size = RAM_size; 528 528 - qdev_init_nofail(dev); 528 528 + qdev_realize_and_unref(dev, NULL, &error_fatal); 529 529 530 530 sysbus_mmio_map(s, 0, addr); 531 531 } ··· 572 572 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 573 573 574 574 /* IOMMU */ 575 575 - iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); 576 576 - qdev_init_nofail(iommu); 575 575 + iommu = qdev_new(TYPE_SUN4U_IOMMU); 576 576 + qdev_realize_and_unref(iommu, NULL, &error_fatal); 577 577 578 578 /* set up devices */ 579 579 ram_init(0, machine->ram_size); ··· 581 581 prom_init(hwdef->prom_addr, bios_name); 582 582 583 583 /* Init sabre (PCI host bridge) */ 584 584 - sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); 584 584 + sabre = SABRE_DEVICE(qdev_new(TYPE_SABRE)); 585 585 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); 586 586 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); 587 587 object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", 588 588 &error_abort); 589 589 - qdev_init_nofail(DEVICE(sabre)); 589 589 + qdev_realize_and_unref(DEVICE(sabre), NULL, &error_fatal); 590 590 591 591 /* Wire up PCI interrupts to CPU */ 592 592 for (i = 0; i < IVEC_MAX; i++) { ··· 689 689 graphic_width, graphic_height, graphic_depth, 690 690 (uint8_t *)&macaddr); 691 691 692 692 - dev = qdev_create(NULL, TYPE_FW_CFG_IO); 692 692 + dev = qdev_new(TYPE_FW_CFG_IO); 693 693 qdev_prop_set_bit(dev, "dma_enabled", false); 694 694 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev)); 695 695 - qdev_init_nofail(dev); 695 695 + qdev_realize_and_unref(dev, NULL, &error_fatal); 696 696 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 697 697 &FW_CFG_IO(dev)->comb_iomem); 698 698

+2 -2

hw/xen/xen-bus.c

··· 1387 1387 1388 1388 void xen_bus_init(void) 1389 1389 { 1390 1390 - DeviceState *dev = qdev_create(NULL, TYPE_XEN_BRIDGE); 1390 1390 + DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE); 1391 1391 BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL); 1392 1392 1393 1393 - qdev_init_nofail(dev); 1393 1393 + qdev_realize_and_unref(dev, NULL, &error_fatal); 1394 1394 qbus_set_bus_hotplug_handler(bus, &error_abort); 1395 1395 }

+2 -2

hw/xen/xen-legacy-backend.c

··· 703 703 xengnttab_close(gnttabdev); 704 704 } 705 705 706 706 - xen_sysdev = qdev_create(NULL, TYPE_XENSYSDEV); 707 707 - qdev_init_nofail(xen_sysdev); 706 706 + xen_sysdev = qdev_new(TYPE_XENSYSDEV); 707 707 + qdev_realize_and_unref(xen_sysdev, NULL, &error_fatal); 708 708 xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus"); 709 709 qbus_set_bus_hotplug_handler(xen_sysbus, &error_abort); 710 710

+2 -2

hw/xtensa/virt.c

··· 62 62 qemu_irq *extints; 63 63 int i; 64 64 65 65 - dev = qdev_create(NULL, TYPE_GPEX_HOST); 66 66 - qdev_init_nofail(dev); 65 65 + dev = qdev_new(TYPE_GPEX_HOST); 66 66 + qdev_realize_and_unref(dev, NULL, &error_fatal); 67 67 68 68 /* Map only the first size_ecam bytes of ECAM space. */ 69 69 ecam_alias = g_new0(MemoryRegion, 1);

+4 -4

hw/xtensa/xtfpga.c

··· 148 148 SysBusDevice *s; 149 149 MemoryRegion *ram; 150 150 151 151 - dev = qdev_create(NULL, "open_eth"); 151 151 + dev = qdev_new("open_eth"); 152 152 qdev_set_nic_properties(dev, nd); 153 153 - qdev_init_nofail(dev); 153 153 + qdev_realize_and_unref(dev, NULL, &error_fatal); 154 154 155 155 s = SYS_BUS_DEVICE(dev); 156 156 sysbus_connect_irq(s, 0, irq); ··· 171 171 DriveInfo *dinfo, int be) 172 172 { 173 173 SysBusDevice *s; 174 174 - DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 174 174 + DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 175 175 176 176 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 177 177 &error_abort); ··· 181 181 qdev_prop_set_uint8(dev, "width", 2); 182 182 qdev_prop_set_bit(dev, "big-endian", be); 183 183 qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 184 184 - qdev_init_nofail(dev); 184 184 + qdev_realize_and_unref(dev, NULL, &error_fatal); 185 185 s = SYS_BUS_DEVICE(dev); 186 186 memory_region_add_subregion(address_space, board->flash->base, 187 187 sysbus_mmio_get_region(s, 0));

+3 -2

include/hw/char/cadence_uart.h

··· 22 22 #include "hw/qdev-properties.h" 23 23 #include "hw/sysbus.h" 24 24 #include "chardev/char-fe.h" 25 25 + #include "qapi/error.h" 25 26 #include "qemu/timer.h" 26 27 27 28 #define CADENCE_UART_RX_FIFO_SIZE 16 ··· 59 60 DeviceState *dev; 60 61 SysBusDevice *s; 61 62 62 62 - dev = qdev_create(NULL, TYPE_CADENCE_UART); 63 63 + dev = qdev_new(TYPE_CADENCE_UART); 63 64 s = SYS_BUS_DEVICE(dev); 64 65 qdev_prop_set_chr(dev, "chardev", chr); 65 65 - qdev_init_nofail(dev); 66 66 + qdev_realize_and_unref(dev, NULL, &error_fatal); 66 67 sysbus_mmio_map(s, 0, addr); 67 68 sysbus_connect_irq(s, 0, irq); 68 69

+2 -2

include/hw/char/cmsdk-apb-uart.h

··· 62 62 DeviceState *dev; 63 63 SysBusDevice *s; 64 64 65 65 - dev = qdev_create(NULL, TYPE_CMSDK_APB_UART); 65 65 + dev = qdev_new(TYPE_CMSDK_APB_UART); 66 66 s = SYS_BUS_DEVICE(dev); 67 67 qdev_prop_set_chr(dev, "chardev", chr); 68 68 qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); 69 69 - qdev_init_nofail(dev); 69 69 + qdev_realize_and_unref(dev, NULL, &error_fatal); 70 70 sysbus_mmio_map(s, 0, addr); 71 71 sysbus_connect_irq(s, 0, txint); 72 72 sysbus_connect_irq(s, 1, rxint);

+5 -4

include/hw/char/pl011.h

··· 18 18 #include "hw/qdev-properties.h" 19 19 #include "hw/sysbus.h" 20 20 #include "chardev/char-fe.h" 21 21 + #include "qapi/error.h" 21 22 22 23 #define TYPE_PL011 "pl011" 23 24 #define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011) ··· 57 58 DeviceState *dev; 58 59 SysBusDevice *s; 59 60 60 60 - dev = qdev_create(NULL, "pl011"); 61 61 + dev = qdev_new("pl011"); 61 62 s = SYS_BUS_DEVICE(dev); 62 63 qdev_prop_set_chr(dev, "chardev", chr); 63 63 - qdev_init_nofail(dev); 64 64 + qdev_realize_and_unref(dev, NULL, &error_fatal); 64 65 sysbus_mmio_map(s, 0, addr); 65 66 sysbus_connect_irq(s, 0, irq); 66 67 ··· 74 75 DeviceState *dev; 75 76 SysBusDevice *s; 76 77 77 77 - dev = qdev_create(NULL, "pl011_luminary"); 78 78 + dev = qdev_new("pl011_luminary"); 78 79 s = SYS_BUS_DEVICE(dev); 79 80 qdev_prop_set_chr(dev, "chardev", chr); 80 80 - qdev_init_nofail(dev); 81 81 + qdev_realize_and_unref(dev, NULL, &error_fatal); 81 82 sysbus_mmio_map(s, 0, addr); 82 83 sysbus_connect_irq(s, 0, irq); 83 84

+2 -2

include/hw/char/xilinx_uartlite.h

··· 25 25 DeviceState *dev; 26 26 SysBusDevice *s; 27 27 28 28 - dev = qdev_create(NULL, "xlnx.xps-uartlite"); 28 28 + dev = qdev_new("xlnx.xps-uartlite"); 29 29 s = SYS_BUS_DEVICE(dev); 30 30 qdev_prop_set_chr(dev, "chardev", chr); 31 31 - qdev_init_nofail(dev); 31 31 + qdev_realize_and_unref(dev, NULL, &error_fatal); 32 32 sysbus_mmio_map(s, 0, addr); 33 33 sysbus_connect_irq(s, 0, irq); 34 34

+2 -2

include/hw/cris/etraxfs.h

··· 41 41 DeviceState *dev; 42 42 SysBusDevice *s; 43 43 44 44 - dev = qdev_create(NULL, "etraxfs,serial"); 44 44 + dev = qdev_new("etraxfs,serial"); 45 45 s = SYS_BUS_DEVICE(dev); 46 46 qdev_prop_set_chr(dev, "chardev", chr); 47 47 - qdev_init_nofail(dev); 47 47 + qdev_realize_and_unref(dev, NULL, &error_fatal); 48 48 sysbus_mmio_map(s, 0, addr); 49 49 sysbus_connect_irq(s, 0, irq); 50 50 return dev;

+3 -2

include/hw/misc/unimp.h

··· 10 10 11 11 #include "hw/qdev-properties.h" 12 12 #include "hw/sysbus.h" 13 13 + #include "qapi/error.h" 13 14 14 15 #define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device" 15 16 ··· 40 41 hwaddr base, 41 42 hwaddr size) 42 43 { 43 43 - DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE); 44 44 + DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 44 45 45 46 qdev_prop_set_string(dev, "name", name); 46 47 qdev_prop_set_uint64(dev, "size", size); 47 47 - qdev_init_nofail(dev); 48 48 + qdev_realize_and_unref(dev, NULL, &error_fatal); 48 49 49 50 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000); 50 51 }

+2 -2

include/hw/timer/cmsdk-apb-timer.h

··· 48 48 DeviceState *dev; 49 49 SysBusDevice *s; 50 50 51 51 - dev = qdev_create(NULL, TYPE_CMSDK_APB_TIMER); 51 51 + dev = qdev_new(TYPE_CMSDK_APB_TIMER); 52 52 s = SYS_BUS_DEVICE(dev); 53 53 qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); 54 54 - qdev_init_nofail(dev); 54 54 + qdev_realize_and_unref(dev, NULL, &error_fatal); 55 55 sysbus_mmio_map(s, 0, addr); 56 56 sysbus_connect_irq(s, 0, timerint); 57 57 return dev;