jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
raspi: add BCM2835 SOC MPHI emulation
Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
emulation. It is very basic, only providing the FIQ interrupt
needed to allow the dwc-otg USB host controller driver in the
Raspbian kernel to function.
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Acked-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200520235349.21215-2-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Paul Zimmerman
and committed by
Peter Maydell
3d46938b
7a1e049a
+255
+17
hw/arm/bcm2835_peripherals.c
+17
hw/arm/bcm2835_peripherals.c
···
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OBJECT(&s->sdhci.sdbus));
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object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
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OBJECT(&s->sdhost.sdbus));
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+
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/* Mphi */
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sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi),
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TYPE_BCM2835_MPHI);
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}
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static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
···
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
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object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus");
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+
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/* Mphi */
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object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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+
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memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0,
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qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
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INTERRUPT_HOSTPORT));
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create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
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create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
+1
hw/misc/Makefile.objs
+1
hw/misc/Makefile.objs
···
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common-obj-$(CONFIG_OMAP) += omap_sdrc.o
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common-obj-$(CONFIG_OMAP) += omap_tap.o
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common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o
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common-obj-$(CONFIG_RASPI) += bcm2835_mphi.o
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common-obj-$(CONFIG_RASPI) += bcm2835_property.o
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common-obj-$(CONFIG_RASPI) += bcm2835_rng.o
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common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o
+191
hw/misc/bcm2835_mphi.c
+191
hw/misc/bcm2835_mphi.c
···
1
+
/*
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* BCM2835 SOC MPHI emulation
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*
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* Very basic emulation, only providing the FIQ interrupt needed to
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* allow the dwc-otg USB host controller driver in the Raspbian kernel
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* to function.
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*
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* Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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+
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/misc/bcm2835_mphi.h"
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#include "migration/vmstate.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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static inline void mphi_raise_irq(BCM2835MphiState *s)
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{
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qemu_set_irq(s->irq, 1);
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}
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+
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static inline void mphi_lower_irq(BCM2835MphiState *s)
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{
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qemu_set_irq(s->irq, 0);
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}
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+
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static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size)
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{
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BCM2835MphiState *s = ptr;
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uint32_t val = 0;
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+
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switch (addr) {
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case 0x28: /* outdda */
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val = s->outdda;
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break;
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case 0x2c: /* outddb */
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val = s->outddb;
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break;
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case 0x4c: /* ctrl */
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val = s->ctrl;
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val |= 1 << 17;
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break;
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case 0x50: /* intstat */
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val = s->intstat;
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break;
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case 0x1f0: /* swirq_set */
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val = s->swirq;
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break;
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case 0x1f4: /* swirq_clr */
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val = s->swirq;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "read from unknown register");
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break;
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}
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return val;
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}
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static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned size)
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{
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BCM2835MphiState *s = ptr;
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int do_irq = 0;
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switch (addr) {
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case 0x28: /* outdda */
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s->outdda = val;
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break;
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case 0x2c: /* outddb */
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s->outddb = val;
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if (val & (1 << 29)) {
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do_irq = 1;
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}
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break;
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case 0x4c: /* ctrl */
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s->ctrl = val;
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if (val & (1 << 16)) {
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do_irq = -1;
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}
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break;
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case 0x50: /* intstat */
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s->intstat = val;
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if (val & ((1 << 16) | (1 << 29))) {
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do_irq = -1;
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}
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break;
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case 0x1f0: /* swirq_set */
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s->swirq |= val;
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do_irq = 1;
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break;
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case 0x1f4: /* swirq_clr */
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s->swirq &= ~val;
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do_irq = -1;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "write to unknown register");
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return;
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}
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if (do_irq > 0) {
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mphi_raise_irq(s);
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} else if (do_irq < 0) {
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mphi_lower_irq(s);
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}
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}
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static const MemoryRegionOps mphi_mmio_ops = {
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.read = mphi_reg_read,
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.write = mphi_reg_write,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void mphi_reset(DeviceState *dev)
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{
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BCM2835MphiState *s = BCM2835_MPHI(dev);
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s->outdda = 0;
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s->outddb = 0;
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s->ctrl = 0;
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s->intstat = 0;
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s->swirq = 0;
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}
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static void mphi_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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BCM2835MphiState *s = BCM2835_MPHI(dev);
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sysbus_init_irq(sbd, &s->irq);
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}
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static void mphi_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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BCM2835MphiState *s = BCM2835_MPHI(obj);
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memory_region_init_io(&s->iomem, obj, &mphi_mmio_ops, s, "mphi", MPHI_MMIO_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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+
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const VMStateDescription vmstate_mphi_state = {
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.name = "mphi",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(outdda, BCM2835MphiState),
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VMSTATE_UINT32(outddb, BCM2835MphiState),
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VMSTATE_UINT32(ctrl, BCM2835MphiState),
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VMSTATE_UINT32(intstat, BCM2835MphiState),
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VMSTATE_UINT32(swirq, BCM2835MphiState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void mphi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = mphi_realize;
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dc->reset = mphi_reset;
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dc->vmsd = &vmstate_mphi_state;
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}
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static const TypeInfo bcm2835_mphi_type_info = {
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.name = TYPE_BCM2835_MPHI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BCM2835MphiState),
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.instance_init = mphi_init,
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.class_init = mphi_class_init,
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};
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static void bcm2835_mphi_register_types(void)
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{
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type_register_static(&bcm2835_mphi_type_info);
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}
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type_init(bcm2835_mphi_register_types)
+2
include/hw/arm/bcm2835_peripherals.h
+2
include/hw/arm/bcm2835_peripherals.h
···
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#include "hw/misc/bcm2835_property.h"
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#include "hw/misc/bcm2835_rng.h"
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#include "hw/misc/bcm2835_mbox.h"
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#include "hw/misc/bcm2835_mphi.h"
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#include "hw/misc/bcm2835_thermal.h"
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#include "hw/sd/sdhci.h"
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#include "hw/sd/bcm2835_sdhost.h"
···
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qemu_irq irq, fiq;
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BCM2835SystemTimerState systmr;
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BCM2835MphiState mphi;
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UnimplementedDeviceState armtmr;
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UnimplementedDeviceState cprman;
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UnimplementedDeviceState a2w;
+44
include/hw/misc/bcm2835_mphi.h
+44
include/hw/misc/bcm2835_mphi.h
···
1
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/*
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* BCM2835 SOC MPHI state definitions
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*
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+
* Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com>
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License as published by
8
+
* the Free Software Foundation; either version 2 of the License, or
9
+
* (at your option) any later version.
10
+
*
11
+
* This program is distributed in the hope that it will be useful,
12
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
15
+
*/
16
+
17
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#ifndef HW_MISC_BCM2835_MPHI_H
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#define HW_MISC_BCM2835_MPHI_H
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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+
23
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#define MPHI_MMIO_SIZE 0x1000
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+
25
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typedef struct BCM2835MphiState BCM2835MphiState;
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+
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struct BCM2835MphiState {
28
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SysBusDevice parent_obj;
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qemu_irq irq;
30
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MemoryRegion iomem;
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+
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uint32_t outdda;
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uint32_t outddb;
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uint32_t ctrl;
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uint32_t intstat;
36
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uint32_t swirq;
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};
38
+
39
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#define TYPE_BCM2835_MPHI "bcm2835-mphi"
40
+
41
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#define BCM2835_MPHI(obj) \
42
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OBJECT_CHECK(BCM2835MphiState, (obj), TYPE_BCM2835_MPHI)
43
+
44
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#endif