+1 -1

hw/alpha/typhoon.c

··· 889 889 &s->pchip.reg_mem, &s->pchip.reg_io, 890 890 0, 64, TYPE_PCI_BUS); 891 891 phb->bus = b; 892 892 - qdev_realize_and_unref(dev, NULL, &error_fatal); 892 892 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 893 893 894 894 /* Host memory as seen from the PCI side, via the IOMMU. */ 895 895 memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu),

+9 -9

hw/arm/exynos4210.c

··· 184 184 qdev_prop_set_uint8(dev, "rd_q_dep", 8); 185 185 qdev_prop_set_uint8(dev, "data_width", width); 186 186 qdev_prop_set_uint16(dev, "data_buffer_dep", width); 187 187 - qdev_realize_and_unref(dev, NULL, &error_fatal); 188 187 busdev = SYS_BUS_DEVICE(dev); 188 188 + sysbus_realize_and_unref(busdev, &error_fatal); 189 189 sysbus_mmio_map(busdev, 0, base); 190 190 191 191 object_property_set_int(OBJECT(orgate), nevents + 1, "num-lines", ··· 234 234 for (i = 0; i < EXYNOS4210_NCPUS; i++) { 235 235 dev = qdev_new("exynos4210.irq_gate"); 236 236 qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); 237 237 - qdev_realize_and_unref(dev, NULL, &error_fatal); 237 237 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 238 238 /* Get IRQ Gate input in gate_irq */ 239 239 for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { 240 240 gate_irq[i][n] = qdev_get_gpio_in(dev, n); ··· 249 249 /* Private memory region and Internal GIC */ 250 250 dev = qdev_new(TYPE_A9MPCORE_PRIV); 251 251 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 252 252 - qdev_realize_and_unref(dev, NULL, &error_fatal); 253 252 busdev = SYS_BUS_DEVICE(dev); 253 253 + sysbus_realize_and_unref(busdev, &error_fatal); 254 254 sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); 255 255 for (n = 0; n < EXYNOS4210_NCPUS; n++) { 256 256 sysbus_connect_irq(busdev, n, gate_irq[n][0]); ··· 265 265 /* External GIC */ 266 266 dev = qdev_new("exynos4210.gic"); 267 267 qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); 268 268 - qdev_realize_and_unref(dev, NULL, &error_fatal); 269 268 busdev = SYS_BUS_DEVICE(dev); 269 269 + sysbus_realize_and_unref(busdev, &error_fatal); 270 270 /* Map CPU interface */ 271 271 sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); 272 272 /* Map Distributer interface */ ··· 280 280 281 281 /* Internal Interrupt Combiner */ 282 282 dev = qdev_new("exynos4210.combiner"); 283 283 - qdev_realize_and_unref(dev, NULL, &error_fatal); 284 283 busdev = SYS_BUS_DEVICE(dev); 284 284 + sysbus_realize_and_unref(busdev, &error_fatal); 285 285 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 286 286 sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); 287 287 } ··· 291 291 /* External Interrupt Combiner */ 292 292 dev = qdev_new("exynos4210.combiner"); 293 293 qdev_prop_set_uint32(dev, "external", 1); 294 294 - qdev_realize_and_unref(dev, NULL, &error_fatal); 295 294 busdev = SYS_BUS_DEVICE(dev); 295 295 + sysbus_realize_and_unref(busdev, &error_fatal); 296 296 for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { 297 297 sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); 298 298 } ··· 354 354 355 355 /* Multi Core Timer */ 356 356 dev = qdev_new("exynos4210.mct"); 357 357 - qdev_realize_and_unref(dev, NULL, &error_fatal); 358 357 busdev = SYS_BUS_DEVICE(dev); 358 358 + sysbus_realize_and_unref(busdev, &error_fatal); 359 359 for (n = 0; n < 4; n++) { 360 360 /* Connect global timer interrupts to Combiner gpio_in */ 361 361 sysbus_connect_irq(busdev, n, ··· 380 380 } 381 381 382 382 dev = qdev_new("exynos4210.i2c"); 383 383 - qdev_realize_and_unref(dev, NULL, &error_fatal); 384 383 busdev = SYS_BUS_DEVICE(dev); 384 384 + sysbus_realize_and_unref(busdev, &error_fatal); 385 385 sysbus_connect_irq(busdev, 0, i2c_irq); 386 386 sysbus_mmio_map(busdev, 0, addr); 387 387 s->i2c_if[n] = (I2CBus *)qdev_get_child_bus(dev, "i2c"); ··· 425 425 */ 426 426 dev = qdev_new(TYPE_S3C_SDHCI); 427 427 qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); 428 428 - qdev_realize_and_unref(dev, NULL, &error_fatal); 429 428 430 429 busdev = SYS_BUS_DEVICE(dev); 430 430 + sysbus_realize_and_unref(busdev, &error_fatal); 431 431 sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n)); 432 432 sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]); 433 433

+1 -1

hw/arm/exynos4_boards.c

··· 84 84 dev = qdev_new(TYPE_LAN9118); 85 85 qdev_set_nic_properties(dev, &nd_table[0]); 86 86 qdev_prop_set_uint32(dev, "mode_16bit", 1); 87 87 - qdev_realize_and_unref(dev, NULL, &error_fatal); 88 87 s = SYS_BUS_DEVICE(dev); 88 88 + sysbus_realize_and_unref(s, &error_fatal); 89 89 sysbus_mmio_map(s, 0, base); 90 90 sysbus_connect_irq(s, 0, irq); 91 91 }

+6 -6

hw/arm/highbank.c

··· 312 312 switch (machine_id) { 313 313 case CALXEDA_HIGHBANK: 314 314 dev = qdev_new("l2x0"); 315 315 - qdev_realize_and_unref(dev, NULL, &error_fatal); 316 315 busdev = SYS_BUS_DEVICE(dev); 316 316 + sysbus_realize_and_unref(busdev, &error_fatal); 317 317 sysbus_mmio_map(busdev, 0, 0xfff12000); 318 318 319 319 dev = qdev_new(TYPE_A9MPCORE_PRIV); ··· 324 324 } 325 325 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 326 326 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); 327 327 - qdev_realize_and_unref(dev, NULL, &error_fatal); 328 327 busdev = SYS_BUS_DEVICE(dev); 328 328 + sysbus_realize_and_unref(busdev, &error_fatal); 329 329 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 330 330 for (n = 0; n < smp_cpus; n++) { 331 331 sysbus_connect_irq(busdev, n, cpu_irq[n]); ··· 341 341 dev = qdev_new("sp804"); 342 342 qdev_prop_set_uint32(dev, "freq0", 150000000); 343 343 qdev_prop_set_uint32(dev, "freq1", 150000000); 344 344 - qdev_realize_and_unref(dev, NULL, &error_fatal); 345 344 busdev = SYS_BUS_DEVICE(dev); 345 345 + sysbus_realize_and_unref(busdev, &error_fatal); 346 346 sysbus_mmio_map(busdev, 0, 0xfff34000); 347 347 sysbus_connect_irq(busdev, 0, pic[18]); 348 348 pl011_create(0xfff36000, pic[20], serial_hd(0)); 349 349 350 350 dev = qdev_new(TYPE_HIGHBANK_REGISTERS); 351 351 - qdev_realize_and_unref(dev, NULL, &error_fatal); 352 351 busdev = SYS_BUS_DEVICE(dev); 352 352 + sysbus_realize_and_unref(busdev, &error_fatal); 353 353 sysbus_mmio_map(busdev, 0, 0xfff3c000); 354 354 355 355 sysbus_create_simple("pl061", 0xfff30000, pic[14]); ··· 365 365 qemu_check_nic_model(&nd_table[0], "xgmac"); 366 366 dev = qdev_new("xgmac"); 367 367 qdev_set_nic_properties(dev, &nd_table[0]); 368 368 - qdev_realize_and_unref(dev, NULL, &error_fatal); 368 368 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 369 369 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); 370 370 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); 371 371 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); ··· 374 374 qemu_check_nic_model(&nd_table[1], "xgmac"); 375 375 dev = qdev_new("xgmac"); 376 376 qdev_set_nic_properties(dev, &nd_table[1]); 377 377 - qdev_realize_and_unref(dev, NULL, &error_fatal); 377 377 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 378 378 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); 379 379 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); 380 380 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);

+1 -1

hw/arm/integratorcp.c

··· 622 622 623 623 dev = qdev_new(TYPE_INTEGRATOR_CM); 624 624 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 625 625 - qdev_realize_and_unref(dev, NULL, &error_fatal); 625 625 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 626 626 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 627 627 628 628 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,

+1 -1

hw/arm/mps2-tz.c

··· 247 247 qemu_check_nic_model(nd, "lan9118"); 248 248 mms->lan9118 = qdev_new(TYPE_LAN9118); 249 249 qdev_set_nic_properties(mms->lan9118, nd); 250 250 - qdev_realize_and_unref(mms->lan9118, NULL, &error_fatal); 251 250 252 251 s = SYS_BUS_DEVICE(mms->lan9118); 252 252 + sysbus_realize_and_unref(s, &error_fatal); 253 253 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); 254 254 return sysbus_mmio_get_region(s, 0); 255 255 }

+1 -1

hw/arm/msf2-som.c

··· 77 77 qdev_prop_set_uint32(dev, "apb0div", 2); 78 78 qdev_prop_set_uint32(dev, "apb1div", 2); 79 79 80 80 - qdev_realize_and_unref(dev, NULL, &error_fatal); 80 80 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 81 81 82 82 soc = MSF2_SOC(dev); 83 83

+2 -2

hw/arm/musicpal.c

··· 1653 1653 qemu_check_nic_model(&nd_table[0], "mv88w8618"); 1654 1654 dev = qdev_new(TYPE_MV88W8618_ETH); 1655 1655 qdev_set_nic_properties(dev, &nd_table[0]); 1656 1656 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1656 1656 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1657 1657 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); 1658 1658 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); 1659 1659 ··· 1692 1692 s = SYS_BUS_DEVICE(dev); 1693 1693 object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev), 1694 1694 "wm8750", NULL); 1695 1695 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1695 1695 + sysbus_realize_and_unref(s, &error_fatal); 1696 1696 sysbus_mmio_map(s, 0, MP_AUDIO_BASE); 1697 1697 sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); 1698 1698

+1 -1

hw/arm/netduino2.c

··· 36 36 37 37 dev = qdev_new(TYPE_STM32F205_SOC); 38 38 qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); 39 39 - qdev_realize_and_unref(dev, NULL, &error_fatal); 39 39 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 40 40 41 41 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 42 42 FLASH_SIZE);

+1 -1

hw/arm/netduinoplus2.c

··· 36 36 37 37 dev = qdev_new(TYPE_STM32F405_SOC); 38 38 qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); 39 39 - qdev_realize_and_unref(dev, NULL, &error_fatal); 39 39 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 40 40 41 41 armv7m_load_kernel(ARM_CPU(first_cpu), 42 42 machine->kernel_filename,

+2 -2

hw/arm/nseries.c

··· 185 185 qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo), 186 186 &error_fatal); 187 187 } 188 188 - qdev_realize_and_unref(s->nand, NULL, &error_fatal); 188 188 + sysbus_realize_and_unref(SYS_BUS_DEVICE(s->nand), &error_fatal); 189 189 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0, 190 190 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO)); 191 191 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS, ··· 804 804 SysBusDevice *dev; 805 805 s->usb = qdev_new("tusb6010"); 806 806 dev = SYS_BUS_DEVICE(s->usb); 807 807 - qdev_realize_and_unref(s->usb, NULL, &error_fatal); 807 807 + sysbus_realize_and_unref(dev, &error_fatal); 808 808 sysbus_connect_irq(dev, 0, 809 809 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO)); 810 810 /* Using the NOR interface */

+4 -4

hw/arm/omap1.c

··· 3890 3890 s->ih[0] = qdev_new("omap-intc"); 3891 3891 qdev_prop_set_uint32(s->ih[0], "size", 0x100); 3892 3892 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "arminth_ck")); 3893 3893 - qdev_realize_and_unref(s->ih[0], NULL, &error_fatal); 3894 3893 busdev = SYS_BUS_DEVICE(s->ih[0]); 3894 3894 + sysbus_realize_and_unref(busdev, &error_fatal); 3895 3895 sysbus_connect_irq(busdev, 0, 3896 3896 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 3897 3897 sysbus_connect_irq(busdev, 1, ··· 3900 3900 s->ih[1] = qdev_new("omap-intc"); 3901 3901 qdev_prop_set_uint32(s->ih[1], "size", 0x800); 3902 3902 omap_intc_set_iclk(OMAP_INTC(s->ih[1]), omap_findclk(s, "arminth_ck")); 3903 3903 - qdev_realize_and_unref(s->ih[1], NULL, &error_fatal); 3904 3903 busdev = SYS_BUS_DEVICE(s->ih[1]); 3904 3904 + sysbus_realize_and_unref(busdev, &error_fatal); 3905 3905 sysbus_connect_irq(busdev, 0, 3906 3906 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); 3907 3907 /* The second interrupt controller's FIQ output is not wired up */ ··· 4013 4013 s->gpio = qdev_new("omap-gpio"); 4014 4014 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); 4015 4015 omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck")); 4016 4016 - qdev_realize_and_unref(s->gpio, NULL, &error_fatal); 4016 4016 + sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal); 4017 4017 sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, 4018 4018 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); 4019 4019 sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); ··· 4031 4031 s->i2c[0] = qdev_new("omap_i2c"); 4032 4032 qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); 4033 4033 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "mpuper_ck")); 4034 4034 - qdev_realize_and_unref(s->i2c[0], NULL, &error_fatal); 4035 4034 busdev = SYS_BUS_DEVICE(s->i2c[0]); 4035 4035 + sysbus_realize_and_unref(busdev, &error_fatal); 4036 4036 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); 4037 4037 sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); 4038 4038 sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);

+4 -4

hw/arm/omap2.c

··· 2310 2310 qdev_prop_set_uint8(s->ih[0], "revision", 0x21); 2311 2311 omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk")); 2312 2312 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk")); 2313 2313 - qdev_realize_and_unref(s->ih[0], NULL, &error_fatal); 2314 2313 busdev = SYS_BUS_DEVICE(s->ih[0]); 2314 2314 + sysbus_realize_and_unref(busdev, &error_fatal); 2315 2315 sysbus_connect_irq(busdev, 0, 2316 2316 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); 2317 2317 sysbus_connect_irq(busdev, 1, ··· 2427 2427 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34); 2428 2428 omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk")); 2429 2429 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk")); 2430 2430 - qdev_realize_and_unref(s->i2c[0], NULL, &error_fatal); 2431 2430 busdev = SYS_BUS_DEVICE(s->i2c[0]); 2431 2431 + sysbus_realize_and_unref(busdev, &error_fatal); 2432 2432 sysbus_connect_irq(busdev, 0, 2433 2433 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ)); 2434 2434 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]); ··· 2439 2439 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34); 2440 2440 omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk")); 2441 2441 omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk")); 2442 2442 - qdev_realize_and_unref(s->i2c[1], NULL, &error_fatal); 2443 2442 busdev = SYS_BUS_DEVICE(s->i2c[1]); 2443 2443 + sysbus_realize_and_unref(busdev, &error_fatal); 2444 2444 sysbus_connect_irq(busdev, 0, 2445 2445 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ)); 2446 2446 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]); ··· 2458 2458 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4, 2459 2459 omap_findclk(s, "gpio5_dbclk")); 2460 2460 } 2461 2461 - qdev_realize_and_unref(s->gpio, NULL, &error_fatal); 2462 2461 busdev = SYS_BUS_DEVICE(s->gpio); 2462 2462 + sysbus_realize_and_unref(busdev, &error_fatal); 2463 2463 sysbus_connect_irq(busdev, 0, 2464 2464 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1)); 2465 2465 sysbus_connect_irq(busdev, 3,

+2 -2

hw/arm/pxa2xx.c

··· 1513 1513 dev = qdev_new(TYPE_PXA2XX_I2C); 1514 1514 qdev_prop_set_uint32(dev, "size", region_size + 1); 1515 1515 qdev_prop_set_uint32(dev, "offset", base & region_size); 1516 1516 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1517 1516 1518 1517 i2c_dev = SYS_BUS_DEVICE(dev); 1518 1518 + sysbus_realize_and_unref(i2c_dev, &error_fatal); 1519 1519 sysbus_mmio_map(i2c_dev, 0, base & ~region_size); 1520 1520 sysbus_connect_irq(i2c_dev, 0, irq); 1521 1521 ··· 2075 2075 2076 2076 dev = qdev_new(TYPE_PXA2XX_FIR); 2077 2077 qdev_prop_set_chr(dev, "chardev", chr); 2078 2078 - qdev_realize_and_unref(dev, NULL, &error_fatal); 2079 2078 sbd = SYS_BUS_DEVICE(dev); 2079 2079 + sysbus_realize_and_unref(sbd, &error_fatal); 2080 2080 sysbus_mmio_map(sbd, 0, base); 2081 2081 sysbus_connect_irq(sbd, 0, irq); 2082 2082 sysbus_connect_irq(sbd, 1, rx_dma);

+1 -1

hw/arm/pxa2xx_gpio.c

··· 273 273 dev = qdev_new(TYPE_PXA2XX_GPIO); 274 274 qdev_prop_set_int32(dev, "lines", lines); 275 275 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index); 276 276 - qdev_realize_and_unref(dev, NULL, &error_fatal); 276 276 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 277 277 278 278 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 279 279 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,

+1 -1

hw/arm/pxa2xx_pic.c

··· 280 280 s->is_fiq[0] = 0; 281 281 s->is_fiq[1] = 0; 282 282 283 283 - qdev_realize_and_unref(dev, NULL, &error_fatal); 283 283 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 284 284 285 285 qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); 286 286

+5 -5

hw/arm/realview.c

··· 164 164 sysctl = qdev_new("realview_sysctl"); 165 165 qdev_prop_set_uint32(sysctl, "sys_id", sys_id); 166 166 qdev_prop_set_uint32(sysctl, "proc_id", proc_id); 167 167 - qdev_realize_and_unref(sysctl, NULL, &error_fatal); 167 167 + sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 168 168 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 169 169 170 170 if (is_mpcore) { 171 171 dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore"); 172 172 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 173 173 - qdev_realize_and_unref(dev, NULL, &error_fatal); 174 173 busdev = SYS_BUS_DEVICE(dev); 174 174 + sysbus_realize_and_unref(busdev, &error_fatal); 175 175 sysbus_mmio_map(busdev, 0, periphbase); 176 176 for (n = 0; n < smp_cpus; n++) { 177 177 sysbus_connect_irq(busdev, n, cpu_irq[n]); ··· 190 190 191 191 pl041 = qdev_new("pl041"); 192 192 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 193 193 - qdev_realize_and_unref(pl041, NULL, &error_fatal); 193 193 + sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 194 194 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 195 195 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); 196 196 ··· 206 206 dev = qdev_new("pl081"); 207 207 object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", 208 208 &error_fatal); 209 209 - qdev_realize_and_unref(dev, NULL, &error_fatal); 210 209 busdev = SYS_BUS_DEVICE(dev); 210 210 + sysbus_realize_and_unref(busdev, &error_fatal); 211 211 sysbus_mmio_map(busdev, 0, 0x10030000); 212 212 sysbus_connect_irq(busdev, 0, pic[24]); 213 213 ··· 241 241 if (!is_pb) { 242 242 dev = qdev_new("realview_pci"); 243 243 busdev = SYS_BUS_DEVICE(dev); 244 244 - qdev_realize_and_unref(dev, NULL, &error_fatal); 244 244 + sysbus_realize_and_unref(busdev, &error_fatal); 245 245 sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ 246 246 sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ 247 247 sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */

+6 -6

hw/arm/sbsa-ref.c

··· 243 243 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); 244 244 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); 245 245 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); 246 246 - qdev_realize_and_unref(dev, NULL, &error_fatal); 246 246 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 247 247 248 248 memory_region_add_subregion(sysmem, base, 249 249 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), ··· 356 356 qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); 357 357 qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); 358 358 359 359 - qdev_realize_and_unref(sms->gic, NULL, &error_fatal); 360 359 gicbusdev = SYS_BUS_DEVICE(sms->gic); 360 360 + sysbus_realize_and_unref(gicbusdev, &error_fatal); 361 361 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); 362 362 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); 363 363 ··· 413 413 SysBusDevice *s = SYS_BUS_DEVICE(dev); 414 414 415 415 qdev_prop_set_chr(dev, "chardev", chr); 416 416 - qdev_realize_and_unref(dev, NULL, &error_fatal); 416 416 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 417 417 memory_region_add_subregion(mem, base, 418 418 sysbus_mmio_get_region(s, 0)); 419 419 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); ··· 466 466 467 467 dev = qdev_new("sysbus-ahci"); 468 468 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); 469 469 - qdev_realize_and_unref(dev, NULL, &error_fatal); 469 469 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 470 470 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 471 471 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); 472 472 ··· 501 501 502 502 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 503 503 &error_abort); 504 504 - qdev_realize_and_unref(dev, NULL, &error_fatal); 504 504 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 505 505 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 506 506 for (i = 0; i < NUM_SMMU_IRQS; i++) { 507 507 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, ··· 526 526 int i; 527 527 528 528 dev = qdev_new(TYPE_GPEX_HOST); 529 529 - qdev_realize_and_unref(dev, NULL, &error_fatal); 529 529 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 530 530 531 531 /* Map ECAM space */ 532 532 ecam_alias = g_new0(MemoryRegion, 1);

+1 -1

hw/arm/spitz.c

··· 163 163 else if (size == FLASH_1024M) 164 164 qdev_prop_set_uint8(dev, "chip_id", 0xf1); 165 165 166 166 - qdev_realize_and_unref(dev, NULL, &error_fatal); 166 166 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 167 167 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE); 168 168 } 169 169

+3 -3

hw/arm/stellaris.c

··· 1315 1315 object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), 1316 1316 "memory", &error_abort); 1317 1317 /* This will exit with an error if the user passed us a bad cpu_type */ 1318 1318 - qdev_realize_and_unref(nvic, NULL, &error_fatal); 1318 1318 + sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal); 1319 1319 1320 1320 qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, 1321 1321 qemu_allocate_irq(&do_sys_reset, NULL, 0)); ··· 1353 1353 uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; 1354 1354 qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); 1355 1355 1356 1356 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1356 1356 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1357 1357 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1358 1358 0, 1359 1359 0x40000000u); ··· 1427 1427 1428 1428 enet = qdev_new("stellaris_enet"); 1429 1429 qdev_set_nic_properties(enet, &nd_table[0]); 1430 1430 - qdev_realize_and_unref(enet, NULL, &error_fatal); 1430 1430 + sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal); 1431 1431 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); 1432 1432 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); 1433 1433 }

+2 -2

hw/arm/strongarm.c

··· 646 646 int i; 647 647 648 648 dev = qdev_new(TYPE_STRONGARM_GPIO); 649 649 - qdev_realize_and_unref(dev, NULL, &error_fatal); 649 649 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 650 650 651 651 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 652 652 for (i = 0; i < 12; i++) ··· 1629 1629 for (i = 0; sa_serial[i].io_base; i++) { 1630 1630 DeviceState *dev = qdev_new(TYPE_STRONGARM_UART); 1631 1631 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 1632 1632 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1632 1632 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1633 1633 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 1634 1634 sa_serial[i].io_base); 1635 1635 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,

+4 -4

hw/arm/versatilepb.c

··· 226 226 sysctl = qdev_new("realview_sysctl"); 227 227 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); 228 228 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); 229 229 - qdev_realize_and_unref(sysctl, NULL, &error_fatal); 229 229 + sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 230 230 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); 231 231 232 232 dev = sysbus_create_varargs("pl190", 0x10140000, ··· 247 247 248 248 dev = qdev_new("versatile_pci"); 249 249 busdev = SYS_BUS_DEVICE(dev); 250 250 - qdev_realize_and_unref(dev, NULL, &error_fatal); 250 250 + sysbus_realize_and_unref(busdev, &error_fatal); 251 251 sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ 252 252 sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ 253 253 sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ ··· 289 289 dev = qdev_new("pl080"); 290 290 object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", 291 291 &error_fatal); 292 292 - qdev_realize_and_unref(dev, NULL, &error_fatal); 293 292 busdev = SYS_BUS_DEVICE(dev); 293 293 + sysbus_realize_and_unref(busdev, &error_fatal); 294 294 sysbus_mmio_map(busdev, 0, 0x10130000); 295 295 sysbus_connect_irq(busdev, 0, pic[17]); 296 296 ··· 321 321 /* Add PL041 AACI Interface to the LM4549 codec */ 322 322 pl041 = qdev_new("pl041"); 323 323 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 324 324 - qdev_realize_and_unref(pl041, NULL, &error_fatal); 324 324 + sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 325 325 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); 326 326 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); 327 327

+4 -4

hw/arm/vexpress.c

··· 238 238 */ 239 239 dev = qdev_new(privdev); 240 240 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); 241 241 - qdev_realize_and_unref(dev, NULL, &error_fatal); 242 241 busdev = SYS_BUS_DEVICE(dev); 242 242 + sysbus_realize_and_unref(busdev, &error_fatal); 243 243 sysbus_mmio_map(busdev, 0, periphbase); 244 244 245 245 /* Interrupts [42:0] are from the motherboard; ··· 532 532 qdev_prop_set_uint16(dev, "id2", 0x00); 533 533 qdev_prop_set_uint16(dev, "id3", 0x00); 534 534 qdev_prop_set_string(dev, "name", name); 535 535 - qdev_realize_and_unref(dev, NULL, &error_fatal); 535 535 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 536 536 537 537 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 538 538 return PFLASH_CFI01(dev); ··· 610 610 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); 611 611 g_free(propname); 612 612 } 613 613 - qdev_realize_and_unref(sysctl, NULL, &error_fatal); 613 613 + sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal); 614 614 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); 615 615 616 616 /* VE_SP810: not modelled */ ··· 618 618 619 619 pl041 = qdev_new("pl041"); 620 620 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); 621 621 - qdev_realize_and_unref(pl041, NULL, &error_fatal); 621 621 + sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal); 622 622 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]); 623 623 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); 624 624

+9 -9

hw/arm/virt.c

··· 579 579 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 580 580 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 581 581 582 582 - qdev_realize_and_unref(dev, NULL, &error_fatal); 582 582 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 583 583 584 584 return dev; 585 585 } ··· 598 598 599 599 object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", 600 600 &error_abort); 601 601 - qdev_realize_and_unref(dev, NULL, &error_fatal); 601 601 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 602 602 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 603 603 604 604 fdt_add_its_gic_node(vms); ··· 614 614 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 615 615 qdev_prop_set_uint32(dev, "base-spi", irq); 616 616 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 617 617 - qdev_realize_and_unref(dev, NULL, &error_fatal); 617 617 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 618 618 619 619 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 620 620 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, ··· 671 671 vms->virt); 672 672 } 673 673 } 674 674 - qdev_realize_and_unref(vms->gic, NULL, &error_fatal); 675 674 gicbusdev = SYS_BUS_DEVICE(vms->gic); 675 675 + sysbus_realize_and_unref(gicbusdev, &error_fatal); 676 676 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 677 677 if (type == 3) { 678 678 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); ··· 758 758 SysBusDevice *s = SYS_BUS_DEVICE(dev); 759 759 760 760 qdev_prop_set_chr(dev, "chardev", chr); 761 761 - qdev_realize_and_unref(dev, NULL, &error_fatal); 761 761 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 762 762 memory_region_add_subregion(mem, base, 763 763 sysbus_mmio_get_region(s, 0)); 764 764 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); ··· 980 980 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 981 981 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 982 982 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 983 983 - qdev_realize_and_unref(dev, NULL, &error_fatal); 983 983 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 984 984 985 985 memory_region_add_subregion(sysmem, base, 986 986 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), ··· 1177 1177 1178 1178 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", 1179 1179 &error_abort); 1180 1180 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1180 1180 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1181 1181 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1182 1182 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1183 1183 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, ··· 1254 1254 PCIHostState *pci; 1255 1255 1256 1256 dev = qdev_new(TYPE_GPEX_HOST); 1257 1257 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1257 1257 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1258 1258 1259 1259 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1260 1260 base_ecam = vms->memmap[ecam_id].base; ··· 1376 1376 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1377 1377 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1378 1378 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1379 1379 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1379 1379 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1380 1380 vms->platform_bus_dev = dev; 1381 1381 1382 1382 s = SYS_BUS_DEVICE(dev);

+8 -8

hw/arm/xilinx_zynq.c

··· 119 119 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 120 120 qdev_set_nic_properties(dev, nd); 121 121 } 122 122 - qdev_realize_and_unref(dev, NULL, &error_fatal); 123 122 s = SYS_BUS_DEVICE(dev); 123 123 + sysbus_realize_and_unref(s, &error_fatal); 124 124 sysbus_mmio_map(s, 0, base); 125 125 sysbus_connect_irq(s, 0, irq); 126 126 } ··· 140 140 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); 141 141 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); 142 142 qdev_prop_set_uint8(dev, "num-busses", num_busses); 143 143 - qdev_realize_and_unref(dev, NULL, &error_fatal); 144 143 busdev = SYS_BUS_DEVICE(dev); 144 144 + sysbus_realize_and_unref(busdev, &error_fatal); 145 145 sysbus_mmio_map(busdev, 0, base_addr); 146 146 if (is_qspi) { 147 147 sysbus_mmio_map(busdev, 1, 0xFC000000); ··· 223 223 224 224 /* Create slcr, keep a pointer to connect clocks */ 225 225 slcr = qdev_new("xilinx,zynq_slcr"); 226 226 - qdev_realize_and_unref(slcr, NULL, &error_fatal); 226 226 + sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); 227 227 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); 228 228 229 229 /* Create the main clock source, and feed slcr with it */ ··· 236 236 237 237 dev = qdev_new(TYPE_A9MPCORE_PRIV); 238 238 qdev_prop_set_uint32(dev, "num-cpu", 1); 239 239 - qdev_realize_and_unref(dev, NULL, &error_fatal); 240 239 busdev = SYS_BUS_DEVICE(dev); 240 240 + sysbus_realize_and_unref(busdev, &error_fatal); 241 241 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); 242 242 sysbus_connect_irq(busdev, 0, 243 243 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); ··· 283 283 dev = qdev_new(TYPE_SYSBUS_SDHCI); 284 284 qdev_prop_set_uint8(dev, "sd-spec-version", 2); 285 285 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); 286 286 - qdev_realize_and_unref(dev, NULL, &error_fatal); 286 286 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 287 287 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); 288 288 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); 289 289 ··· 296 296 } 297 297 298 298 dev = qdev_new(TYPE_ZYNQ_XADC); 299 299 - qdev_realize_and_unref(dev, NULL, &error_fatal); 299 299 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 300 300 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); 301 301 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); 302 302 ··· 312 312 qdev_prop_set_uint8(dev, "rd_q_dep", 16); 313 313 qdev_prop_set_uint16(dev, "data_buffer_dep", 256); 314 314 315 315 - qdev_realize_and_unref(dev, NULL, &error_fatal); 316 315 busdev = SYS_BUS_DEVICE(dev); 316 316 + sysbus_realize_and_unref(busdev, &error_fatal); 317 317 sysbus_mmio_map(busdev, 0, 0xF8003000); 318 318 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ 319 319 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ ··· 321 321 } 322 322 323 323 dev = qdev_new("xlnx.ps7-dev-cfg"); 324 324 - qdev_realize_and_unref(dev, NULL, &error_fatal); 325 324 busdev = SYS_BUS_DEVICE(dev); 325 325 + sysbus_realize_and_unref(busdev, &error_fatal); 326 326 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); 327 327 sysbus_mmio_map(busdev, 0, 0xF8007000); 328 328

+1 -1

hw/arm/xlnx-versal-virt.c

··· 434 434 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); 435 435 dev = qdev_new("virtio-mmio"); 436 436 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev)); 437 437 - qdev_realize_and_unref(dev, NULL, &error_fatal); 437 437 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 438 438 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); 439 439 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 440 440 memory_region_add_subregion(&s->soc.mr_ps, base, mr);

+1 -1

hw/arm/xlnx-versal.c

··· 309 309 qdev_prop_set_string(dev, "name", name); 310 310 qdev_prop_set_uint64(dev, "size", size); 311 311 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 312 312 - qdev_realize_and_unref(dev, NULL, &error_fatal); 312 312 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 313 313 314 314 mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 315 315 memory_region_add_subregion(mr, base, mr_dev);

+2 -2

hw/block/fdc.c

··· 2583 2583 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), 2584 2584 &error_fatal); 2585 2585 } 2586 2586 - qdev_realize_and_unref(dev, NULL, &error_fatal); 2587 2586 sbd = SYS_BUS_DEVICE(dev); 2587 2587 + sysbus_realize_and_unref(sbd, &error_fatal); 2588 2588 sysbus_connect_irq(sbd, 0, irq); 2589 2589 sysbus_mmio_map(sbd, 0, mmio_base); 2590 2590 } ··· 2600 2600 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]), 2601 2601 &error_fatal); 2602 2602 } 2603 2603 - qdev_realize_and_unref(dev, NULL, &error_fatal); 2603 2603 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2604 2604 sys = SYSBUS_FDC(dev); 2605 2605 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); 2606 2606 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);

+1 -1

hw/block/pflash_cfi01.c

··· 974 974 qdev_prop_set_uint16(dev, "id2", id2); 975 975 qdev_prop_set_uint16(dev, "id3", id3); 976 976 qdev_prop_set_string(dev, "name", name); 977 977 - qdev_realize_and_unref(dev, NULL, &error_fatal); 977 977 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 978 978 979 979 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 980 980 return PFLASH_CFI01(dev);

+1 -1

hw/block/pflash_cfi02.c

··· 1016 1016 qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); 1017 1017 qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); 1018 1018 qdev_prop_set_string(dev, "name", name); 1019 1019 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1019 1019 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1020 1020 1021 1021 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1022 1022 return PFLASH_CFI02(dev);

+1 -1

hw/char/exynos4210_uart.c

··· 661 661 qdev_prop_set_uint32(dev, "tx-size", fifo_size); 662 662 663 663 bus = SYS_BUS_DEVICE(dev); 664 664 - qdev_realize_and_unref(dev, NULL, &error_fatal); 664 664 + sysbus_realize_and_unref(bus, &error_fatal); 665 665 if (addr != (hwaddr)-1) { 666 666 sysbus_mmio_map(bus, 0, addr); 667 667 }

+1 -1

hw/char/mcf_uart.c

··· 348 348 if (chrdrv) { 349 349 qdev_prop_set_chr(dev, "chardev", chrdrv); 350 350 } 351 351 - qdev_realize_and_unref(dev, NULL, &error_fatal); 351 351 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 352 352 353 353 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 354 354

+1 -1

hw/char/serial.c

··· 1134 1134 qdev_prop_set_chr(DEVICE(smm), "chardev", chr); 1135 1135 qdev_set_legacy_instance_id(DEVICE(smm), base, 2); 1136 1136 qdev_prop_set_uint8(DEVICE(smm), "endianness", end); 1137 1137 - qdev_realize_and_unref(DEVICE(smm), NULL, &error_fatal); 1137 1137 + sysbus_realize_and_unref(SYS_BUS_DEVICE(smm), &error_fatal); 1138 1138 1139 1139 sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq); 1140 1140 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0);

+1 -1

hw/core/sysbus.c

··· 232 232 233 233 dev = qdev_new(name); 234 234 s = SYS_BUS_DEVICE(dev); 235 235 - qdev_realize_and_unref(dev, NULL, &error_fatal); 235 235 + sysbus_realize_and_unref(s, &error_fatal); 236 236 if (addr != (hwaddr)-1) { 237 237 sysbus_mmio_map(s, 0, addr); 238 238 }

+1 -1

hw/cris/axis_dev88.c

··· 290 290 291 291 292 292 dev = qdev_new("etraxfs,pic"); 293 293 - qdev_realize_and_unref(dev, NULL, &error_fatal); 294 293 s = SYS_BUS_DEVICE(dev); 294 294 + sysbus_realize_and_unref(s, &error_fatal); 295 295 sysbus_mmio_map(s, 0, 0x3001c000); 296 296 sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ)); 297 297 sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));

+1 -1

hw/display/milkymist-tmu2.c

··· 544 544 XCloseDisplay(d); 545 545 546 546 dev = qdev_new(TYPE_MILKYMIST_TMU2); 547 547 - qdev_realize_and_unref(dev, NULL, &error_fatal); 547 547 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 548 548 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 549 549 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 550 550

+1 -1

hw/display/sm501.c

··· 1971 1971 usb_dev = qdev_new("sysbus-ohci"); 1972 1972 qdev_prop_set_uint32(usb_dev, "num-ports", 2); 1973 1973 qdev_prop_set_uint64(usb_dev, "dma-offset", s->base); 1974 1974 - qdev_realize_and_unref(usb_dev, NULL, &error_fatal); 1974 1974 + sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal); 1975 1975 memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, 1976 1976 sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0)); 1977 1977 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));

+2 -2

hw/dma/pxa2xx_dma.c

··· 497 497 498 498 dev = qdev_new("pxa2xx-dma"); 499 499 qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); 500 500 - qdev_realize_and_unref(dev, NULL, &error_fatal); 500 500 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 501 501 502 502 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 503 503 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); ··· 511 511 512 512 dev = qdev_new("pxa2xx-dma"); 513 513 qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); 514 514 - qdev_realize_and_unref(dev, NULL, &error_fatal); 514 514 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 515 515 516 516 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 517 517 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

+1 -1

hw/dma/rc4030.c

··· 746 746 DeviceState *dev; 747 747 748 748 dev = qdev_new(TYPE_RC4030); 749 749 - qdev_realize_and_unref(dev, NULL, &error_fatal); 749 749 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 750 750 751 751 *dmas = rc4030_allocate_dmas(dev, 4); 752 752 *dma_mr = &RC4030(dev)->dma_mr;

+4 -4

hw/dma/sparc32_dma.c

··· 310 310 esp->dma_opaque = SPARC32_DMA_DEVICE(dev); 311 311 sysbus->it_shift = 2; 312 312 esp->dma_enabled = 1; 313 313 - qdev_realize_and_unref(d, NULL, &error_fatal); 313 313 + sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal); 314 314 } 315 315 316 316 static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data) ··· 347 347 object_property_add_child(OBJECT(dev), "lance", OBJECT(d)); 348 348 qdev_set_nic_properties(d, nd); 349 349 object_property_set_link(OBJECT(d), OBJECT(dev), "dma", errp); 350 350 - qdev_realize_and_unref(d, NULL, &error_fatal); 350 350 + sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal); 351 351 } 352 352 353 353 static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data) ··· 381 381 espdma = qdev_new(TYPE_SPARC32_ESPDMA_DEVICE); 382 382 object_property_set_link(OBJECT(espdma), iommu, "iommu", errp); 383 383 object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma)); 384 384 - qdev_realize_and_unref(espdma, NULL, &error_fatal); 384 384 + sysbus_realize_and_unref(SYS_BUS_DEVICE(espdma), &error_fatal); 385 385 386 386 esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp")); 387 387 sbd = SYS_BUS_DEVICE(esp); ··· 396 396 ledma = qdev_new(TYPE_SPARC32_LEDMA_DEVICE); 397 397 object_property_set_link(OBJECT(ledma), iommu, "iommu", errp); 398 398 object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma)); 399 399 - qdev_realize_and_unref(ledma, NULL, &error_fatal); 399 399 + sysbus_realize_and_unref(SYS_BUS_DEVICE(ledma), &error_fatal); 400 400 401 401 lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance")); 402 402 sbd = SYS_BUS_DEVICE(lance);

+1 -1

hw/hppa/dino.c

··· 548 548 &s->pci_mem, get_system_io(), 549 549 PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS); 550 550 s->parent_obj.bus = b; 551 551 - qdev_realize_and_unref(dev, NULL, &error_fatal); 551 551 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 552 552 553 553 /* Set up windows into PCI bus memory. */ 554 554 for (i = 1; i < 31; i++) {

+1 -1

hw/hppa/lasi.c

··· 309 309 s, "lasi", 0x100000); 310 310 memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem); 311 311 312 312 - qdev_realize_and_unref(dev, NULL, &error_fatal); 312 312 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 313 313 314 314 /* LAN */ 315 315 if (enable_lasi_lan()) {

+1 -1

hw/hppa/machine.c

··· 125 125 /* Graphics setup. */ 126 126 if (machine->enable_graphics && vga_interface_type != VGA_NONE) { 127 127 dev = qdev_new("artist"); 128 128 - qdev_realize_and_unref(dev, NULL, &error_fatal); 129 128 s = SYS_BUS_DEVICE(dev); 129 129 + sysbus_realize_and_unref(s, &error_fatal); 130 130 sysbus_mmio_map(s, 0, LASI_GFX_HPA); 131 131 sysbus_mmio_map(s, 1, ARTIST_FB_ADDR); 132 132 }

+1 -1

hw/i386/pc.c

··· 1216 1216 if (!compat) { 1217 1217 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1218 1218 } 1219 1219 - qdev_realize_and_unref(hpet, NULL, &error_fatal); 1219 1219 + sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1220 1220 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1221 1221 1222 1222 for (i = 0; i < GSI_NUM_PINS; i++) {

+1 -1

hw/i386/pc_q35.c

··· 230 230 object_property_set_int(OBJECT(q35_host), x86ms->above_4g_mem_size, 231 231 PCI_HOST_ABOVE_4G_MEM_SIZE, NULL); 232 232 /* pci */ 233 233 - qdev_realize_and_unref(DEVICE(q35_host), NULL, &error_fatal); 233 233 + sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); 234 234 phb = PCI_HOST_BRIDGE(q35_host); 235 235 host_bus = phb->bus; 236 236 /* create ISA bus */

+1 -1

hw/i386/pc_sysfw.c

··· 187 187 total_size += size; 188 188 qdev_prop_set_uint32(DEVICE(system_flash), "num-blocks", 189 189 size / FLASH_SECTOR_SIZE); 190 190 - qdev_realize_and_unref(DEVICE(system_flash), NULL, &error_fatal); 190 190 + sysbus_realize_and_unref(SYS_BUS_DEVICE(system_flash), &error_fatal); 191 191 sysbus_mmio_map(SYS_BUS_DEVICE(system_flash), 0, 192 192 0x100000000ULL - total_size); 193 193

+1 -1

hw/i386/x86.c

··· 351 351 } 352 352 object_property_add_child(object_resolve_path(parent_name, NULL), 353 353 "ioapic", OBJECT(dev)); 354 354 - qdev_realize_and_unref(dev, NULL, &error_fatal); 355 354 d = SYS_BUS_DEVICE(dev); 355 355 + sysbus_realize_and_unref(d, &error_fatal); 356 356 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 357 357 358 358 for (i = 0; i < IOAPIC_NUM_PINS; i++) {

+1 -1

hw/intc/exynos4210_gic.c

··· 300 300 s->gic = qdev_new("arm_gic"); 301 301 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); 302 302 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); 303 303 - qdev_realize_and_unref(s->gic, NULL, &error_fatal); 304 303 gicbusdev = SYS_BUS_DEVICE(s->gic); 304 304 + sysbus_realize_and_unref(gicbusdev, &error_fatal); 305 305 306 306 /* Pass through outbound IRQ lines from the GIC */ 307 307 sysbus_pass_irq(sbd, gicbusdev);

+1 -1

hw/intc/s390_flic.c

··· 71 71 object_property_add_child(qdev_get_machine(), TYPE_QEMU_S390_FLIC, 72 72 OBJECT(dev)); 73 73 } 74 74 - qdev_realize_and_unref(dev, NULL, &error_fatal); 74 74 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 75 75 } 76 76 77 77 static int qemu_s390_register_io_adapter(S390FLICState *fs, uint32_t id,

+1 -1

hw/isa/isa-bus.c

··· 62 62 } 63 63 if (!dev) { 64 64 dev = qdev_new("isabus-bridge"); 65 65 - qdev_realize_and_unref(dev, NULL, &error_fatal); 65 65 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 66 66 } 67 67 68 68 isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL));

+3 -3

hw/lm32/lm32.h

··· 11 11 SysBusDevice *d; 12 12 13 13 dev = qdev_new("lm32-pic"); 14 14 - qdev_realize_and_unref(dev, NULL, &error_fatal); 15 14 d = SYS_BUS_DEVICE(dev); 15 15 + sysbus_realize_and_unref(d, &error_fatal); 16 16 sysbus_connect_irq(d, 0, cpu_irq); 17 17 18 18 return dev; ··· 24 24 25 25 dev = qdev_new(TYPE_LM32_JUART); 26 26 qdev_prop_set_chr(dev, "chardev", chr); 27 27 - qdev_realize_and_unref(dev, NULL, &error_fatal); 27 27 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 28 28 29 29 return dev; 30 30 } ··· 39 39 dev = qdev_new("lm32-uart"); 40 40 s = SYS_BUS_DEVICE(dev); 41 41 qdev_prop_set_chr(dev, "chardev", chr); 42 42 - qdev_realize_and_unref(dev, NULL, &error_fatal); 42 42 + sysbus_realize_and_unref(s, &error_fatal); 43 43 sysbus_mmio_map(s, 0, addr); 44 44 sysbus_connect_irq(s, 0, irq); 45 45 return dev;

+9 -9

hw/lm32/milkymist-hw.h

··· 13 13 14 14 dev = qdev_new("milkymist-uart"); 15 15 qdev_prop_set_chr(dev, "chardev", chr); 16 16 - qdev_realize_and_unref(dev, NULL, &error_fatal); 16 16 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 17 17 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 18 18 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 19 19 ··· 25 25 DeviceState *dev; 26 26 27 27 dev = qdev_new("milkymist-hpdmc"); 28 28 - qdev_realize_and_unref(dev, NULL, &error_fatal); 28 28 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 29 29 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 30 30 31 31 return dev; ··· 36 36 DeviceState *dev; 37 37 38 38 dev = qdev_new("milkymist-memcard"); 39 39 - qdev_realize_and_unref(dev, NULL, &error_fatal); 39 39 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 40 40 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 41 41 42 42 return dev; ··· 50 50 dev = qdev_new("milkymist-vgafb"); 51 51 qdev_prop_set_uint32(dev, "fb_offset", fb_offset); 52 52 qdev_prop_set_uint32(dev, "fb_mask", fb_mask); 53 53 - qdev_realize_and_unref(dev, NULL, &error_fatal); 53 53 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 54 54 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 55 55 56 56 return dev; ··· 68 68 qdev_prop_set_uint32(dev, "systemid", system_id); 69 69 qdev_prop_set_uint32(dev, "capabilities", capabilities); 70 70 qdev_prop_set_uint32(dev, "gpio_strappings", gpio_strappings); 71 71 - qdev_realize_and_unref(dev, NULL, &error_fatal); 71 71 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 72 72 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 73 73 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, gpio_irq); 74 74 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, timer0_irq); ··· 83 83 DeviceState *dev; 84 84 85 85 dev = qdev_new("milkymist-pfpu"); 86 86 - qdev_realize_and_unref(dev, NULL, &error_fatal); 86 86 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 87 87 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 88 88 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 89 89 return dev; ··· 96 96 DeviceState *dev; 97 97 98 98 dev = qdev_new("milkymist-ac97"); 99 99 - qdev_realize_and_unref(dev, NULL, &error_fatal); 99 99 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 100 100 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 101 101 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, crrequest_irq); 102 102 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, crreply_irq); ··· 114 114 qemu_check_nic_model(&nd_table[0], "minimac2"); 115 115 dev = qdev_new("milkymist-minimac2"); 116 116 qdev_set_nic_properties(dev, &nd_table[0]); 117 117 - qdev_realize_and_unref(dev, NULL, &error_fatal); 117 117 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 118 118 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 119 119 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, buffers_base); 120 120 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, rx_irq); ··· 132 132 dev = qdev_new("milkymist-softusb"); 133 133 qdev_prop_set_uint32(dev, "pmem_size", pmem_size); 134 134 qdev_prop_set_uint32(dev, "dmem_size", dmem_size); 135 135 - qdev_realize_and_unref(dev, NULL, &error_fatal); 135 135 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 136 136 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 137 137 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, pmem_base); 138 138 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, dmem_base);

+1 -1

hw/m68k/mcf5208.c

··· 216 216 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET); 217 217 dev = qdev_new(TYPE_MCF_FEC_NET); 218 218 qdev_set_nic_properties(dev, nd); 219 219 - qdev_realize_and_unref(dev, NULL, &error_fatal); 220 219 221 220 s = SYS_BUS_DEVICE(dev); 221 221 + sysbus_realize_and_unref(s, &error_fatal); 222 222 for (i = 0; i < FEC_NUM_IRQ; i++) { 223 223 sysbus_connect_irq(s, i, irqs[i]); 224 224 }

+1 -1

hw/m68k/mcf_intc.c

··· 206 206 mcf_intc_state *s; 207 207 208 208 dev = qdev_new(TYPE_MCF_INTC); 209 209 - qdev_realize_and_unref(dev, NULL, &error_fatal); 209 209 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 210 210 211 211 s = MCF_INTC(dev); 212 212 s->cpu = cpu;

+3 -3

hw/m68k/next-cube.c

··· 848 848 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 849 849 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 850 850 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 851 851 - qdev_realize_and_unref(dev, NULL, &error_fatal); 852 851 853 852 s = SYS_BUS_DEVICE(dev); 853 853 + sysbus_realize_and_unref(s, &error_fatal); 854 854 sysbus_connect_irq(s, 0, ser_irq[0]); 855 855 sysbus_connect_irq(s, 1, ser_irq[1]); 856 856 sysbus_mmio_map(s, 0, 0x2118000); ··· 896 896 897 897 /* Framebuffer */ 898 898 dev = qdev_new(TYPE_NEXTFB); 899 899 - qdev_realize_and_unref(dev, NULL, &error_fatal); 899 899 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 900 900 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000); 901 901 902 902 /* MMIO */ ··· 919 919 920 920 /* KBD */ 921 921 dev = qdev_new(TYPE_NEXTKBD); 922 922 - qdev_realize_and_unref(dev, NULL, &error_fatal); 922 922 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 923 923 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000); 924 924 925 925 /* Load ROM here */

+6 -6

hw/m68k/q800.c

··· 224 224 qdev_prop_set_drive(via_dev, "drive", blk_by_legacy_dinfo(dinfo), 225 225 &error_abort); 226 226 } 227 227 - qdev_realize_and_unref(via_dev, NULL, &error_fatal); 228 227 sysbus = SYS_BUS_DEVICE(via_dev); 228 228 + sysbus_realize_and_unref(sysbus, &error_fatal); 229 229 sysbus_mmio_map(sysbus, 0, VIA_BASE); 230 230 qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0, pic[0]); 231 231 qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 1, pic[1]); ··· 265 265 qdev_prop_set_bit(dev, "big_endian", true); 266 266 object_property_set_link(OBJECT(dev), OBJECT(get_system_memory()), 267 267 "dma_mr", &error_abort); 268 268 - qdev_realize_and_unref(dev, NULL, &error_fatal); 269 268 sysbus = SYS_BUS_DEVICE(dev); 269 269 + sysbus_realize_and_unref(sysbus, &error_fatal); 270 270 sysbus_mmio_map(sysbus, 0, SONIC_BASE); 271 271 sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE); 272 272 sysbus_connect_irq(sysbus, 0, pic[2]); ··· 282 282 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 283 283 qdev_prop_set_uint32(dev, "chnBtype", 0); 284 284 qdev_prop_set_uint32(dev, "chnAtype", 0); 285 285 - qdev_realize_and_unref(dev, NULL, &error_fatal); 286 285 sysbus = SYS_BUS_DEVICE(dev); 286 286 + sysbus_realize_and_unref(sysbus, &error_fatal); 287 287 sysbus_connect_irq(sysbus, 0, pic[3]); 288 288 sysbus_connect_irq(sysbus, 1, pic[3]); 289 289 sysbus_mmio_map(sysbus, 0, SCC_BASE); ··· 298 298 esp->dma_opaque = NULL; 299 299 sysbus_esp->it_shift = 4; 300 300 esp->dma_enabled = 1; 301 301 - qdev_realize_and_unref(dev, NULL, &error_fatal); 302 301 303 302 sysbus = SYS_BUS_DEVICE(dev); 303 303 + sysbus_realize_and_unref(sysbus, &error_fatal); 304 304 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in_named(via_dev, 305 305 "via2-irq", 306 306 VIA2_IRQ_SCSI_BIT)); ··· 315 315 /* SWIM floppy controller */ 316 316 317 317 dev = qdev_new(TYPE_SWIM); 318 318 - qdev_realize_and_unref(dev, NULL, &error_fatal); 318 318 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 319 319 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE); 320 320 321 321 /* NuBus */ 322 322 323 323 dev = qdev_new(TYPE_MAC_NUBUS_BRIDGE); 324 324 - qdev_realize_and_unref(dev, NULL, &error_fatal); 324 324 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 325 325 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, NUBUS_SUPER_SLOT_BASE); 326 326 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE); 327 327

+5 -5

hw/microblaze/petalogix_ml605_mmu.c

··· 112 112 113 113 dev = qdev_new("xlnx.xps-intc"); 114 114 qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); 115 115 - qdev_realize_and_unref(dev, NULL, &error_fatal); 115 115 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 116 116 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 117 117 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 118 118 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ)); ··· 128 128 dev = qdev_new("xlnx.xps-timer"); 129 129 qdev_prop_set_uint32(dev, "one-timer-only", 0); 130 130 qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); 131 131 - qdev_realize_and_unref(dev, NULL, &error_fatal); 131 131 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 132 132 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 133 133 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 134 134 ··· 152 152 "axistream-connected", &error_abort); 153 153 object_property_set_link(OBJECT(eth0), cs, 154 154 "axistream-control-connected", &error_abort); 155 155 - qdev_realize_and_unref(eth0, NULL, &error_fatal); 155 155 + sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal); 156 156 sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR); 157 157 sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]); 158 158 ··· 165 165 "axistream-connected", &error_abort); 166 166 object_property_set_link(OBJECT(dma), cs, 167 167 "axistream-control-connected", &error_abort); 168 168 - qdev_realize_and_unref(dma, NULL, &error_fatal); 168 168 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 169 169 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); 170 170 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]); 171 171 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]); ··· 175 175 176 176 dev = qdev_new("xlnx.xps-spi"); 177 177 qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); 178 178 - qdev_realize_and_unref(dev, NULL, &error_fatal); 179 178 busdev = SYS_BUS_DEVICE(dev); 179 179 + sysbus_realize_and_unref(busdev, &error_fatal); 180 180 sysbus_mmio_map(busdev, 0, SPI_BASEADDR); 181 181 sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]); 182 182

+3 -3

hw/microblaze/petalogix_s3adsp1800_mmu.c

··· 92 92 dev = qdev_new("xlnx.xps-intc"); 93 93 qdev_prop_set_uint32(dev, "kind-of-intr", 94 94 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ); 95 95 - qdev_realize_and_unref(dev, NULL, &error_fatal); 95 95 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 96 96 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 97 97 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 98 98 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ)); ··· 107 107 dev = qdev_new("xlnx.xps-timer"); 108 108 qdev_prop_set_uint32(dev, "one-timer-only", 0); 109 109 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); 110 110 - qdev_realize_and_unref(dev, NULL, &error_fatal); 110 110 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 111 111 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 112 112 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 113 113 ··· 116 116 qdev_set_nic_properties(dev, &nd_table[0]); 117 117 qdev_prop_set_uint32(dev, "tx-ping-pong", 0); 118 118 qdev_prop_set_uint32(dev, "rx-ping-pong", 0); 119 119 - qdev_realize_and_unref(dev, NULL, &error_fatal); 119 119 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 120 120 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); 121 121 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); 122 122

+2 -2

hw/mips/boston.c

··· 409 409 qdev_prop_set_uint64(dev, "mmio_size", mmio_size); 410 410 qdev_prop_set_bit(dev, "link_up", link_up); 411 411 412 412 - qdev_realize_and_unref(dev, NULL, &error_fatal); 412 412 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 413 413 414 414 cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 415 415 memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0); ··· 442 442 } 443 443 444 444 dev = qdev_new(TYPE_MIPS_BOSTON); 445 445 - qdev_realize_and_unref(dev, NULL, &error_fatal); 445 445 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 446 446 447 447 s = BOSTON(dev); 448 448 s->mach = machine;

+1 -1

hw/mips/gt64xxx_pci.c

··· 1213 1213 &d->pci0_mem, 1214 1214 get_system_io(), 1215 1215 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); 1216 1216 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1216 1216 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1217 1217 memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, 1218 1218 "isd-mem", 0x1000); 1219 1219

+4 -4

hw/mips/jazz.c

··· 256 256 switch (jazz_model) { 257 257 case JAZZ_MAGNUM: 258 258 dev = qdev_new("sysbus-g364"); 259 259 - qdev_realize_and_unref(dev, NULL, &error_fatal); 260 259 sysbus = SYS_BUS_DEVICE(dev); 260 260 + sysbus_realize_and_unref(sysbus, &error_fatal); 261 261 sysbus_mmio_map(sysbus, 0, 0x60080000); 262 262 sysbus_mmio_map(sysbus, 1, 0x40000000); 263 263 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3)); ··· 292 292 qdev_prop_set_uint8(dev, "it_shift", 2); 293 293 object_property_set_link(OBJECT(dev), OBJECT(rc4030_dma_mr), 294 294 "dma_mr", &error_abort); 295 295 - qdev_realize_and_unref(dev, NULL, &error_fatal); 296 295 sysbus = SYS_BUS_DEVICE(dev); 296 296 + sysbus_realize_and_unref(sysbus, &error_fatal); 297 297 sysbus_mmio_map(sysbus, 0, 0x80001000); 298 298 sysbus_mmio_map(sysbus, 1, 0x8000b000); 299 299 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); ··· 317 317 sysbus_esp->it_shift = 0; 318 318 /* XXX for now until rc4030 has been changed to use DMA enable signal */ 319 319 esp->dma_enabled = 1; 320 320 - qdev_realize_and_unref(dev, NULL, &error_fatal); 321 320 322 321 sysbus = SYS_BUS_DEVICE(dev); 322 322 + sysbus_realize_and_unref(sysbus, &error_fatal); 323 323 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 5)); 324 324 sysbus_mmio_map(sysbus, 0, 0x80002000); 325 325 ··· 363 363 364 364 /* NVRAM */ 365 365 dev = qdev_new("ds1225y"); 366 366 - qdev_realize_and_unref(dev, NULL, &error_fatal); 367 366 sysbus = SYS_BUS_DEVICE(dev); 367 367 + sysbus_realize_and_unref(sysbus, &error_fatal); 368 368 sysbus_mmio_map(sysbus, 0, 0x80009000); 369 369 370 370 /* LED indicator */

+1 -1

hw/mips/malta.c

··· 1243 1243 */ 1244 1244 empty_slot_init("GT64120", 0, 0x20000000); 1245 1245 1246 1246 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1246 1246 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1247 1247 1248 1248 /* create CPU */ 1249 1249 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);

+2 -2

hw/mips/mipssim.c

··· 131 131 132 132 dev = qdev_new("mipsnet"); 133 133 qdev_set_nic_properties(dev, nd); 134 134 - qdev_realize_and_unref(dev, NULL, &error_fatal); 135 134 136 135 s = SYS_BUS_DEVICE(dev); 136 136 + sysbus_realize_and_unref(s, &error_fatal); 137 137 sysbus_connect_irq(s, 0, irq); 138 138 memory_region_add_subregion(get_system_io(), 139 139 base, ··· 220 220 221 221 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); 222 222 qdev_set_legacy_instance_id(dev, 0x3f8, 2); 223 223 - qdev_realize_and_unref(dev, NULL, &error_fatal); 223 223 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 224 224 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]); 225 225 sysbus_add_io(SYS_BUS_DEVICE(dev), 0x3f8, 226 226 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));

+1 -1

hw/misc/empty_slot.c

··· 60 60 dev = qdev_new(TYPE_EMPTY_SLOT); 61 61 62 62 qdev_prop_set_uint64(dev, "size", slot_size); 63 63 - qdev_realize_and_unref(dev, NULL, &error_fatal); 63 63 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 64 64 65 65 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, addr, -10000); 66 66 }

+1 -1

hw/net/etraxfs_eth.c

··· 668 668 */ 669 669 ETRAX_FS_ETH(dev)->dma_out = dma_out; 670 670 ETRAX_FS_ETH(dev)->dma_in = dma_in; 671 671 - qdev_realize_and_unref(dev, NULL, &error_fatal); 671 671 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 672 672 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 673 673 674 674 return dev;

+1 -1

hw/net/fsl_etsec/etsec.c

··· 455 455 456 456 dev = qdev_new("eTSEC"); 457 457 qdev_set_nic_properties(dev, nd); 458 458 - qdev_realize_and_unref(dev, NULL, &error_fatal); 458 458 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 459 459 460 460 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq); 461 461 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);

+1 -1

hw/net/lan9118.c

··· 1397 1397 qemu_check_nic_model(nd, "lan9118"); 1398 1398 dev = qdev_new(TYPE_LAN9118); 1399 1399 qdev_set_nic_properties(dev, nd); 1400 1400 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1401 1400 s = SYS_BUS_DEVICE(dev); 1401 1401 + sysbus_realize_and_unref(s, &error_fatal); 1402 1402 sysbus_mmio_map(s, 0, base); 1403 1403 sysbus_connect_irq(s, 0, irq); 1404 1404 }

+1 -1

hw/net/lasi_i82596.c

··· 131 131 s = SYSBUS_I82596(dev); 132 132 s->state.irq = lan_irq; 133 133 qdev_set_nic_properties(dev, &nd_table[0]); 134 134 - qdev_realize_and_unref(dev, NULL, &error_fatal); 134 134 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 135 135 s->state.conf.macaddr = HP_MAC; /* set HP MAC prefix */ 136 136 137 137 /* LASI 82596 ports in main memory. */

+1 -1

hw/net/smc91c111.c

··· 824 824 qemu_check_nic_model(nd, "smc91c111"); 825 825 dev = qdev_new(TYPE_SMC91C111); 826 826 qdev_set_nic_properties(dev, nd); 827 827 - qdev_realize_and_unref(dev, NULL, &error_fatal); 828 827 s = SYS_BUS_DEVICE(dev); 828 828 + sysbus_realize_and_unref(s, &error_fatal); 829 829 sysbus_mmio_map(s, 0, base); 830 830 sysbus_connect_irq(s, 0, irq); 831 831 }

+3 -3

hw/nios2/10m50_devboard.c

··· 82 82 /* Register: Internal Interrupt Controller (IIC) */ 83 83 dev = qdev_new("altera,iic"); 84 84 object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu)); 85 85 - qdev_realize_and_unref(dev, NULL, &error_fatal); 85 85 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 86 86 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); 87 87 for (i = 0; i < 32; i++) { 88 88 irq[i] = qdev_get_gpio_in(dev, i); ··· 95 95 /* Register: Timer sys_clk_timer */ 96 96 dev = qdev_new("ALTR.timer"); 97 97 qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000); 98 98 - qdev_realize_and_unref(dev, NULL, &error_fatal); 98 98 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 99 99 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xf8001440); 100 100 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[0]); 101 101 102 102 /* Register: Timer sys_clk_timer_1 */ 103 103 dev = qdev_new("ALTR.timer"); 104 104 qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000); 105 105 - qdev_realize_and_unref(dev, NULL, &error_fatal); 105 105 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 106 106 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880); 107 107 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]); 108 108

+2 -2

hw/nvram/fw_cfg.c

··· 1106 1106 1107 1107 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1108 1108 OBJECT(dev)); 1109 1109 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1110 1109 1111 1110 sbd = SYS_BUS_DEVICE(dev); 1111 1111 + sysbus_realize_and_unref(sbd, &error_fatal); 1112 1112 ios = FW_CFG_IO(dev); 1113 1113 sysbus_add_io(sbd, iobase, &ios->comb_iomem); 1114 1114 ··· 1146 1146 1147 1147 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1148 1148 OBJECT(dev)); 1149 1149 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1150 1149 1151 1150 sbd = SYS_BUS_DEVICE(dev); 1151 1151 + sysbus_realize_and_unref(sbd, &error_fatal); 1152 1152 sysbus_mmio_map(sbd, 0, ctl_addr); 1153 1153 sysbus_mmio_map(sbd, 1, data_addr); 1154 1154

+2 -2

hw/openrisc/openrisc_sim.c

··· 61 61 62 62 dev = qdev_new("open_eth"); 63 63 qdev_set_nic_properties(dev, nd); 64 64 - qdev_realize_and_unref(dev, NULL, &error_fatal); 65 64 66 65 s = SYS_BUS_DEVICE(dev); 66 66 + sysbus_realize_and_unref(s, &error_fatal); 67 67 for (i = 0; i < num_cpus; i++) { 68 68 sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]); 69 69 } ··· 80 80 81 81 dev = qdev_new("or1k-ompic"); 82 82 qdev_prop_set_uint32(dev, "num-cpus", num_cpus); 83 83 - qdev_realize_and_unref(dev, NULL, &error_fatal); 84 83 85 84 s = SYS_BUS_DEVICE(dev); 85 85 + sysbus_realize_and_unref(s, &error_fatal); 86 86 for (i = 0; i < num_cpus; i++) { 87 87 sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); 88 88 }

+1 -1

hw/pci-bridge/pci_expander_bridge.c

··· 255 255 goto err_register_bus; 256 256 } 257 257 258 258 - qdev_realize_and_unref(ds, NULL, &error_fatal); 258 258 + sysbus_realize_and_unref(SYS_BUS_DEVICE(ds), &error_fatal); 259 259 if (bds) { 260 260 qdev_realize_and_unref(bds, &bus->qbus, &error_fatal); 261 261 }

+1 -1

hw/pci-host/bonito.c

··· 748 748 phb = PCI_HOST_BRIDGE(dev); 749 749 pcihost = BONITO_PCI_HOST_BRIDGE(dev); 750 750 pcihost->pic = pic; 751 751 - qdev_realize_and_unref(dev, NULL, &error_fatal); 751 751 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 752 752 753 753 d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO); 754 754 s = PCI_BONITO(d);

+1 -1

hw/pci-host/i440fx.c

··· 277 277 address_space_io, 0, TYPE_PCI_BUS); 278 278 s->bus = b; 279 279 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev)); 280 280 - qdev_realize_and_unref(dev, NULL, &error_fatal); 280 280 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 281 281 282 282 d = pci_create_simple(b, 0, pci_type); 283 283 *pi440fx_state = I440FX_PCI_DEVICE(d);

+1 -1

hw/pcmcia/pxa2xx.c

··· 152 152 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 153 153 s = PXA2XX_PCMCIA(dev); 154 154 155 155 - qdev_realize_and_unref(dev, NULL, &error_fatal); 155 155 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 156 156 157 157 return s; 158 158 }

+8 -8

hw/ppc/e500.c

··· 748 748 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 749 749 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 750 750 751 751 - qdev_realize_and_unref(dev, NULL, &error_fatal); 752 751 s = SYS_BUS_DEVICE(dev); 752 752 + sysbus_realize_and_unref(s, &error_fatal); 753 753 754 754 k = 0; 755 755 for (i = 0; i < smp_cpus; i++) { ··· 771 771 dev = qdev_new(TYPE_KVM_OPENPIC); 772 772 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 773 773 774 774 - qdev_realize_and_unref(dev, NULL, &err); 774 774 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &err); 775 775 if (err) { 776 776 error_propagate(errp, err); 777 777 object_unparent(OBJECT(dev)); ··· 916 916 dev = qdev_new("e500-ccsr"); 917 917 object_property_add_child(qdev_get_machine(), "e500-ccsr", 918 918 OBJECT(dev)); 919 919 - qdev_realize_and_unref(dev, NULL, &error_fatal); 919 919 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 920 920 ccsr = CCSR(dev); 921 921 ccsr_addr_space = &ccsr->ccsr_space; 922 922 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, ··· 939 939 /* I2C */ 940 940 dev = qdev_new("mpc-i2c"); 941 941 s = SYS_BUS_DEVICE(dev); 942 942 - qdev_realize_and_unref(dev, NULL, &error_fatal); 942 942 + sysbus_realize_and_unref(s, &error_fatal); 943 943 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 944 944 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 945 945 sysbus_mmio_get_region(s, 0)); ··· 949 949 950 950 /* General Utility device */ 951 951 dev = qdev_new("mpc8544-guts"); 952 952 - qdev_realize_and_unref(dev, NULL, &error_fatal); 953 952 s = SYS_BUS_DEVICE(dev); 953 953 + sysbus_realize_and_unref(s, &error_fatal); 954 954 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 955 955 sysbus_mmio_get_region(s, 0)); 956 956 ··· 959 959 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev)); 960 960 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 961 961 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 962 962 - qdev_realize_and_unref(dev, NULL, &error_fatal); 963 962 s = SYS_BUS_DEVICE(dev); 963 963 + sysbus_realize_and_unref(s, &error_fatal); 964 964 for (i = 0; i < PCI_NUM_PINS; i++) { 965 965 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 966 966 } ··· 987 987 988 988 dev = qdev_new("mpc8xxx_gpio"); 989 989 s = SYS_BUS_DEVICE(dev); 990 990 - qdev_realize_and_unref(dev, NULL, &error_fatal); 990 990 + sysbus_realize_and_unref(s, &error_fatal); 991 991 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 992 992 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 993 993 sysbus_mmio_get_region(s, 0)); ··· 1003 1003 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1004 1004 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1005 1005 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1006 1006 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1006 1006 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1007 1007 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1008 1008 1009 1009 s = SYS_BUS_DEVICE(pms->pbus_dev);

+8 -8

hw/ppc/mac_newworld.c

··· 243 243 244 244 /* UniN init */ 245 245 dev = qdev_new(TYPE_UNI_NORTH); 246 246 - qdev_realize_and_unref(dev, NULL, &error_fatal); 247 246 s = SYS_BUS_DEVICE(dev); 247 247 + sysbus_realize_and_unref(s, &error_fatal); 248 248 memory_region_add_subregion(get_system_memory(), 0xf8000000, 249 249 sysbus_mmio_get_region(s, 0)); 250 250 ··· 290 290 291 291 pic_dev = qdev_new(TYPE_OPENPIC); 292 292 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); 293 293 - qdev_realize_and_unref(pic_dev, NULL, &error_fatal); 294 293 s = SYS_BUS_DEVICE(pic_dev); 294 294 + sysbus_realize_and_unref(s, &error_fatal); 295 295 k = 0; 296 296 for (i = 0; i < smp_cpus; i++) { 297 297 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { ··· 306 306 dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); 307 307 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 308 308 &error_abort); 309 309 - qdev_realize_and_unref(dev, NULL, &error_fatal); 309 309 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 310 310 uninorth_pci = U3_AGP_HOST_BRIDGE(dev); 311 311 s = SYS_BUS_DEVICE(dev); 312 312 /* PCI hole */ ··· 325 325 dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 326 326 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 327 327 &error_abort); 328 328 - qdev_realize_and_unref(dev, NULL, &error_fatal); 329 328 s = SYS_BUS_DEVICE(dev); 329 329 + sysbus_realize_and_unref(s, &error_fatal); 330 330 sysbus_mmio_map(s, 0, 0xf0800000); 331 331 sysbus_mmio_map(s, 1, 0xf0c00000); 332 332 ··· 334 334 dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 335 335 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 336 336 &error_abort); 337 337 - qdev_realize_and_unref(dev, NULL, &error_fatal); 338 337 s = SYS_BUS_DEVICE(dev); 338 338 + sysbus_realize_and_unref(s, &error_fatal); 339 339 sysbus_mmio_map(s, 0, 0xf4800000); 340 340 sysbus_mmio_map(s, 1, 0xf4c00000); 341 341 ··· 344 344 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000); 345 345 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 346 346 &error_abort); 347 347 - qdev_realize_and_unref(dev, NULL, &error_fatal); 347 347 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 348 348 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); 349 349 s = SYS_BUS_DEVICE(dev); 350 350 /* PCI hole */ ··· 444 444 dev = qdev_new(TYPE_MACIO_NVRAM); 445 445 qdev_prop_set_uint32(dev, "size", 0x2000); 446 446 qdev_prop_set_uint32(dev, "it_shift", 1); 447 447 - qdev_realize_and_unref(dev, NULL, &error_fatal); 447 447 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 448 448 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 449 449 nvr = MACIO_NVRAM(dev); 450 450 pmac_format_nvram_partition(nvr, 0x2000); ··· 456 456 qdev_prop_set_bit(dev, "dma_enabled", false); 457 457 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 458 458 OBJECT(fw_cfg)); 459 459 - qdev_realize_and_unref(dev, NULL, &error_fatal); 460 459 s = SYS_BUS_DEVICE(dev); 460 460 + sysbus_realize_and_unref(s, &error_fatal); 461 461 sysbus_mmio_map(s, 0, CFG_ADDR); 462 462 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 463 463

+3 -3

hw/ppc/mac_oldworld.c

··· 223 223 224 224 /* XXX: we register only 1 output pin for heathrow PIC */ 225 225 pic_dev = qdev_new(TYPE_HEATHROW); 226 226 - qdev_realize_and_unref(pic_dev, NULL, &error_fatal); 226 226 + sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal); 227 227 228 228 /* Connect the heathrow PIC outputs to the 6xx bus */ 229 229 for (i = 0; i < smp_cpus; i++) { ··· 256 256 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 257 257 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 258 258 &error_abort); 259 259 - qdev_realize_and_unref(dev, NULL, &error_fatal); 260 259 s = SYS_BUS_DEVICE(dev); 260 260 + sysbus_realize_and_unref(s, &error_fatal); 261 261 sysbus_mmio_map(s, 0, GRACKLE_BASE); 262 262 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 263 263 /* PCI hole */ ··· 315 315 qdev_prop_set_bit(dev, "dma_enabled", false); 316 316 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 317 317 OBJECT(fw_cfg)); 318 318 - qdev_realize_and_unref(dev, NULL, &error_fatal); 319 318 s = SYS_BUS_DEVICE(dev); 319 319 + sysbus_realize_and_unref(s, &error_fatal); 320 320 sysbus_mmio_map(s, 0, CFG_ADDR); 321 321 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 322 322

+4 -4

hw/ppc/pnv.c

··· 733 733 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 734 734 &error_abort); 735 735 } 736 736 - qdev_realize_and_unref(dev, NULL, &error_fatal); 736 736 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 737 737 pnv->pnor = PNV_PNOR(dev); 738 738 739 739 /* load skiboot firmware */ ··· 849 849 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 850 850 &error_abort); 851 851 } 852 852 - qdev_realize_and_unref(DEVICE(chip), NULL, &error_fatal); 852 852 + sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 853 853 } 854 854 g_free(chip_typename); 855 855 ··· 1205 1205 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1206 1206 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1207 1207 &error_fatal); 1208 1208 - qdev_realize(DEVICE(phb), NULL, &local_err); 1208 1208 + sysbus_realize(SYS_BUS_DEVICE(phb), &local_err); 1209 1209 if (local_err) { 1210 1210 error_propagate(errp, local_err); 1211 1211 return; ··· 1410 1410 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1411 1411 &error_fatal); 1412 1412 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1413 1413 - qdev_realize(DEVICE(obj), NULL, &local_err); 1413 1413 + sysbus_realize(SYS_BUS_DEVICE(obj), &local_err); 1414 1414 if (local_err) { 1415 1415 error_propagate(errp, local_err); 1416 1416 return;

+2 -2

hw/ppc/ppc440_uc.c

··· 1369 1369 1370 1370 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1371 1371 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE); 1372 1372 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1372 1372 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1373 1373 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1374 1374 1375 1375 dev = qdev_new(TYPE_PPC460EX_PCIE_HOST); 1376 1376 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE); 1377 1377 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1377 1377 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1378 1378 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1379 1379 }

+2 -2

hw/ppc/prep.c

··· 278 278 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 279 279 pcihost = SYS_BUS_DEVICE(dev); 280 280 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev)); 281 281 - qdev_realize_and_unref(dev, NULL, &error_fatal); 281 281 + sysbus_realize_and_unref(pcihost, &error_fatal); 282 282 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 283 283 if (!pci_bus) { 284 284 error_report("could not create PCI host controller"); ··· 351 351 qdev_prop_set_bit(dev, "dma_enabled", false); 352 352 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 353 353 OBJECT(fw_cfg)); 354 354 - qdev_realize_and_unref(dev, NULL, &error_fatal); 355 354 s = SYS_BUS_DEVICE(dev); 355 355 + sysbus_realize_and_unref(s, &error_fatal); 356 356 sysbus_mmio_map(s, 0, CFG_ADDR); 357 357 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 358 358

+1 -1

hw/ppc/sam460ex.c

··· 373 373 dev = qdev_new("sysbus-ohci"); 374 374 qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); 375 375 qdev_prop_set_uint32(dev, "num-ports", 6); 376 376 - qdev_realize_and_unref(dev, NULL, &error_fatal); 377 376 sbdev = SYS_BUS_DEVICE(dev); 377 377 + sysbus_realize_and_unref(sbdev, &error_fatal); 378 378 sysbus_mmio_map(sbdev, 0, 0x4bffd0000); 379 379 sysbus_connect_irq(sbdev, 0, uic[2][30]); 380 380 usb_create_simple(usb_bus_find(-1), "usb-kbd");

+1 -1

hw/ppc/spapr.c

··· 2642 2642 2643 2643 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2644 2644 qdev_prop_set_uint32(dev, "index", 0); 2645 2645 - qdev_realize_and_unref(dev, NULL, &error_fatal); 2645 2645 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2646 2646 2647 2647 return PCI_HOST_BRIDGE(dev); 2648 2648 }

+1 -1

hw/ppc/spapr_irq.c

··· 334 334 qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); 335 335 object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric", 336 336 &error_abort); 337 337 - qdev_realize_and_unref(dev, NULL, &error_fatal); 337 337 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 338 338 339 339 spapr->xive = SPAPR_XIVE(dev); 340 340

+1 -1

hw/ppc/spapr_vio.c

··· 577 577 578 578 /* Create bridge device */ 579 579 dev = qdev_new(TYPE_SPAPR_VIO_BRIDGE); 580 580 - qdev_realize_and_unref(dev, NULL, &error_fatal); 580 580 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 581 581 582 582 /* Create bus on bridge device */ 583 583 qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");

+2 -2

hw/ppc/virtex_ml507.c

··· 231 231 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; 232 232 dev = qdev_new("xlnx.xps-intc"); 233 233 qdev_prop_set_uint32(dev, "kind-of-intr", 0); 234 234 - qdev_realize_and_unref(dev, NULL, &error_fatal); 234 234 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 235 235 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 236 236 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); 237 237 for (i = 0; i < 32; i++) { ··· 245 245 dev = qdev_new("xlnx.xps-timer"); 246 246 qdev_prop_set_uint32(dev, "one-timer-only", 0); 247 247 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); 248 248 - qdev_realize_and_unref(dev, NULL, &error_fatal); 248 248 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 249 249 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 250 250 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 251 251

+1 -1

hw/riscv/sifive_clint.c

··· 252 252 qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); 253 253 qdev_prop_set_uint32(dev, "time-base", time_base); 254 254 qdev_prop_set_uint32(dev, "aperture-size", size); 255 255 - qdev_realize_and_unref(dev, NULL, &error_fatal); 255 255 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 256 256 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 257 257 return dev; 258 258 }

+1 -1

hw/riscv/sifive_e_prci.c

··· 119 119 DeviceState *sifive_e_prci_create(hwaddr addr) 120 120 { 121 121 DeviceState *dev = qdev_new(TYPE_SIFIVE_E_PRCI); 122 122 - qdev_realize_and_unref(dev, NULL, &error_fatal); 122 122 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 123 123 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 124 124 return dev; 125 125 }

+1 -1

hw/riscv/sifive_plic.c

··· 508 508 qdev_prop_set_uint32(dev, "context-base", context_base); 509 509 qdev_prop_set_uint32(dev, "context-stride", context_stride); 510 510 qdev_prop_set_uint32(dev, "aperture-size", aperture_size); 511 511 - qdev_realize_and_unref(dev, NULL, &error_fatal); 511 511 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 512 512 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 513 513 return dev; 514 514 }

+1 -1

hw/riscv/sifive_test.c

··· 94 94 DeviceState *sifive_test_create(hwaddr addr) 95 95 { 96 96 DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST); 97 97 - qdev_realize_and_unref(dev, NULL, &error_fatal); 97 97 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 98 98 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 99 99 return dev; 100 100 }

+2 -2

hw/riscv/virt.c

··· 114 114 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 115 115 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 116 116 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 117 117 - qdev_realize_and_unref(dev, NULL, &error_fatal); 117 117 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 118 118 119 119 memory_region_add_subregion(sysmem, base, 120 120 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), ··· 445 445 446 446 dev = qdev_new(TYPE_GPEX_HOST); 447 447 448 448 - qdev_realize_and_unref(dev, NULL, &error_fatal); 448 448 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 449 449 450 450 ecam_alias = g_new0(MemoryRegion, 1); 451 451 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

+1 -1

hw/rtc/m48t59.c

··· 582 582 583 583 dev = qdev_new(m48txx_sysbus_info[i].bus_name); 584 584 qdev_prop_set_int32(dev, "base-year", base_year); 585 585 - qdev_realize_and_unref(dev, NULL, &error_fatal); 586 585 s = SYS_BUS_DEVICE(dev); 586 586 + sysbus_realize_and_unref(s, &error_fatal); 587 587 sysbus_connect_irq(s, 0, IRQ); 588 588 if (io_base != 0) { 589 589 memory_region_add_subregion(get_system_io(), io_base,

+1 -1

hw/rtc/sun4v-rtc.c

··· 59 59 dev = qdev_new(TYPE_SUN4V_RTC); 60 60 s = SYS_BUS_DEVICE(dev); 61 61 62 62 - qdev_realize_and_unref(dev, NULL, &error_fatal); 62 62 + sysbus_realize_and_unref(s, &error_fatal); 63 63 64 64 sysbus_mmio_map(s, 0, addr); 65 65 }

+1 -1

hw/s390x/ap-bridge.c

··· 52 52 dev = qdev_new(TYPE_AP_BRIDGE); 53 53 object_property_add_child(qdev_get_machine(), TYPE_AP_BRIDGE, 54 54 OBJECT(dev)); 55 55 - qdev_realize_and_unref(dev, NULL, &error_fatal); 55 55 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 56 56 57 57 /* Create bus on bridge device */ 58 58 bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS);

+1 -1

hw/s390x/css-bridge.c

··· 104 104 dev = qdev_new(TYPE_VIRTUAL_CSS_BRIDGE); 105 105 object_property_add_child(qdev_get_machine(), TYPE_VIRTUAL_CSS_BRIDGE, 106 106 OBJECT(dev)); 107 107 - qdev_realize_and_unref(dev, NULL, &error_fatal); 107 107 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 108 108 109 109 /* Create bus on bridge device */ 110 110 bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");

+1 -1

hw/s390x/s390-virtio-ccw.c

··· 272 272 dev = qdev_new(TYPE_S390_PCI_HOST_BRIDGE); 273 273 object_property_add_child(qdev_get_machine(), TYPE_S390_PCI_HOST_BRIDGE, 274 274 OBJECT(dev)); 275 275 - qdev_realize_and_unref(dev, NULL, &error_fatal); 275 275 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 276 276 277 277 /* register hypercalls */ 278 278 virtio_ccw_register_hcalls();

+1 -1

hw/s390x/sclp.c

··· 338 338 * as we can't find a fitting bus via the qom tree, we have to add the 339 339 * event facility to the sysbus, so e.g. a sclp console can be created. 340 340 */ 341 341 - qdev_realize(DEVICE(sclp->event_facility), NULL, &err); 341 341 + sysbus_realize(SYS_BUS_DEVICE(sclp->event_facility), &err); 342 342 if (err) { 343 343 goto out; 344 344 }

+1 -1

hw/sd/pxa2xx_mmci.c

··· 492 492 sysbus_connect_irq(sbd, 0, irq); 493 493 qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma); 494 494 qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma); 495 495 - qdev_realize_and_unref(dev, NULL, &error_fatal); 495 495 + sysbus_realize_and_unref(sbd, &error_fatal); 496 496 497 497 /* Create and plug in the sd card */ 498 498 carddev = qdev_new(TYPE_SD_CARD);

+3 -3

hw/sh4/r2d.c

··· 259 259 260 260 dev = qdev_new("sh_pci"); 261 261 busdev = SYS_BUS_DEVICE(dev); 262 262 - qdev_realize_and_unref(dev, NULL, &error_fatal); 262 262 + sysbus_realize_and_unref(busdev, &error_fatal); 263 263 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); 264 264 sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000)); 265 265 sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000)); ··· 273 273 qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE); 274 274 qdev_prop_set_uint32(dev, "base", 0x10000000); 275 275 qdev_prop_set_chr(dev, "chardev", serial_hd(2)); 276 276 - qdev_realize_and_unref(dev, NULL, &error_fatal); 276 276 + sysbus_realize_and_unref(busdev, &error_fatal); 277 277 sysbus_mmio_map(busdev, 0, 0x10000000); 278 278 sysbus_mmio_map(busdev, 1, 0x13e00000); 279 279 sysbus_connect_irq(busdev, 0, irq[SM501]); ··· 284 284 busdev = SYS_BUS_DEVICE(dev); 285 285 sysbus_connect_irq(busdev, 0, irq[CF_IDE]); 286 286 qdev_prop_set_uint32(dev, "shift", 1); 287 287 - qdev_realize_and_unref(dev, NULL, &error_fatal); 287 287 + sysbus_realize_and_unref(busdev, &error_fatal); 288 288 sysbus_mmio_map(busdev, 0, 0x14001000); 289 289 sysbus_mmio_map(busdev, 1, 0x1400080c); 290 290 mmio_ide_init_drives(dev, dinfo, NULL);

+5 -5

hw/sparc/leon3.c

··· 214 214 qemu_register_reset(main_cpu_reset, reset_info); 215 215 216 216 ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP)); 217 217 - qdev_realize_and_unref(DEVICE(ahb_pnp), NULL, &error_fatal); 217 217 + sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal); 218 218 sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET); 219 219 grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER, 220 220 GRLIB_LEON3_DEV, GRLIB_AHB_MASTER, 221 221 GRLIB_CPU_AREA); 222 222 223 223 apb_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP)); 224 224 - qdev_realize_and_unref(DEVICE(apb_pnp), NULL, &error_fatal); 224 224 + sysbus_realize_and_unref(SYS_BUS_DEVICE(apb_pnp), &error_fatal); 225 225 sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET); 226 226 grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF, 227 227 GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV, ··· 233 233 env, "pil", 1); 234 234 qdev_connect_gpio_out_named(dev, "grlib-irq", 0, 235 235 qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0)); 236 236 - qdev_realize_and_unref(dev, NULL, &error_fatal); 236 236 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 237 237 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_IRQMP_OFFSET); 238 238 env->irq_manager = dev; 239 239 env->qemu_irq_ack = leon3_irq_manager; ··· 326 326 qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT); 327 327 qdev_prop_set_uint32(dev, "frequency", CPU_CLK); 328 328 qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ); 329 329 - qdev_realize_and_unref(dev, NULL, &error_fatal); 329 329 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 330 330 331 331 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET); 332 332 for (i = 0; i < LEON3_TIMER_COUNT; i++) { ··· 341 341 /* Allocate uart */ 342 342 dev = qdev_new(TYPE_GRLIB_APB_UART); 343 343 qdev_prop_set_chr(dev, "chrdev", serial_hd(0)); 344 344 - qdev_realize_and_unref(dev, NULL, &error_fatal); 344 344 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 345 345 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET); 346 346 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]); 347 347 grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,

+16 -16

hw/sparc/sun4m.c

··· 318 318 319 319 dev = qdev_new(TYPE_SUN4M_IOMMU); 320 320 qdev_prop_set_uint32(dev, "version", version); 321 321 - qdev_realize_and_unref(dev, NULL, &error_fatal); 322 321 s = SYS_BUS_DEVICE(dev); 322 322 + sysbus_realize_and_unref(s, &error_fatal); 323 323 sysbus_connect_irq(s, 0, irq); 324 324 sysbus_mmio_map(s, 0, addr); 325 325 ··· 337 337 SysBusPCNetState *lance; 338 338 339 339 dma = qdev_new(TYPE_SPARC32_DMA); 340 340 - qdev_realize_and_unref(dma, NULL, &error_fatal); 340 340 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 341 341 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 342 342 343 343 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( ··· 368 368 unsigned int i, j; 369 369 370 370 dev = qdev_new("slavio_intctl"); 371 371 - qdev_realize_and_unref(dev, NULL, &error_fatal); 372 371 373 372 s = SYS_BUS_DEVICE(dev); 373 373 + sysbus_realize_and_unref(s, &error_fatal); 374 374 375 375 for (i = 0; i < MAX_CPUS; i++) { 376 376 for (j = 0; j < MAX_PILS; j++) { ··· 397 397 398 398 dev = qdev_new("slavio_timer"); 399 399 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 400 400 - qdev_realize_and_unref(dev, NULL, &error_fatal); 401 400 s = SYS_BUS_DEVICE(dev); 401 401 + sysbus_realize_and_unref(s, &error_fatal); 402 402 sysbus_connect_irq(s, 0, master_irq); 403 403 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 404 404 ··· 434 434 SysBusDevice *s; 435 435 436 436 dev = qdev_new("slavio_misc"); 437 437 - qdev_realize_and_unref(dev, NULL, &error_fatal); 438 437 s = SYS_BUS_DEVICE(dev); 438 438 + sysbus_realize_and_unref(s, &error_fatal); 439 439 if (base) { 440 440 /* 8 bit registers */ 441 441 /* Slavio control */ ··· 472 472 473 473 dev = qdev_new("eccmemctl"); 474 474 qdev_prop_set_uint32(dev, "version", version); 475 475 - qdev_realize_and_unref(dev, NULL, &error_fatal); 476 475 s = SYS_BUS_DEVICE(dev); 476 476 + sysbus_realize_and_unref(s, &error_fatal); 477 477 sysbus_connect_irq(s, 0, irq); 478 478 sysbus_mmio_map(s, 0, base); 479 479 if (version == 0) { // SS-600MP only ··· 487 487 SysBusDevice *s; 488 488 489 489 dev = qdev_new("apc"); 490 490 - qdev_realize_and_unref(dev, NULL, &error_fatal); 491 490 s = SYS_BUS_DEVICE(dev); 491 491 + sysbus_realize_and_unref(s, &error_fatal); 492 492 /* Power management (APC) XXX: not a Slavio device */ 493 493 sysbus_mmio_map(s, 0, power_base); 494 494 sysbus_connect_irq(s, 0, cpu_halt); ··· 505 505 qdev_prop_set_uint16(dev, "width", width); 506 506 qdev_prop_set_uint16(dev, "height", height); 507 507 qdev_prop_set_uint16(dev, "depth", depth); 508 508 - qdev_realize_and_unref(dev, NULL, &error_fatal); 509 508 s = SYS_BUS_DEVICE(dev); 509 509 + sysbus_realize_and_unref(s, &error_fatal); 510 510 511 511 /* 10/ROM : FCode ROM */ 512 512 sysbus_mmio_map(s, 0, addr); ··· 557 557 qdev_prop_set_uint16(dev, "width", width); 558 558 qdev_prop_set_uint16(dev, "height", height); 559 559 qdev_prop_set_uint16(dev, "depth", depth); 560 560 - qdev_realize_and_unref(dev, NULL, &error_fatal); 561 560 s = SYS_BUS_DEVICE(dev); 561 561 + sysbus_realize_and_unref(s, &error_fatal); 562 562 563 563 /* FCode ROM */ 564 564 sysbus_mmio_map(s, 0, addr); ··· 582 582 SysBusDevice *s; 583 583 584 584 dev = qdev_new(TYPE_MACIO_ID_REGISTER); 585 585 - qdev_realize_and_unref(dev, NULL, &error_fatal); 586 585 s = SYS_BUS_DEVICE(dev); 586 586 + sysbus_realize_and_unref(s, &error_fatal); 587 587 588 588 sysbus_mmio_map(s, 0, addr); 589 589 address_space_write_rom(&address_space_memory, addr, ··· 648 648 SysBusDevice *s; 649 649 650 650 dev = qdev_new(TYPE_TCX_AFX); 651 651 - qdev_realize_and_unref(dev, NULL, &error_fatal); 652 651 s = SYS_BUS_DEVICE(dev); 652 652 + sysbus_realize_and_unref(s, &error_fatal); 653 653 654 654 sysbus_mmio_map(s, 0, addr); 655 655 } ··· 709 709 int ret; 710 710 711 711 dev = qdev_new(TYPE_OPENPROM); 712 712 - qdev_realize_and_unref(dev, NULL, &error_fatal); 713 712 s = SYS_BUS_DEVICE(dev); 713 713 + sysbus_realize_and_unref(s, &error_fatal); 714 714 715 715 sysbus_mmio_map(s, 0, addr); 716 716 ··· 879 879 /* Create and map RAM frontend */ 880 880 dev = qdev_new("memory"); 881 881 object_property_set_link(OBJECT(dev), ram_memdev, "memdev", &error_fatal); 882 882 - qdev_realize_and_unref(dev, NULL, &error_fatal); 882 882 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 883 883 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 884 884 885 885 /* models without ECC don't trap when missing ram is accessed */ ··· 990 990 qdev_prop_set_chr(dev, "chrA", NULL); 991 991 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 992 992 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 993 993 - qdev_realize_and_unref(dev, NULL, &error_fatal); 994 993 s = SYS_BUS_DEVICE(dev); 994 994 + sysbus_realize_and_unref(s, &error_fatal); 995 995 sysbus_connect_irq(s, 0, slavio_irq[14]); 996 996 sysbus_connect_irq(s, 1, slavio_irq[14]); 997 997 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); ··· 1004 1004 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 1005 1005 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 1006 1006 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 1007 1007 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1008 1007 1009 1008 s = SYS_BUS_DEVICE(dev); 1009 1009 + sysbus_realize_and_unref(s, &error_fatal); 1010 1010 sysbus_connect_irq(s, 0, slavio_irq[15]); 1011 1011 sysbus_connect_irq(s, 1, slavio_irq[15]); 1012 1012 sysbus_mmio_map(s, 0, hwdef->serial_base); ··· 1068 1068 qdev_prop_set_bit(dev, "dma_enabled", false); 1069 1069 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1070 1070 OBJECT(fw_cfg)); 1071 1071 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1072 1071 s = SYS_BUS_DEVICE(dev); 1072 1072 + sysbus_realize_and_unref(s, &error_fatal); 1073 1073 sysbus_mmio_map(s, 0, CFG_ADDR); 1074 1074 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1075 1075

+6 -6

hw/sparc64/sun4u.c

··· 354 354 355 355 /* Power */ 356 356 dev = qdev_new(TYPE_SUN4U_POWER); 357 357 - qdev_realize_and_unref(dev, NULL, &error_fatal); 358 357 sbd = SYS_BUS_DEVICE(dev); 358 358 + sysbus_realize_and_unref(sbd, &error_fatal); 359 359 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, 360 360 sysbus_mmio_get_region(sbd, 0)); 361 361 ··· 429 429 int ret; 430 430 431 431 dev = qdev_new(TYPE_OPENPROM); 432 432 - qdev_realize_and_unref(dev, NULL, &error_fatal); 433 432 s = SYS_BUS_DEVICE(dev); 433 433 + sysbus_realize_and_unref(s, &error_fatal); 434 434 435 435 sysbus_mmio_map(s, 0, addr); 436 436 ··· 527 527 528 528 d = SUN4U_RAM(dev); 529 529 d->size = RAM_size; 530 530 - qdev_realize_and_unref(dev, NULL, &error_fatal); 530 530 + sysbus_realize_and_unref(s, &error_fatal); 531 531 532 532 sysbus_mmio_map(s, 0, addr); 533 533 } ··· 575 575 576 576 /* IOMMU */ 577 577 iommu = qdev_new(TYPE_SUN4U_IOMMU); 578 578 - qdev_realize_and_unref(iommu, NULL, &error_fatal); 578 578 + sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal); 579 579 580 580 /* set up devices */ 581 581 ram_init(0, machine->ram_size); ··· 588 588 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); 589 589 object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", 590 590 &error_abort); 591 591 - qdev_realize_and_unref(DEVICE(sabre), NULL, &error_fatal); 591 591 + sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal); 592 592 593 593 /* Wire up PCI interrupts to CPU */ 594 594 for (i = 0; i < IVEC_MAX; i++) { ··· 698 698 dev = qdev_new(TYPE_FW_CFG_IO); 699 699 qdev_prop_set_bit(dev, "dma_enabled", false); 700 700 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev)); 701 701 - qdev_realize_and_unref(dev, NULL, &error_fatal); 701 701 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 702 702 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 703 703 &FW_CFG_IO(dev)->comb_iomem); 704 704

+1 -1

hw/xen/xen-bus.c

··· 1390 1390 DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE); 1391 1391 BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL); 1392 1392 1393 1393 - qdev_realize_and_unref(dev, NULL, &error_fatal); 1393 1393 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1394 1394 qbus_set_bus_hotplug_handler(bus, &error_abort); 1395 1395 }

+1 -1

hw/xen/xen-legacy-backend.c

··· 703 703 } 704 704 705 705 xen_sysdev = qdev_new(TYPE_XENSYSDEV); 706 706 - qdev_realize_and_unref(xen_sysdev, NULL, &error_fatal); 706 706 + sysbus_realize_and_unref(SYS_BUS_DEVICE(xen_sysdev), &error_fatal); 707 707 xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus"); 708 708 qbus_set_bus_hotplug_handler(xen_sysbus, &error_abort); 709 709

+1 -1

hw/xtensa/virt.c

··· 63 63 int i; 64 64 65 65 dev = qdev_new(TYPE_GPEX_HOST); 66 66 - qdev_realize_and_unref(dev, NULL, &error_fatal); 66 66 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 67 67 68 68 /* Map only the first size_ecam bytes of ECAM space. */ 69 69 ecam_alias = g_new0(MemoryRegion, 1);

+2 -2

hw/xtensa/xtfpga.c

··· 150 150 151 151 dev = qdev_new("open_eth"); 152 152 qdev_set_nic_properties(dev, nd); 153 153 - qdev_realize_and_unref(dev, NULL, &error_fatal); 154 153 155 154 s = SYS_BUS_DEVICE(dev); 155 155 + sysbus_realize_and_unref(s, &error_fatal); 156 156 sysbus_connect_irq(s, 0, irq); 157 157 memory_region_add_subregion(address_space, base, 158 158 sysbus_mmio_get_region(s, 0)); ··· 181 181 qdev_prop_set_uint8(dev, "width", 2); 182 182 qdev_prop_set_bit(dev, "big-endian", be); 183 183 qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 184 184 - qdev_realize_and_unref(dev, NULL, &error_fatal); 185 184 s = SYS_BUS_DEVICE(dev); 185 185 + sysbus_realize_and_unref(s, &error_fatal); 186 186 memory_region_add_subregion(address_space, board->flash->base, 187 187 sysbus_mmio_get_region(s, 0)); 188 188 return PFLASH_CFI01(dev);

+1 -1

include/hw/char/cadence_uart.h

··· 63 63 dev = qdev_new(TYPE_CADENCE_UART); 64 64 s = SYS_BUS_DEVICE(dev); 65 65 qdev_prop_set_chr(dev, "chardev", chr); 66 66 - qdev_realize_and_unref(dev, NULL, &error_fatal); 66 66 + sysbus_realize_and_unref(s, &error_fatal); 67 67 sysbus_mmio_map(s, 0, addr); 68 68 sysbus_connect_irq(s, 0, irq); 69 69

+1 -1

include/hw/char/cmsdk-apb-uart.h

··· 66 66 s = SYS_BUS_DEVICE(dev); 67 67 qdev_prop_set_chr(dev, "chardev", chr); 68 68 qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); 69 69 - qdev_realize_and_unref(dev, NULL, &error_fatal); 69 69 + sysbus_realize_and_unref(s, &error_fatal); 70 70 sysbus_mmio_map(s, 0, addr); 71 71 sysbus_connect_irq(s, 0, txint); 72 72 sysbus_connect_irq(s, 1, rxint);

+2 -2

include/hw/char/pl011.h

··· 61 61 dev = qdev_new("pl011"); 62 62 s = SYS_BUS_DEVICE(dev); 63 63 qdev_prop_set_chr(dev, "chardev", chr); 64 64 - qdev_realize_and_unref(dev, NULL, &error_fatal); 64 64 + sysbus_realize_and_unref(s, &error_fatal); 65 65 sysbus_mmio_map(s, 0, addr); 66 66 sysbus_connect_irq(s, 0, irq); 67 67 ··· 78 78 dev = qdev_new("pl011_luminary"); 79 79 s = SYS_BUS_DEVICE(dev); 80 80 qdev_prop_set_chr(dev, "chardev", chr); 81 81 - qdev_realize_and_unref(dev, NULL, &error_fatal); 81 81 + sysbus_realize_and_unref(s, &error_fatal); 82 82 sysbus_mmio_map(s, 0, addr); 83 83 sysbus_connect_irq(s, 0, irq); 84 84

+1 -1

include/hw/char/xilinx_uartlite.h

··· 28 28 dev = qdev_new("xlnx.xps-uartlite"); 29 29 s = SYS_BUS_DEVICE(dev); 30 30 qdev_prop_set_chr(dev, "chardev", chr); 31 31 - qdev_realize_and_unref(dev, NULL, &error_fatal); 31 31 + sysbus_realize_and_unref(s, &error_fatal); 32 32 sysbus_mmio_map(s, 0, addr); 33 33 sysbus_connect_irq(s, 0, irq); 34 34

+1 -1

include/hw/cris/etraxfs.h

··· 44 44 dev = qdev_new("etraxfs,serial"); 45 45 s = SYS_BUS_DEVICE(dev); 46 46 qdev_prop_set_chr(dev, "chardev", chr); 47 47 - qdev_realize_and_unref(dev, NULL, &error_fatal); 47 47 + sysbus_realize_and_unref(s, &error_fatal); 48 48 sysbus_mmio_map(s, 0, addr); 49 49 sysbus_connect_irq(s, 0, irq); 50 50 return dev;

+1 -1

include/hw/misc/unimp.h

··· 45 45 46 46 qdev_prop_set_string(dev, "name", name); 47 47 qdev_prop_set_uint64(dev, "size", size); 48 48 - qdev_realize_and_unref(dev, NULL, &error_fatal); 48 48 + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 49 49 50 50 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000); 51 51 }

+1 -1

include/hw/timer/cmsdk-apb-timer.h

··· 51 51 dev = qdev_new(TYPE_CMSDK_APB_TIMER); 52 52 s = SYS_BUS_DEVICE(dev); 53 53 qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); 54 54 - qdev_realize_and_unref(dev, NULL, &error_fatal); 54 54 + sysbus_realize_and_unref(s, &error_fatal); 55 55 sysbus_mmio_map(s, 0, addr); 56 56 sysbus_connect_irq(s, 0, timerint); 57 57 return dev;