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qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs

In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.

"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"

Integer stores of all sizes are allowed with these ASIs.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>

Artyom Tarasenko 3390537b 7285fba0

+11
+11
target/sparc/translate.c
··· 2321 2321 case GET_ASI_EXCP: 2322 2322 break; 2323 2323 case GET_ASI_DTWINX: /* Reserved for stda. */ 2324 + #ifndef TARGET_SPARC64 2324 2325 gen_exception(dc, TT_ILL_INSN); 2325 2326 break; 2327 + #else 2328 + if (!(dc->def->features & CPU_FEATURE_HYPV)) { 2329 + /* Pre OpenSPARC CPUs don't have these */ 2330 + gen_exception(dc, TT_ILL_INSN); 2331 + return; 2332 + } 2333 + /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions 2334 + * are ST_BLKINIT_ ASIs */ 2335 + /* fall through */ 2336 + #endif 2326 2337 case GET_ASI_DIRECT: 2327 2338 gen_address_mask(dc, addr); 2328 2339 tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);