target/arm: Cache the Tagged bit for a page in MemTxAttrs

qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

This "bit" is a particular value of the page's MemAttr.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

authored by

Richard Henderson and committed by

Peter Maydell 5 years ago 337a03f0 7e98e21c

+50 -3

2 changed files

expand all

target

arm

helper.c

tlb_helper.c

+45 -3

target/arm/helper.c

··· 11834 11834 */ 11835 11835 static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) 11836 11836 { 11837 - uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4); 11838 - uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4); 11837 + uint8_t s1lo, s2lo, s1hi, s2hi; 11839 11838 ARMCacheAttrs ret; 11839 + bool tagged = false; 11840 + 11841 + if (s1.attrs == 0xf0) { 11842 + tagged = true; 11843 + s1.attrs = 0xff; 11844 + } 11845 + 11846 + s1lo = extract32(s1.attrs, 0, 4); 11847 + s2lo = extract32(s2.attrs, 0, 4); 11848 + s1hi = extract32(s1.attrs, 4, 4); 11849 + s2hi = extract32(s2.attrs, 4, 4); 11840 11850 11841 11851 /* Combine shareability attributes (table D4-43) */ 11842 11852 if (s1.shareability == 2 || s2.shareability == 2) { ··· 11882 11892 */ 11883 11893 ret.shareability = 2; 11884 11894 } 11895 + } 11896 + 11897 + /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ 11898 + if (tagged && ret.attrs == 0xff) { 11899 + ret.attrs = 0xf0; 11885 11900 } 11886 11901 11887 11902 return ret; ··· 11963 11978 * Normal Non-Shareable, 11964 11979 * Inner Write-Back Read-Allocate Write-Allocate, 11965 11980 * Outer Write-Back Read-Allocate Write-Allocate. 11981 + * Do not overwrite Tagged within attrs. 11966 11982 */ 11967 - cacheattrs->attrs = 0xff; 11983 + if (cacheattrs->attrs != 0xf0) { 11984 + cacheattrs->attrs = 0xff; 11985 + } 11968 11986 cacheattrs->shareability = 0; 11969 11987 } 11970 11988 *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); ··· 12029 12047 /* Definitely a real MMU, not an MPU */ 12030 12048 12031 12049 if (regime_translation_disabled(env, mmu_idx)) { 12050 + uint64_t hcr; 12051 + uint8_t memattr; 12052 + 12032 12053 /* 12033 12054 * MMU disabled. S1 addresses within aa64 translation regimes are 12034 12055 * still checked for bounds -- see AArch64.TranslateAddressS1Off. ··· 12066 12087 *phys_ptr = address; 12067 12088 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 12068 12089 *page_size = TARGET_PAGE_SIZE; 12090 + 12091 + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ 12092 + hcr = arm_hcr_el2_eff(env); 12093 + cacheattrs->shareability = 0; 12094 + if (hcr & HCR_DC) { 12095 + if (hcr & HCR_DCT) { 12096 + memattr = 0xf0; /* Tagged, Normal, WB, RWA */ 12097 + } else { 12098 + memattr = 0xff; /* Normal, WB, RWA */ 12099 + } 12100 + } else if (access_type == MMU_INST_FETCH) { 12101 + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { 12102 + memattr = 0xee; /* Normal, WT, RA, NT */ 12103 + } else { 12104 + memattr = 0x44; /* Normal, NC, No */ 12105 + } 12106 + cacheattrs->shareability = 2; /* outer sharable */ 12107 + } else { 12108 + memattr = 0x00; /* Device, nGnRnE */ 12109 + } 12110 + cacheattrs->attrs = memattr; 12069 12111 return 0; 12070 12112 } 12071 12113

target/arm/tlb_helper.c

··· 188 188 phys_addr &= TARGET_PAGE_MASK; 189 189 address &= TARGET_PAGE_MASK; 190 190 } 191 + /* Notice and record tagged memory. */ 192 + if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) { 193 + arm_tlb_mte_tagged(&attrs) = true; 194 + } 195 + 191 196 tlb_set_page_with_attrs(cs, address, phys_addr, attrs, 192 197 prot, mmu_idx, page_size); 193 198 return true;