target/riscv: vector compress instruction

qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-61-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

authored by

LIU Zhiwei and committed by

Alistair Francis 5 years ago 31bf42a2 e4b83d5c

+64

4 changed files

expand all

target

riscv

helper.h

insn32.decode

insn_trans

trans_rvv.inc.c

vector_helper.c

target/riscv/helper.h

··· 1145 1145 DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32) 1146 1146 DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32) 1147 1147 DEF_HELPER_6(vrgather_vx_d, void, ptr, ptr, tl, ptr, env, i32) 1148 + 1149 + DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32) 1150 + DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) 1151 + DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) 1152 + DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)

target/riscv/insn32.decode

··· 577 577 vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm 578 578 vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm 579 579 vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm 580 + vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r 580 581 581 582 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm 582 583 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

+32

target/riscv/insn_trans/trans_rvv.inc.c

··· 2854 2854 } 2855 2855 return true; 2856 2856 } 2857 + 2858 + /* Vector Compress Instruction */ 2859 + static bool vcompress_vm_check(DisasContext *s, arg_r *a) 2860 + { 2861 + return (vext_check_isa_ill(s) && 2862 + vext_check_reg(s, a->rd, false) && 2863 + vext_check_reg(s, a->rs2, false) && 2864 + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) && 2865 + (a->rd != a->rs2)); 2866 + } 2867 + 2868 + static bool trans_vcompress_vm(DisasContext *s, arg_r *a) 2869 + { 2870 + if (vcompress_vm_check(s, a)) { 2871 + uint32_t data = 0; 2872 + static gen_helper_gvec_4_ptr * const fns[4] = { 2873 + gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h, 2874 + gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d, 2875 + }; 2876 + TCGLabel *over = gen_new_label(); 2877 + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); 2878 + 2879 + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); 2880 + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); 2881 + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), 2882 + vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), 2883 + cpu_env, 0, s->vlen / 8, data, fns[s->sew]); 2884 + gen_set_label(over); 2885 + return true; 2886 + } 2887 + return false; 2888 + }

+26

target/riscv/vector_helper.c

··· 4871 4871 GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2, clearh) 4872 4872 GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4, clearl) 4873 4873 GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq) 4874 + 4875 + /* Vector Compress Instruction */ 4876 + #define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H, CLEAR_FN) \ 4877 + void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 4878 + CPURISCVState *env, uint32_t desc) \ 4879 + { \ 4880 + uint32_t mlen = vext_mlen(desc); \ 4881 + uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ 4882 + uint32_t vl = env->vl; \ 4883 + uint32_t num = 0, i; \ 4884 + \ 4885 + for (i = 0; i < vl; i++) { \ 4886 + if (!vext_elem_mask(vs1, mlen, i)) { \ 4887 + continue; \ 4888 + } \ 4889 + *((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \ 4890 + num++; \ 4891 + } \ 4892 + CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ 4893 + } 4894 + 4895 + /* Compress into vd elements of vs2 where vs1 is enabled */ 4896 + GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, clearb) 4897 + GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh) 4898 + GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl) 4899 + GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq)