jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/mips: Style improvements in cp0_timer.c
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1566216496-17375-7-git-send-email-aleksandar.markovic@rt-rk.com>
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-19
+23
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target/mips/cp0_timer.c
+23
-19
target/mips/cp0_timer.c
···
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#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
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/* XXX: do not use a global */
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-
uint32_t cpu_mips_get_random (CPUMIPSState *env)
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+
uint32_t cpu_mips_get_random(CPUMIPSState *env)
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{
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static uint32_t seed = 1;
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static uint32_t prev_idx = 0;
···
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/* Don't return same value twice, so get another value */
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do {
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/* Use a simple algorithm of Linear Congruential Generator
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* from ISO/IEC 9899 standard. */
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/*
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* Use a simple algorithm of Linear Congruential Generator
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* from ISO/IEC 9899 standard.
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*/
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seed = 1103515245 * seed + 12345;
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idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
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} while (idx == prev_idx);
···
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qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
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}
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-
uint32_t cpu_mips_get_count (CPUMIPSState *env)
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uint32_t cpu_mips_get_count(CPUMIPSState *env)
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{
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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return env->CP0_Count;
···
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}
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}
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-
void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
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void cpu_mips_store_count(CPUMIPSState *env, uint32_t count)
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{
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/*
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* This gets called from cpu_state_reset(), potentially before timer init.
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* So env->timer may be NULL, which is also the case with KVM enabled so
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* treat timer as disabled in that case.
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*/
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if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer)
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if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) {
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env->CP0_Count = count;
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-
else {
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} else {
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/* Store new count register */
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env->CP0_Count = count -
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(uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
···
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}
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}
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-
void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
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void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
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{
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env->CP0_Compare = value;
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if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
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if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
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cpu_mips_timer_update(env);
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if (env->insn_flags & ISA_MIPS32R2)
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}
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if (env->insn_flags & ISA_MIPS32R2) {
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env->CP0_Cause &= ~(1 << CP0Ca_TI);
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}
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qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
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}
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···
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TIMER_PERIOD);
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}
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static void mips_timer_cb (void *opaque)
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static void mips_timer_cb(void *opaque)
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{
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CPUMIPSState *env;
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env = opaque;
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#if 0
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qemu_log("%s\n", __func__);
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#endif
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if (env->CP0_Cause & (1 << CP0Ca_DC))
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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return;
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}
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/* ??? This callback should occur when the counter is exactly equal to
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the comparator value. Offset the count by one to avoid immediately
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retriggering the callback before any virtual time has passed. */
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/*
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* ??? This callback should occur when the counter is exactly equal to
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* the comparator value. Offset the count by one to avoid immediately
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* retriggering the callback before any virtual time has passed.
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*/
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env->CP0_Count++;
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cpu_mips_timer_expire(env);
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env->CP0_Count--;
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}
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-
void cpu_mips_clock_init (MIPSCPU *cpu)
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+
void cpu_mips_clock_init(MIPSCPU *cpu)
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{
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CPUMIPSState *env = &cpu->env;
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